CN113451426A - 具有相邻阳极-阴极对的光电探测器 - Google Patents

具有相邻阳极-阴极对的光电探测器 Download PDF

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CN113451426A
CN113451426A CN202110212216.4A CN202110212216A CN113451426A CN 113451426 A CN113451426 A CN 113451426A CN 202110212216 A CN202110212216 A CN 202110212216A CN 113451426 A CN113451426 A CN 113451426A
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semiconductor layer
doped region
light absorbing
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卞宇生
米歇尔·拉科斯基
李袁熙
阿西夫·乔杜里
A·P·雅各布
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GlobalFoundries US Inc
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Abstract

本发明涉及具有相邻阳极‑阴极对的光电探测器,揭示一种用于光电探测器的结构以及制造用于光电探测器的结构的方法。该结构包括具有侧边的光吸收区域,相邻于该光吸收区域的该侧边的阳极,以及相邻于该光吸收区域的该侧边的阴极。

Description

具有相邻阳极-阴极对的光电探测器
技术领域
本发明涉及光子(photonics)芯片,更具体而言,涉及用于光电探测器(photodetector)的结构和制造用于光电探测器的结构的方法。
背景技术
光子芯片用于许多应用和系统,如数据通信系统和数据计算系统。光子芯片将光学组件(如波导管和光开关)和电子组件(如场效应晶体管)集成到一个统一的平台中。在其他因素中,可以通过两种类型的组件的集成来减少布局面积、成本和运营开销。
光子芯片包括将调制光转换为电信号的探测器。常见的探测器是由如锗等材料组成的光电探测器,其特点是在红外波长范围内具有高吸收。当电磁辐射的光子被锗吸收时,锗光电探测器将调制的光脉冲转换成电流。
需要改进的用于光电探测器的结构和制造用于光电探测器的结构的方法。
发明内容
于本发明的一实施例中,提供一种用于光电探测器的结构。该结构包括具有侧边的光吸收区域,相邻于该光吸收区域的该侧边的阳极,以及相邻于该光吸收区域的该侧边的阴极。
于本发明的一实施例中,提供一种形成用于光电探测器的结构的方法。该方法包括形成光吸收区域,形成相邻于该光吸收区域的该侧边的阳极,以及形成相邻于该光吸收区域的该侧边的阴极。
附图说明
并入本说明书并构成本说明书一部分的附图说明了本发明的各种实施例,并且与上面给出的本发明的一般描述和下面给出的实施例的详细描述一起,用于解释本发明的实施例。在附图中,相似标号是指各种视图中的相似特征。
图1为根据本发明的实施例所示的处理方法的初始制造阶段的结构的俯视图。
图2为图1沿线2-2所示的横截面图。
图3为在图1之后的处理方法的制造阶段的结构的俯视图。
图4为沿图3的线4-4所示的横截面图。
图5为在图3之后的处理方法的制造阶段的结构的俯视图。
图6为沿图5的线6-6所示的横截面图。
图7为在图5之后的处理方法的制造阶段的结构的俯视图。
图8为沿图7的线8-8所示的横截面图。
图8A为沿图7的线8A-8A所示的横截面图。
图9为在图7之后的处理方法的制造阶段的结构的俯视图。
图10为沿图9的线10-10所示的横截面图。
图10A为沿图9的线10A-10A所示的横截面图。
图11为在图9之后的处理方法的制造阶段的结构的俯视图。
图12和图13为根据本发明的替换实施例的结构的俯视图。
附图标记说明
10 基板
11 顶面
12 设备层
14 埋置绝缘层
16 处理晶圆
17,17a,17b 浅沟槽隔离区域
18,18a,18b 浅沟槽隔离区域
20 介电层
21 开口
22 沟槽
24 层
25 侧边
26,26a 掺杂区域
27 侧边
28,28a 掺杂区域
30 植入掩模
32,32a 掺杂区域
34,34a 掺杂区域
35 开口
36 植入掩模
37 开口
38 波导管
40 触点
42 触点。
具体实施方式
参考图1、图2,根据本发明的实施例中,绝缘体上半导体(semiconductor-on-insulator;SOI)基板中的具有代表性形式的基板10包括定义半导体层的设备层(devicelayer)12、埋置绝缘层14和处理晶圆(handle wafer)16。设备层12通过中间的埋置绝缘层14与处理晶圆16分离,并且可以比处理晶圆16薄得多。设备层12和处理晶圆16可以由单晶半导体材料(例如单晶硅)构成,并且可以轻掺杂以具有例如p型导电性。埋置绝缘层14可以由诸如二氧化硅之类的介电材料构成。设备层12通过埋置绝缘层14与处理晶圆16电性隔离。
浅沟槽隔离区域17、18可通过蚀刻设备层12中的沟槽,在沟槽中沉积介电材料(如二氧化硅),并利用化学机械抛光进行平坦化来形成。浅沟槽隔离区域17、18可完全穿过设备层12到达埋置绝缘层14。
参考图3、图4,其中相同的附图标记表示图1、图2中的相似特征。在随后的制造阶段,在基板10的顶面11上沉积介电层20,并且通过光刻和蚀刻工艺图案化以定义窗口(window)或开口21。介电层20可由介电材料(例如氮化硅)构成。完全穿透介电层20到设备层12的开口21暴露在设备层12的顶面11上的区域。介电层20中的开口21可以横向位于浅沟槽隔离区域17和浅沟槽隔离区域18之间。
在设备层12中形成部分穿过设备层12的沟槽22,沟槽22可由蚀刻工艺形成,例如反应离子蚀刻工艺。图案化的介电层20在蚀刻工艺期间起到蚀刻掩模的作用,并且图案化的介电层20中的开口21定义了沟槽22在设备层12中的位置。设备层12的表面与沟槽22接界(border)。
参考图5、图6,其中相同的附图标记表示图3、图4中的相似特征。在随后的制造阶段,在沟槽22内沉积含有光吸收材料的层24并且定义光电探测器的光吸收区域。在一实施例中,层24可以具有包括锗的组合物。在一实施例中,层24可以由元素锗组成。在一实施例中,沟槽22和沟槽22内的层24可以从浅沟槽隔离区域17延伸到浅沟槽隔离区域18。层24包括定义光吸收区域的宽度的相对侧边25、27以及连接侧边25、27的端部。浅沟槽隔离区域17终止于层24的侧边25,且浅沟槽隔离区域18终止于层24的侧边27。
在一实施例中,可以选择性地沉积层24,使得材料不会沉积在介电层20的介电材料上。在一实施例中,与沟槽22接界的设备层12的表面可以执行表面处理工艺,然后进行锗的化学气相沉积,锗只在设备层12的半导体表面暴露的位置生长,导致选择性沉积和穿线位错(threading dislocation)密度的最小化。
参考图7、图8、图8A,其中相同的附图标记表示图5、图6中的相似特征。在随后的制造阶段,在设备层12的各个部分中形成掺杂区域26和掺杂区域28。在一实施例中,掺杂区域26、28可穿过设备层12的整个厚度延伸至埋置绝缘层14。具体而言,掺杂区域26、28可以从设备层12的顶面完全穿过设备层12延伸到设备层12和埋置绝缘层14之间的界面。层24可以横向设置在掺杂区域26和掺杂区域28之间的侧边25、27处。浅沟槽隔离区域17、18沿平行于层24的侧边25、27的方向为掺杂区域26、28定义各自的边界。
掺杂区域26,28可以例如通过离子植入形成,植入掩模(implantation mask)30覆盖在设备层12上的区域,以确定用于掺杂区域26、28的设备层12的植入区域。植入掩模30可以包括一层感光材料(例如光刻胶),通过旋涂工艺,预焙,暴露于通过光掩模投射的光,曝光后烘烤,并用化学显影剂显影以定义开口35来实现。植入掩模30中的开口35设置在要植入的设备层12的区域上方,并且植入掩模30中的每个开口35可以与浅沟槽隔离区域17、18在一侧重叠。可以选择植入条件(例如,离子种类、剂量、动能)来调节掺杂区域26、28的电性特征和物理特性。植入掩模30可以在形成掺杂区域26、28之后被剥离。
在一实施例中,层24的各个部分可以被植入,使得掺杂区域26、28的部分(portion)位于层24中,如图8、图8A中的虚线所示。层24的同时植入可以通过使植入掩模30中的每个开口35在其内部边缘处与层24稍微重叠,使得开口35向内延伸超过层24的侧边25、27来提供。在一实施例中,掺杂区域26、28的半导体材料可掺杂提供p型导电性的p型掺杂剂(例如,硼)。在一实施例中,可适度掺杂该掺杂区域26、28以包含等于约1x1017 atoms/cm3到约5x1018 atoms/cm3的范围内的掺杂浓度。
参考图9、图10、图10A,其中相同的附图标记表示图7、图8、图8A中的相似特征。在随后的制造阶段,在设备层12的与包含掺杂区域26、28的设备层12的部分不一致的各个部分中形成掺杂区域32和掺杂区域34。在一实施例中,掺杂区域32、34可以延伸穿过设备层12的整个厚度直至埋置绝缘层14。具体地,掺杂区域32、34可以从设备层12的顶面延伸完全穿过设备层12到达设备层12与埋置绝缘层14之间的界面。浅沟槽隔离区域17、18在平行于层24的侧边25、27的方向上定义掺杂区域32、34的各自的边界。
掺杂区域32、34可以例如通过离子植入形成,植入掩模36覆盖设备层12上方的区域,以确定用于掺杂区域32、34的设备层12的植入区域。植入掩模36可以包括一层感光材料,例如光刻胶,通过旋涂工艺,预焙,暴露于通过光掩模投射的光,曝光后烘烤,并用化学显影剂显影以定义开口37来执行。植入掩模36中的开口37设置在要植入的设备层12的区域上,并且植入掩模36中的每个开口37可以在一侧与浅沟槽隔离区域17、18重叠。植入掩模36覆盖包含掺杂区域26、28的设备层12的部分。可以选择植入条件(例如,离子种类、剂量、动能)来调节掺杂区域32、34的电性特征和物理特性。在形成掺杂区域32、34之后,可以剥离植入掩模36。
在一实施例中,可以在层24的各个部分植入,使得掺杂区域32、34的部分可以位于层24中,如图10、图10A中的虚线所示。层24的同时植入可以通过在植入掩模36中的每个开口37在内边缘处与层24稍微重叠,使得这些开口37向内延伸超过层24的侧边25、27来提供。掺杂区域32、34被掺杂以具有与掺杂区域26、28相反的导电类型。在一实施例中,掺杂区域32、34的半导体材料可掺杂提供n型导电性的n型掺杂剂(例如,磷和/或砷)。在一实施例中,可适度掺杂该掺杂区域32、34以包含等于约1x1017 atoms/cm3到约5x1018 atoms/cm3的范围内的掺杂浓度。
掺杂区域26沿着层24的侧边25位于浅沟槽隔离区域17的与掺杂区域32相反的一侧。掺杂区域28沿层24的侧边27位于浅沟槽隔离区域18的与掺杂区域34的相反的一侧。层24可以横向定位在掺杂区域26、32和掺杂区域28、34之间。层24的侧边25相邻于掺杂区域26、32和浅沟槽隔离区域17,且层24的侧边27相邻于掺杂区域26、32和浅沟槽隔离区域18。
参考图11,其中相同的附图标记表示图9、图10和图10A中的相同特征,并在随后的制造阶段,形成耦合到层24的波导管(waveguide)38。波导管38将光引导到层24以转换成电信号。可以通过利用光刻和蚀刻工艺图案化设备层12来形成波导管38。
随后进行中段工艺(middle-of-line;MOL)和后段工艺(back-end-of-line;BEOL),其包括硅化物、触点(contact)、通孔和用于与光电探测器耦合的互连结构的布线的形成。特别地,以虚线示意性地示出了到掺杂区域26、28的触点40和到掺杂区域32、34的触点42。可以在掺杂区域26、28和掺杂区域32、34中提供重掺杂区域(未示出),并且可以降低接触电阻。层24不接触互连结构的触点。
完成的光电探测器包括作为阴极的掺杂区域26、28,作为阳极的掺杂区域32、34,以及作为光吸收区域的层24。浅沟槽隔离区域17横向位于由掺杂区域26表示的阴极和由掺杂区域32表示的阳极之间。浅沟槽隔离区域18横向位于由掺杂区域28表示的阴极和由掺杂区域34表示的阳极之间。层24横向位于表示阳极-阴极对(anode-cathode pair)的掺杂区域26、32和同样代表阳极-阴极对的掺杂区域28、34之间。
在使用中,激光被波导管38引导到吸收光子的层24。偏压阳极提供高电场的增殖区域。结(junction)在靠近浅沟槽隔离区域17、18的位置延伸到层24,并且在这些位置发生雪崩(avalanche)效应,其特征是高电场。
沿光吸收区域的相对侧边设置阳极-阴极对可以降低光电探测器的工作电压,提高光电探测器的增益,减小光电探测器的电容,并提高光电探测器的带宽(bandwidth)。光探测器的击穿电压可于不在光吸收区域上放置触点而降低。光电探测器的结构易于与低压CMOS技术集成。光电探测器的结构可以在低工作电压下表现出高雪崩增益。靠近浅沟槽隔离区域17、18的附加电场可加速电荷载流子,从而在不减少载流子渡越时间的情况下拓宽光吸收区域,可以提高量子效率,并且可以提高响应度。
参考图12,其中类似标号表示图11中的类似特征,并且根据替代实施例,可以通过添加附加掺杂区域26a、28a和附加掺杂区域32a,34a来修改光电探测器以增加阳极-阴极对的数量。附加的浅沟槽隔离区域17a、17b和18a、18b也位于设备层12中,以提供光电探测器的附加阳极和阴极的电性隔离。在代表性实施例中,掺杂区域26、26a、32、32a具有均匀的间距,且掺杂区域28、28a、34、34a也具有均匀的间距。在一替换实施例中,掺杂区域26、26a、32、32a具有不均匀的间距,并且掺杂区域28、28a、34、34a也具有非均匀的间距,使得阳极和阴极可以具有不同尺寸的形状。浅沟槽隔离区域17、17a、17b终止于层24的侧边25,且浅沟槽隔离区域18、18a、18b终止于层24的侧边27。
参考图13,其中类似标号表示图11中的类似特征,并且根据替代实施例,可以修改光电探测器以添加横向定位在由掺杂区域26、28定义的阴极和层24之间的区域44。区域44可以由轻掺杂的设备层12的半导体材料组成,该半导体材料具有与掺杂区域26、28相反的导电类型(例如,p型导电性)。区域44可用于进一步增加光电探测器的增益。在一替换实施例中,图12的光电探测器可以具有类似于区域44的区域,并且这些区域中的每个区域都位于一个阴极和层24之间。
上述方法用于制造集成电路芯片。由此产生的集成电路芯片可由制造商以原始晶圆形式(例如,作为具有多个未封装芯片的单个晶圆)、裸芯片形式或封装形式分布。该芯片可以与其他芯片、分立电路元件和/或其他信号处理设备集成,作为中间产品或最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品,例如具有中央处理器的计算机产品或智能手机。
本文中提及的经近似语言修改的术语,如“大约”、“近似”和“基本上”,不限于规定的精确值。近似语言可与用于测量数值的仪器的精度相对应,除非仪器的精度另有规定,否则可表示规定值的+/-10%。
本文中提及的“垂直”、“水平”等术语是通过举例而非限制的方式来建立参照系的。本文所使用的术语“水平”被定义为与半导体基板的常规平面平行的平面,而不管其实际三维空间方向如何。术语“垂直”和“正交”是指垂直于水平的方向,正如之前定义的那样。术语“横向”是指水平面内的一个方向。
与另一特征“连接”或“耦合”的特征可以直接连接或耦合到另一特征,或者可以存在一个或多个中间特征。如果不存在中间特征,则特征可以与另一特征“直接连接”或“直接耦合”。如果存在至少一个中间特征,则特征可以与另一特征“间接连接”或“间接耦合”。位于另一特征“上”或“接触”另一特征的特征可以直接位于另一特征上或直接接触另一特征,或者,可以存在一个或多个中间特征。一个特征可以是“直接位于另一个特征上”或“直接接触”另一个特征,如果没有中间的特征。如果存在至少一个中间特征,则特征可以是“间接位于另一个特征上”或“间接接触”另一特征。
本发明的各种实施例的描述是为了说明的目的而提出的,但并不打算是穷尽的,也不限于所公开的实施例。在不脱离所描述实施例的范围和精神的情况下,对于本领域的普通技术人员来说,许多修改和变化是显而易见的。本文使用的术语是为了最好地解释实施例的原理、对市场上发现的技术的实际应用或技术改进,或使本领域技术人员能够理解本文公开的实施例。

Claims (20)

1.一种用于光电探测器的结构,其特征在于,该结构包括:
光吸收区域,其包括第一侧边;
第一阳极,其相邻于该光吸收区域的该第一侧边;以及
第一阴极,其相邻于该光吸收区域的该第一侧边。
2.根据权利要求1所述的结构,其特征在于,该结构还包括:
半导体层,
其中,该第一阳极为该半导体层中的第一掺杂区域,该第一阴极为该半导体层中的第二掺杂区域,该第一掺杂区域具有第一导电类型,且该第二掺杂区域具有与该第一导电类型相反的第二导电类型。
3.根据权利要求2所述的结构,其特征在于,该结构还包括:
浅沟槽隔离区域,其横向位于该第一掺杂区域和该二掺杂区域之间的该半导体层中。
4.根据权利要求3所述的结构,其特征在于,该浅沟槽隔离区域终止于该第一侧边。
5.根据权利要求3所述的结构,其特征在于,该结构还包括:
介电层,其位于该半导体层下方,
其中,该浅沟槽隔离区域穿过该半导体层直至该介电层。
6.根据权利要求2所述的结构,其特征在于,该半导体层包括沟槽,该光吸收区域是位于该沟槽中的层,该层由锗组成。
7.根据权利要求2所述的结构,其特征在于,该半导体层包括沟槽,该光吸收区域是位于该沟槽中的层,该层由元素锗构成。
8.根据权利要求2所述的结构,其特征在于,该结构还包括:
第三掺杂区域,其位于该半导体层中,该第三掺杂区域横向位于该第二掺杂区域和该光吸收区域之间,且该第三掺杂区域具有该第一导电类型。
9.根据权利要求1所述的结构,其特征在于,该光吸收区域包括与该第一侧边相对的第二侧边,且还包括:
第二阳极,其相邻于该光吸收区域的该第二侧边;以及
第二阴极,其相邻于该光吸收区域的该第二侧边。
10.根据权利要求9所述的结构,其特征在于,该结构还包括:
半导体层,
其中,该第一阳极为该半导体层中的第一掺杂区域,该第二阳极为该半导体层中的第二掺杂区域,该第一阴极为该半导体层中的第三掺杂区域,该第二阴极为该半导体层中的第四掺杂区域,该第一掺杂区域和该第二掺杂区域具有第一导电类型,且该第三掺杂区域和该第四掺杂区域具有与该第一导电类型相反的第二导电类型。
11.根据权利要求10所述的结构,其特征在于,该结构还包括:
第一浅沟槽隔离区域,其横向位于该第一掺杂区域和该第三掺杂区域之间的该半导体层中;以及
第二浅沟槽隔离区域,其横向位于该第二掺杂区域和该第四掺杂区域之间的该半导体层中;
其中,该第一浅沟槽隔离区域止于该第一侧边,且该第二浅沟槽隔离区域止于该第二侧边。
12.根据权利要求11所述的结构,其特征在于,该结构还包括:
介电层,其位于该半导体层的下方,
其中,该第一浅沟槽隔离区域和该第二浅沟槽隔离区域各自穿过该半导体层直至该介电层。
13.根据权利要求10所述的结构,其特征在于,该半导体层包括沟槽,该光吸收区域是位于该沟槽中的层,该层由锗构成。
14.根据权利要求10所述的结构,其特征在于,该半导体层包括沟槽,该光吸收区域是位于该沟槽中的层,该层由元素锗构成。
15.根据权利要求1所述的结构,其特征在于,该结构还包括:
第二阳极,其相邻于该第一侧边;以及
第二阴极,其相邻于该第一侧边。
16.根据权利要求15所述的结构,其特征在于,该结构还包括:
第一浅沟槽隔离区域,其位于该第一阴极和该第一阳极之间;
第二浅沟槽隔离区域,其位于该第一阳极和该第二阴极之间;以及
第三浅沟槽隔离区域,其位于该第二阴极和该第二阳极之间,
其中,该第一浅沟槽隔离区域、该第二浅沟槽隔离区域、及该第三浅沟槽隔离区域止于该第一侧边。
17.一种形成用于光电探测器的结构的方法,其特征在于,该结构包括:
形成光吸收区域;
形成相邻于该光吸收区域的第一侧边的第一阳极;以及
形成相邻于该光吸收区域的该第一侧边的第一阴极。
18.根据权利要求17所述的方法,其特征在于,该光吸收区域包括与该第一侧边相对的第二侧边,且该方法还包括:
形成相邻于该光吸收区域的该第二侧边的第二阳极;以及
形成相邻于该光吸收区域的该第二侧边的第二阴极。
19.根据权利要求17所述的方法,其特征在于,该第一阳极由第一离子植入工艺形成以作为半导体层中的第一掺杂区域,该第一阴极由第二离子植入工艺形成以作为该半导体层中的第二掺杂区域,该第一掺杂区域具有第一导电类型,且该第二掺杂区域具有相反于该第一导电类型的第二导电类型。
20.根据权利要求19所述的方法,其特征在于,该方法还包括:
形成浅沟槽隔离区域,其位于该第一掺杂区域和该第二掺杂区域之间的该半导体层中。
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