CN113451158A - Flip chip package structure and manufacturing process thereof - Google Patents
Flip chip package structure and manufacturing process thereof Download PDFInfo
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- CN113451158A CN113451158A CN202110450236.5A CN202110450236A CN113451158A CN 113451158 A CN113451158 A CN 113451158A CN 202110450236 A CN202110450236 A CN 202110450236A CN 113451158 A CN113451158 A CN 113451158A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
Abstract
The invention discloses a flip chip package structure and a manufacturing process thereof, wherein the manufacturing process comprises the steps of respectively adhering a first tin paste body and a second tin paste body (or soldering flux) to a positive electrode and a negative electrode of a wafer; cutting the wafer to obtain a plurality of independent flip chips, wherein the positive electrode and the negative electrode of each flip chip are respectively adhered with a first tin paste body and a second tin paste body; arranging one side of the flip chip, which is adhered with the first tin paste body and the second tin paste body, on the substrate; carrying out temperature-controlled heating treatment on the first tin paste body and the second tin paste body, and melting the first tin paste body and the second tin paste body so as to fix the flip chip on the substrate; and packaging the flip chip. Therefore, the solder paste consumption on the flip chip can be effectively controlled, the problem of conduction failure of the flip chip packaging structure caused by the problems of uneven or improper solder amount and the like in the manufacturing process is avoided, and the production process yield and the reliability of the flip chip packaging structure are improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing process, in particular to a flip chip packaging structure and a manufacturing process thereof.
Background
In an electronic component of a Flip Chip (Flip Chip), a Chip is disposed on a substrate by a process of adhering a solder paste onto a dispensing needle, placing the solder paste on the substrate, melting and curing the solder paste by controlling temperature, adhering the Chip to the substrate, and performing a subsequent packaging process.
According to the process for placing the chips on the substrate by dipping the solder paste on the glue needle, the quantity of the solder paste dipped on the glue needle is difficult to control in the large-batch production process. If the tin amount is too much, the tin paste can connect the positive and negative electrode welding pads (pads) of the chip together, so that the whole circuit is in poor conduction; if the amount of tin is too small, the contact between the positive electrode welding pad and the negative electrode welding pad of the chip and the substrate is incomplete, the heat dissipation area of the chip is reduced, and the reliability of the product is reduced.
Therefore, the present invention is directed to a flip chip package and a fabrication process thereof to solve the above problems.
Disclosure of Invention
The present invention provides a flip chip package and a process for fabricating the same, which can effectively control the amount of solder paste on the flip chip, avoid the problem of conduction failure of the flip chip package due to the uneven or improper amount of solder in the process, and improve the yield and reliability of the production process of the flip chip package.
To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a process for fabricating a flip chip package structure, including the following steps:
step one, respectively adhering a first tin paste body and a second tin paste body to the anode and the cathode of a wafer, wherein the first tin paste body and the second tin paste body are positioned on the same side of the wafer; step two, cutting the wafer to obtain a plurality of independent flip chip, wherein the anode and the cathode of each flip chip are respectively adhered with a first tin paste body and a second tin paste body; thirdly, arranging one side of the flip chip, which is adhered with the first tin paste body and the second tin paste body, on the substrate; step four, carrying out temperature-controlled heating treatment on the first tin paste body and the second tin paste body, and melting the first tin paste body and the second tin paste body so as to fix the flip chip on the substrate; and step five, packaging the flip chip.
In some embodiments, the substrate is one selected from a metal substrate, a ceramic substrate, a printed circuit board.
In some embodiments, before the third step, the method further comprises: a reflective cup-shaped support structure is formed on the surface of the substrate using a thermoset material.
Further, the thermosetting material is at least one selected from the group consisting of Epoxy Molding Compound (Epoxy Molding Compound), Silicone Molding Compound (Silicone Molding Compound), and unsaturated polyester.
In some embodiments, before the third step, the method further comprises: a reflective cup-shaped support structure is formed on a surface of a substrate using a thermoplastic material.
Further, the thermoplastic material is at least one selected from the group consisting of PCT resin, PPA plastic, and Liquid Crystal Polymer (Liquid Crystal Polymer).
In some embodiments, the step five further comprises: and packaging the flip chip by using a packaging layer.
Further, the packaging layer contains fluorescent powder.
Further, the encapsulation layer may be made of epoxy resin or silicone material.
To achieve at least one of the above advantages or other advantages, another embodiment of the present invention further provides a flip chip package structure manufactured by the manufacturing process of the flip chip package structure described in any one of the above aspects.
Therefore, the flip chip package structure and the manufacturing process thereof provided by the invention can adhere the solder paste to the anode and the cathode of the flip chip in the Wafer (Wafer) period, thereby accelerating the production efficiency, effectively controlling the solder paste consumption on the flip chip, avoiding the conduction failure of the flip chip package structure caused by uneven or improper solder amount in the manufacturing process, and improving the yield and the reliability of the manufacturing process of the flip chip package structure.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described below in detail with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It should be apparent that the drawings in the following description are only examples of the present application and are not intended to limit the embodiments of the present invention, and that other drawings may be derived from the drawings by those skilled in the art without inventive faculty. The drawings comprise:
FIG. 1 is a schematic flow chart of a process for fabricating a flip chip package structure according to the present invention;
FIG. 2 is a schematic diagram of a process for fabricating a flip chip package structure according to the present invention; and
fig. 3 is a schematic cross-sectional view of the flip chip package structure of the present invention.
The attached drawings are marked as follows: 10. 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53-flip chip package structure; 12-a substrate; 14-a support structure; 16-flip chip; 18-a first tin paste; 20-a second tin paste; 22-an encapsulation layer; 24-silica gel.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations and positional relationships based on those shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or component in question must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be taken as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. In addition, the term "comprises" and any variations thereof mean "including at least".
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integrally formed connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic flow chart of a manufacturing process of the flip chip package structure 10 of the present invention, and fig. 2 is a schematic process of the flip chip package structure 10 of the present invention. To achieve at least one of the above advantages or other advantages, an embodiment of the invention provides a process for fabricating a flip chip package structure 10. As shown in the figure, the process for fabricating the flip chip package structure 10 includes the following steps:
s100: respectively adhering the first tin paste body and the second tin paste body to the anode and the cathode of the wafer;
s200: cutting the wafer;
s300: arranging one side of the flip chip, which is adhered with the first tin paste body and the second tin paste body, on the substrate;
s400: carrying out temperature-controlled heating treatment on the first tin paste body and the second tin paste body, and melting the first tin paste body and the second tin paste body so as to fix the flip chip on the substrate;
s500: and packaging the flip chip.
To further illustrate, before step S100, the integrated circuits are scribed on the wafer, and the surface metallization is completed. That is, the wafer has been divided into positive and negative electrodes. In step S100, the first solder paste 18 and the second solder paste 20 are adhered to the same side of the wafer, and since the solder paste is adhered at the wafer stage, the wafer surface is flat and the positive pad (pad) and the negative pad (pad) are equally spaced, so that the control of the solder paste amount is easier and the subsequent process is facilitated. In step S200, after the Wafer is diced, a plurality of independent flip chip chips 16 can be obtained, and since the first solder paste 18 and the second solder paste 20 are already adhered to the positive electrode and the negative electrode thereof at the Wafer (Wafer) stage, the first solder paste 18 and the second solder paste 20 are adhered to the positive electrode pad and the negative electrode pad of each flip chip 16 obtained after dicing respectively.
The first and second tin paste bodies 18, 20 may be solder pastes containing flux and solder powder. The main components of the soldering flux comprise an activator (Activation), a Thixotropic agent (Thixotropic), a resin (Resins), and a Solvent (Solvent). The activator mainly plays a role in removing oxide substances on the surface layer of the PCB copper film bonding pad and the welding part of the part, and has the effect of reducing the surface tension of tin and lead. The thixotropic agent is mainly used for adjusting the viscosity and the printing performance of the soldering paste and plays a role in preventing trailing, adhesion and other phenomena in printing. The resin mainly plays a role in increasing the adhesiveness of the solder paste, protecting and preventing the PCB from being oxidized again after welding, and plays an important role in fixing parts. The solvent is a solvent of the welding flux components, plays a role in uniformly adjusting in the stirring process of the solder paste, and has certain influence on the service life of the solder paste. The solder powder is tin powder, which mainly consists of tin-lead alloy.
In general, the invention adheres the solder paste on the anode and the cathode of the wafer in the wafer period, which can accelerate the production efficiency, i.e. it is beneficial to simplify the process and fast operation, and it is not necessary to separately adhere the solder paste on each flip chip. Moreover, the amount of solder paste on the flip chip 16 can be effectively controlled, thereby avoiding the occurrence of conduction failure of the flip chip package structure 10 due to uneven or improper solder amount in the manufacturing process, and improving the yield and reliability of the manufacturing process of the flip chip package structure 10.
In an embodiment, the step S500 further includes encapsulating the flip chip 16 by using the encapsulation layer 22 to isolate the flip chip 16 from the outside, and filling a protective silica gel between the flip chip 16 and the encapsulation layer 22 to prevent the electrical performance of the flip chip 16 from being degraded due to the corrosion of the circuit by the impurities in the air, and to protect the flip chip 16 from the external damage and the external environment. The encapsulation layer 22 may be made of epoxy resin or silicone material. In addition, the phosphor can be mixed with the encapsulant to form the encapsulation layer 22, thereby improving the light emitting effect of the flip chip 16. However, the present invention is not limited thereto. As shown in fig. 4, the flip chip 16 may be packaged by using only protective silica gel, so as to achieve the packaging protection effect.
In an embodiment, before the step S300, that is, before the flip chip 16 is disposed on the substrate 12, the reflective cup-shaped supporting structure 14 may be formed on the surface of the substrate 12 by using a thermosetting material, and the encapsulating layer 22 may cooperate with the protective layer to protect the flip chip 16 inside, so as to collect the light-emitting range of the flip chip 16 and improve the brightness effect. The thermosetting material is at least one selected from the group consisting of Epoxy Molding Compound (Epoxy Molding Compound), Silicone Molding Compound (Silicone Molding Compound), and unsaturated polyester.
However, the present invention is not limited thereto. In other embodiments, the reflective cup-shaped support structure 14 may be formed on the surface of the substrate 12 using a thermoplastic material. The thermoplastic material is at least one selected from the group consisting of PCT resin, PPA plastic and Liquid Crystal Polymer (Liquid Crystal Polymer).
In one embodiment, the substrate 12 may be a metal substrate 12, a ceramic substrate 12, or a Printed Circuit Board (PCB) to meet different requirements.
The following describes various aspects of the flip chip package structure finally manufactured according to the process of manufacturing the flip chip package structure of the present invention with reference to the drawings of fig. 3 to fig. 15.
Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a flip chip package structure 10 according to a first embodiment of the invention. To achieve at least one of the advantages or other advantages, a flip chip package structure 10 is further provided in another embodiment of the present invention. The flip chip package structure 10 is manufactured according to the manufacturing process of the flip chip package structure 10 in the foregoing embodiment. As shown in fig. 3, the flip chip package 10 includes a substrate 12, a supporting structure 14, a flip chip 16, a first solder paste 18, a second solder paste 20, an encapsulation layer 22, and a silicone gel 24.
The support structure 14 is in the shape of a reflective cup. The flip chip 16 is located inside the supporting structure 14, and the positive electrode and the negative electrode of the flip chip are respectively adhered with a first solder paste 18 and a second solder paste 20, and are fixed on the substrate 12 through the first solder paste 18 and the second solder paste 20. The packaging layer 22 covers the supporting structure 14 to encapsulate the flip chip 16. The silica gel 24 is filled between the package layer 22, the flip chip 16 and the supporting structure 14 for protection.
Referring to fig. 4, fig. 4 is a schematic cross-sectional view of a flip chip package 42 according to a second embodiment of the invention. To achieve at least one of the above advantages or other advantages, a flip chip package structure 42 is further provided in another embodiment of the present invention. Compared with the flip chip package 10 shown in fig. 3, the flip chip package structure 42 only uses the silica gel 24 to package the flip chip 16 without using the package layer 22, thereby achieving the protection effect, reducing the overall thickness and saving the material.
Referring to fig. 5, fig. 5 is a schematic cross-sectional view of a flip chip package structure 43 according to a third embodiment of the invention. To achieve at least one of the above advantages or other advantages, a flip chip package structure 43 is further provided in another embodiment of the present invention. Compared to the flip chip package 10 shown in fig. 3, the flip chip package 43 has a space for the package layer 22 to be disposed on the supporting structure 14 for the subsequent process.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of a flip chip package 44 according to a fourth embodiment of the invention. To achieve at least one of the above advantages or other advantages, a flip chip package junction 44 is further provided in another embodiment of the present invention. Compared to the flip chip package 10 shown in fig. 3, the flip chip package 44 has an arc-shaped top end of the package layer 22 to meet the requirement of the application.
Referring to fig. 7, fig. 7 is a schematic cross-sectional view of a fifth embodiment of a flip chip package structure 45 according to the present invention. To achieve at least one of the above advantages or other advantages, a flip chip package structure 45 is further provided in another embodiment of the present invention. Compared with the flip chip package 42 shown in fig. 4, the flip chip package 45 has an arc shape of the final shape of the filled silicone gel 24, so as to meet the requirement of use.
Further, each of the flip chip packages 10, 42, 43, 44, 45 of fig. 3-7 uses a lead-out design. However, the present invention is not limited thereto. As shown in fig. 8 to 12, in comparison with the flip chip packages 10, 42, 43, 44 and 45 of fig. 3 to 7, the flip chip packages 46, 47, 48, 49 and 50 of fig. 8 to 12 have the advantages that the leads are not protruded, so that the flip chip packages are convenient to mount and use, and the occupied space is reduced.
In an embodiment, as shown in fig. 13, compared to the flip chip package 10 of fig. 3, the flip chip package 51 does not need to form the supporting structure 14 to further enhance the overall structural strength, and the silicone gel 24 is coated on the surfaces of the substrate 12 and the flip chip 16, so as to achieve the supporting and protecting effects, reduce the overall volume, and save the material.
In an embodiment, the flip chip package structure 52 shown in fig. 14 can achieve the protection effect without using the package layer 22, and reduce the overall thickness and save material compared to the flip chip package structure 51 shown in fig. 13.
In one embodiment, the flip chip package 53 shown in fig. 15 has an arc-shaped top portion formed by the silicone rubber 24 to satisfy the requirement of the application, compared to the flip chip package 52 shown in fig. 14.
In summary, the flip chip package structure 10 and the manufacturing process thereof provided by the present invention can adhere solder paste to the positive electrode and the negative electrode thereof during the wafer period, thereby increasing the production efficiency, effectively controlling the solder paste amount on the flip chip 16, avoiding the occurrence of conduction failure of the flip chip package structure 10 due to uneven or improper solder amount in the manufacturing process, and improving the yield and reliability of the manufacturing process of the flip chip package structure 10.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A manufacturing process of a flip chip package structure is characterized by comprising the following steps:
respectively adhering a first tin paste body and a second tin paste body to the anode and the cathode of a wafer, wherein the first tin paste body and the second tin paste body are positioned on the same side of the wafer;
cutting the wafer to obtain a plurality of independent flip chips, wherein the first tin paste body and the second tin paste body are respectively adhered to the anode and the cathode of each flip chip;
arranging one side of the flip chip, which is adhered with the first tin paste body and the second tin paste body, on a substrate;
carrying out temperature-controlled heating treatment on the first tin paste body and the second tin paste body, and melting the first tin paste body and the second tin paste body so as to fix the flip chip on the substrate; and
and packaging the flip chip.
2. The process for fabricating a flip chip package according to claim 1, wherein the substrate is one selected from a metal substrate, a ceramic substrate, and a printed circuit board.
3. The process for manufacturing a flip chip package according to claim 1, wherein before the step of disposing the side of the flip chip bonded with the first and second solder paste on the substrate, the process further comprises: a reflective cup-shaped support structure is formed on the surface of the substrate using a thermoset material.
4. The process of claim 3, wherein the thermosetting material is at least one selected from the group consisting of Epoxy Molding Compound (Epoxy Molding Compound), Silicone Molding Compound (Silicone Molding Compound), and unsaturated polyester.
5. The process for manufacturing a flip chip package according to claim 1, wherein before the step of disposing the side of the flip chip bonded with the first and second solder paste on the substrate, the process further comprises: a reflective cup-shaped support structure is formed on a surface of a substrate using a thermoplastic material.
6. The process of claim 5, wherein the thermoplastic material is at least one selected from the group consisting of PCT resin, PPA plastic, and Liquid crystal polymer (Liquid crystalline polymer).
7. The process for fabricating a flip chip package according to claim 1, wherein the step of performing the packaging process on the flip chip further comprises: and packaging the flip chip by using a packaging layer.
8. The process for fabricating a flip chip package according to claim 7, wherein the package layer comprises phosphor.
9. The process for fabricating a flip chip package according to claim 7, wherein the encapsulation layer is made of epoxy or silicone material.
10. A flip chip package structure, wherein the flip chip package structure is manufactured by the process of manufacturing the flip chip package structure according to any one of claims 1 to 9.
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| CN202110450236.5A CN113451158A (en) | 2021-04-25 | 2021-04-25 | Flip chip package structure and manufacturing process thereof |
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2021
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| CN1941303A (en) * | 2005-09-28 | 2007-04-04 | 相丰科技股份有限公司 | Chip packing and IC module assembling mode |
| CN103500724A (en) * | 2013-09-02 | 2014-01-08 | 扬州虹扬科技发展有限公司 | Prewelding method for Schottky grains |
| CN106328548A (en) * | 2015-06-15 | 2017-01-11 | 苏州普福斯信息科技有限公司 | Application method of solder paste printing on wafer in diode packaging |
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