CN113436986A - Chip mounting device and method for manufacturing semiconductor device - Google Patents

Chip mounting device and method for manufacturing semiconductor device Download PDF

Info

Publication number
CN113436986A
CN113436986A CN202110197928.3A CN202110197928A CN113436986A CN 113436986 A CN113436986 A CN 113436986A CN 202110197928 A CN202110197928 A CN 202110197928A CN 113436986 A CN113436986 A CN 113436986A
Authority
CN
China
Prior art keywords
chip
substrate
illumination
imaging device
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110197928.3A
Other languages
Chinese (zh)
Other versions
CN113436986B (en
Inventor
小桥英晴
保坂浩二
吉山仁晃
小野悠太
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fasford Technology Co Ltd
Original Assignee
Fasford Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fasford Technology Co Ltd filed Critical Fasford Technology Co Ltd
Publication of CN113436986A publication Critical patent/CN113436986A/en
Application granted granted Critical
Publication of CN113436986B publication Critical patent/CN113436986B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Abstract

The invention provides a technology capable of improving crack identification precision. The chip mounting device is provided with: a shooting device for shooting the chip; an illuminating device for illuminating the chip obliquely with respect to an optical system axis of the imaging device; and a control device for controlling the imaging device and the illumination device. The control device is configured to irradiate the chip with light having a wavelength shorter than green in a visible light region by the illumination device and to image the chip by the imaging device in order to detect a crack formed in the chip.

Description

Chip mounting device and method for manufacturing semiconductor device
Technical Field
The present invention relates to a chip mounter and is applicable to, for example, a chip mounter which detects cracks in a chip.
Background
The semiconductor device manufacturing process includes a step of mounting a semiconductor chip (hereinafter, simply referred to as a chip) on a wiring board, a lead frame, or the like (hereinafter, simply referred to as a board) and assembling and packaging the semiconductor chip, and the semiconductor device manufacturing process includes a step of separating the chip from a semiconductor wafer (hereinafter, simply referred to as a wafer) (dicing step) and a mounting step of mounting the separated chip on the board. The semiconductor manufacturing apparatus used in the mounting process is a die mounter such as a die mounter.
In the dicing step, a crack extending from the dicing surface into the chip may occur due to cutting resistance during dicing. Therefore, in the mounting process, the chip is photographed by a camera to perform surface inspection (appearance inspection).
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 2019-54203
Disclosure of Invention
Since a protective film (surface protective film) on the surface of a chip formed of a polyimide film or the like is a layer that can transmit irradiation light from an illumination device, it is sometimes difficult to detect a crack formed from the upper surface or the lower surface of the surface protective film toward a substrate such as silicon, depending on the thickness of the surface protective film, the uneven pattern formed below the surface protective film, or the like.
The invention provides a technology capable of improving crack identification precision.
A brief description of a summary of representative contents of the present invention is as follows:
that is, the die bonding apparatus includes: a shooting device for shooting the chip; an illuminating device for illuminating the chip obliquely with respect to an optical system axis of the imaging device; and a control device for controlling the imaging device and the illumination device. The control device is configured to: in order to detect cracks formed in the chip, the chip is irradiated with light having a wavelength shorter than green in the visible light region by an illumination device, and the chip is photographed by a photographing device.
Effects of the invention
According to the chip mounting device, the crack identification precision can be improved.
Drawings
Fig. 1 is a schematic plan view showing an example of the configuration of the chip mounter.
Fig. 2 is a diagram illustrating a schematic configuration when viewed from the direction of arrow a in fig. 1.
Fig. 3 is a schematic cross-sectional view showing a main part of the chip supply unit of fig. 1.
Fig. 4 is a block diagram showing a schematic configuration of a control system of the chip mounter of fig. 1.
Fig. 5 is a flowchart illustrating a chip mounting process in the chip mounter of fig. 1.
Fig. 6 is a schematic diagram illustrating oblique illumination.
Fig. 7 is a diagram illustrating a crack and its background.
Fig. 8 is a diagram illustrating differences in visual appearance of patterns generated based on illumination colors.
Fig. 9 is a graph showing the measurement results of the coordinates in the field of view and the cracks and background illuminance on the chip surface.
Description of the reference numerals
BD … chip mounting device
CM … shooting device
CNT … control device
D … chip
LD … lighting device
Detailed Description
First, the technique studied by the present inventors will be described with reference to fig. 6 to 9. Fig. 6 is a schematic diagram illustrating oblique illumination. Fig. 7 is a diagram illustrating a crack and its background, where fig. 7 (a) is a diagram showing an image in a case where a difference in brightness contrast between the crack and the background is large, and fig. 7 (b) is a diagram showing an image in a case where a difference in brightness contrast between the crack and the background is small. Fig. 8 is a diagram illustrating differences in visual expression of patterns generated based on illumination colors, where fig. 8 (a) is an image in the case where the illumination color is blue, fig. 8 (b) is an image in the case where the illumination color is green, and fig. 8 (c) is an image in the case where the illumination color is red. Fig. 9 is a graph showing the measurement results of the coordinates in the field of view and the cracks and background illuminance on the chip surface, where fig. 9 (a) shows the case of white illumination, fig. 9 (b) shows the case of blue illumination, and fig. 9 (c) shows the case of red illumination.
When designing a crack inspection function using an image obtained by a camera, the illumination configuration includes a bright field method of "imaging the background brightly and imaging the content desired to be observed darkly" and a dark field method of "imaging the background darkly and imaging the content desired to be observed brightly". In general, when inspecting a fine flaw, it is preferable to use a dark field method. When the wafer surface is inspected by the dark field method while being close to the mirror surface, it is preferable to use oblique illumination, which is an illumination method of irradiating light from an oblique direction. As shown in fig. 6, when detecting a crack in the chip D, it is easier to illuminate the crack when the incident angle (θ) of the oblique illumination of the illumination device LD is as close as possible to the axis of the optical system of the imaging device CM (when the incident angle (θ) is as close as possible to 0). In this specification, this illumination is referred to as high-angle crack detection illumination.
The spectral reflectance of the memory cell layer changes due to the thinning of a surface protective film made of a polyimide film or the like, the lamination of surface memories, and the like. Therefore, under high-angle crack detection illumination, as shown in fig. 7 (b), a pattern such as a stripe pattern may appear on the memory cells of the memory array MARY on the chip surface. When the streak pattern appears in the background, it becomes difficult to distinguish the streak pattern from the crack CRK. That is, the streak pattern hinders separation of the crack region from other regions by image processing, and it is difficult to detect a crack with a small difference in brightness contrast with respect to the background and accurately measure the crack length. In the case where the area of a region constituted by a repetitive pattern is larger than the area of other regions like the memory array MARY, the influence is large.
As shown in fig. 8, the longer the wavelength of the oblique illumination used in the stripe pattern, the more conspicuous it becomes; the shorter the length, the more disappearing and gradually invisible.
When the cracks and the background illuminance on the chip surface are measured, as shown in fig. 9 (a), there are portions (a) where the local brightness becomes bright under white illumination, which are cracks, and in fig. 9 (a), (B) is the brightness of the background, (C) is a region where the memory cell is exposed and becomes bright, and (D) is a region where the memory cell is totally reflected. As for the region where the storage unit is exposed and brightened under the white illumination shown in (C) of fig. 9 (a), the region becomes absent under the blue illumination of (b) of fig. 9, while the region where the storage unit is exposed and brightened under the red illumination shown in (C) of fig. 9 exists. Therefore, it is found that the portion where the background brightness becomes brighter under white illumination is caused by the red component in white.
The above differences based on the illumination color are due to:
(a) a difference in absorption spectrum of the surface protective film (blue light is more easily absorbed);
(b) interference of light of the surface protective film (red light is more likely to interfere);
(c) difference in reflection spectrum of a short (shoot) portion (chip surface) in the memory layer of the silicon surface layer (red light is more easily reflected).
That is, the longer the wavelength is in the visible light region, the higher the reflectance of the chip surface is, and the polyimide film intervenes therein, so that transmission and interference occur, and the memory cell pattern on the chip surface is visible. On the other hand, this is because the shorter the wavelength, the less its characteristic is, and only the diffused light of the crack is reflected.
Therefore, as shown in fig. 6, the die bonding apparatus BD according to the embodiment includes the imaging device CM and the illumination device LD. The lighting device LD uses illumination with light having a wavelength shorter than green in the visible light region so that no stripe pattern appears on the surface. For example, a blue LED or a violet LED is used as the light source. The light source to be used may be a white light source that transmits a short pass filter (short pass filter) in addition to a light source emitting blue light (e.g., a blue LED). Here, the short-wavelength pass filter is a wavelength (color) separation filter that can transmit light on the short-wavelength side and cut light on the long-wavelength side by sharp startability. The short-wavelength pass filter as the optical filter is preferably a cyan filter (cyan filter) that cuts red and transmits blue, for example.
In addition, the illumination device LD is preferably obliquely illuminated. Further, the oblique illumination is more preferably a high angle. The illumination device LD may be oblique ring illumination or oblique strip illumination. The incident angle (θ) is, for example, preferably more than 0 degrees and 30 degrees or less, and more preferably 5 degrees to 15 degrees.
This can increase the contrast between the crack and the background. For a crack imaged by a camera as a contrast difference, separation of the crack imaged shallowly (low contrast) from its background becomes easy, so that detection of a crack having a narrower width is possible. In addition, the same inspection sensitivity as that of a product having no stripe pattern in the background can be obtained. This improves the inspection sensitivity and stabilizes the inspection.
When positioning or position inspection (hereinafter, collectively referred to as position recognition) of the chip and the substrate is performed, illumination by a white light source is used. Further, the illumination may be performed by using a white light source (white LED or the like), and the illumination may be performed by irradiating blue light or violet light through the short-wavelength pass filter when detecting a chip crack, and by irradiating white light without transmitting through the short-wavelength pass filter when recognizing a position. In addition, a light source different from that for chip crack detection may be provided for positioning or position inspection of the chip and the substrate.
Hereinafter, embodiments will be described with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and redundant description thereof may be omitted. In addition, in order to make the description more clear, the drawings may schematically show the width, thickness, shape, and the like of each part as compared with the actual form, but the drawings are only an example and do not limit the explanation of the present invention.
Examples
Fig. 1 is a plan view schematically showing a chip mounter according to an embodiment. Fig. 2 is a diagram illustrating the operation of the pick-up head and the mounting head when viewed from the direction of arrow a in fig. 1.
The chip mounter 10 generally has: a chip supply section 1 that supplies a chip D to be mounted on a substrate S; a pickup section 2; an intermediate stage section 3; a mounting portion 4; a conveying part 5; a substrate supply unit 6; a substrate carrying-out section 7; and a control unit 8 for monitoring and controlling the operation of each unit. The Y-axis direction is the front-rear direction of the chip mounter 10, and the X-axis direction is the left-right direction. The chip supply unit 1 is disposed on the front side of the chip mounter 10, and the mounting unit 4 is disposed on the rear side. Here, one or more product areas (hereinafter, referred to as package areas P) that eventually become one package are printed on the substrate S.
First, the chip supply section 1 supplies a chip D to be mounted on the package region P of the substrate S. The chip supply unit 1 includes a wafer holding table 12 for holding the wafer 11 and a lift unit 13 indicated by a broken line for lifting the chip D from the wafer 11. The chip supply portion 1 is moved in the XY direction by a drive mechanism not shown, and moves the chip D to be picked up to the position of the ceiling unit 13.
The pickup section 2 includes: a pickup head 21 for picking up the chip D; a Y drive section 23 of the pickup head that moves the pickup head 21 in the Y direction; and driving units, not shown, for moving the collet 22 up and down, rotating it, and moving it in the X direction. The pickup head 21 has a collet 22 (see also fig. 2) that sucks and holds the lifted chip D to the tip, picks up the chip D from the chip supply unit 1, and mounts the chip D on the intermediate stage 31. The pickup head 21 includes driving units, not shown, for moving the collet 22 up and down, rotating, and moving in the X direction.
The intermediate stage unit 3 has an intermediate stage 31 on which the chip D is temporarily placed, and a stage recognition camera 32 for recognizing the chip D on the intermediate stage 31.
The mounting unit 4 picks up the chip D from the intermediate stage 31 and mounts the chip D on the package region P of the substrate S that has been carried or on the chip that has been mounted on the package region P of the substrate S. The mounting portion 4 has: a mounting head 41 provided with a collet 42 (see also fig. 2) for holding the chip D by suction at the tip, similarly to the pickup head 21; a Y drive unit 43 for moving the mounting head 41 in the Y direction; and a substrate recognition camera 44 that photographs a position recognition mark (not shown) of the package region P of the substrate S and recognizes a mounting position. According to this configuration, the mounting head 41 corrects the pickup position and the posture based on the imaging data of the stage recognition camera 32, picks up the chip D from the intermediate stage 31, and mounts the chip D on the substrate based on the imaging data of the substrate recognition camera 44.
The conveying unit 5 includes a substrate conveying claw 51 for holding and conveying the substrate S, and a conveying path (lane)52 for moving the substrate S. The substrate S is moved by driving a nut, not shown, of the substrate transport claw 51 provided in the transport path 52 by a ball screw, not shown, provided along the transport path 52. With this configuration, the substrate S is moved from the substrate supply unit 6 to the mounting position along the conveyance path 52, moved to the substrate carry-out unit 7 after mounting, and delivered to the substrate carry-out unit 7.
The control unit 8 includes: a memory storing a program (software) for monitoring and controlling the operation of each part of the chip mounter 10; and a Central Processing Unit (CPU) that executes a program stored in the memory.
Next, the structure of the chip supply unit 1 will be described with reference to fig. 3. Fig. 3 is a schematic cross-sectional view showing a main part of the chip supply unit of fig. 1.
The chip supply unit 1 includes a wafer holding table 12 that moves in a horizontal direction (XY direction), and a lift unit 13 that moves in a vertical direction. The wafer holding stage 12 includes an extension ring 15 that holds the wafer ring 14, and a support ring 17 that horizontally positions a dicing blue (dicing tape)16 that is held by the wafer ring 14 and to which a plurality of chips D are bonded. The jacking unit 13 is arranged inside the bearing ring 17.
The chip supply unit 1 lowers the extension ring 15 holding the wafer ring 14 when the chip D is lifted up. As a result, the dicing blue film 16 held by the wafer ring 14 is stretched to increase the interval between the chips D, and the chip D is lifted from below the chip D by the lifting means 13, thereby improving the pickup property of the chip D. In addition, as the thickness of the wafer is reduced, the adhesive for bonding the chip to the substrate is changed from a liquid state to a film state, and a film-like adhesive material called a film adhesive (DAF)18 is attached between the wafer 11 and the dicing blue film 16. In the wafer 11 having the adhesive sheet film 18, dicing is performed on the wafer 11 and the adhesive sheet film 18. Therefore, in the peeling step, the wafer 11 and the adhesive sheet film 18 are peeled from the dicing blue film 16. In addition, the presence of the adhesive sheet film 18 will be described later with omission.
The chip mounter 10 has: a wafer recognition camera 24 that recognizes a posture of the chip D on the wafer 11; a stage recognition camera 32 that recognizes a posture of the chip D mounted on the intermediate stage 31; and a substrate recognition camera 44 that recognizes a mounting position on the mounting stage BS. The cameras that must be subjected to the correction of the attitude deviation between the recognition cameras are the stage recognition camera 32 relating to the pickup by the mounting head 41 and the substrate recognition camera 44 relating to the mounting position by the mounting head 41. In the present embodiment, the illumination device described in the embodiment is used together with the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44 to detect cracks of the chip D.
The control unit 8 will be described with reference to fig. 4. Fig. 4 is a block diagram showing a schematic configuration of the control system. The control system 80 includes a control unit 8, a drive unit 86, a signal unit 87, and an optical system 88. The control unit 8 generally includes a control and arithmetic device 81 mainly composed of a cpu (central Processor unit), a storage device 82, an input/output device 83, a bus 84, and a power supply unit 85. The storage device 82 includes a main storage device 82a composed of a RAM in which a processing program and the like are stored, and an auxiliary storage device 82b composed of a HDD in which control data, image data and the like necessary for control are stored. The input/output device 83 includes: a monitor 83a that displays device status, information, and the like; a touch panel 83b for inputting an instruction of an operator; a mouse 83c for operating the monitor; and an image acquisition device 83d for acquiring image data from the optical system 88. The input/output device 83 further includes: a motor control device 83e for controlling a drive unit 86 such as a ZY drive shaft of an XY table (not shown) of the chip supply unit 1 and a head table; and an I/O signal control device 83f that takes in or controls various sensor signals and takes in or controls signals from a signal unit 87 such as a switch of the lighting device or the like. The optical system 88 includes the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44. The control and arithmetic device 81 takes in necessary data via the bus 84 and performs arithmetic operations, and transmits information to the control of the pickup head 21 and the like and the monitor 83a and the like.
The control unit 8 stores the image data captured by the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44 in the storage device 82 via the image capture device 83 d. The control and arithmetic device 81 is used to position the package regions P of the chip D and the substrate S and to inspect the surfaces of the chip D and the substrate S by software programmed based on the stored image data. The driving unit 86 is operated by software through the motor control device 83e based on the positions of the chip D and the package region P of the substrate S calculated by the control and arithmetic device 81. In this process, the chips on the wafer are positioned, and the chips D are mounted on the package region P of the substrate S by the operation of the driving units of the pickup unit 2 and the mounting unit 4. The wafer recognition camera 24, stage recognition camera 32, and substrate recognition camera 44 to be used are a grayscale camera, a color camera, and the like, and the light intensity is digitized.
Fig. 5 is a flowchart illustrating a chip mounting process in the chip mounter of fig. 1.
In the die bonding step of the embodiment, first, the control unit 8 takes out the wafer ring 14 holding the wafer 11 from the wafer cassette and places the wafer ring on the wafer holding stage 12, and conveys the wafer holding stage 12 to a reference position where the chip D is picked up (wafer loading (step P1)). Next, the control unit 8 performs fine adjustment so that the arrangement position of the wafer 11 accurately coincides with the reference position, based on the image acquired by the wafer recognition camera 24.
Next, the controller 8 moves the wafer holding table 12 on which the wafer 11 is placed at a predetermined pitch and holds the wafer holding table horizontally, thereby placing the chip D to be picked up first at the pickup position (chip transfer (step P2)). The wafer 11 is inspected for each chip by an inspection device such as a prober in advance, and map data (map data) indicating pass or fail is generated for each chip and stored in the storage device 82 of the control unit 8. Whether the chip D to be picked up is a non-defective product or a defective product is determined from the map data. When the chip D is a defective product, the control unit 8 moves the wafer holding table 12 on which the wafer 11 is placed at a predetermined pitch, positions the chip D to be picked up next at the picking position, and skips over the chip D of the defective product.
The control unit 8 images the main surface (upper surface) of the chip D as the pickup object by the wafer recognition camera 24, and calculates the positional displacement amount of the chip D as the pickup object with respect to the pickup position from the acquired image. The control unit 8 moves the wafer holding table 12 on which the wafer 11 is placed based on the positional deviation amount, and accurately arranges the chip D as the pickup object at the pickup position (chip positioning (step P3)).
Next, the control unit 8 performs surface inspection of the chip D based on the image acquired by the wafer recognition camera 24 (step P4). Here, the control unit 8 determines whether or not there is a problem by surface inspection, and proceeds to the next step (step P9 described later) if it determines that there is no problem on the surface of the chip D, but if it determines that there is a problem, the control unit visually checks the surface image, performs inspection with higher sensitivity, performs inspection such as changing the lighting conditions, and performs the skip processing if there is a problem, and performs the processing of the next step if there is no problem. The skip process is a process after the step P9 of skipping the chip D, in which the wafer holding table 12 on which the wafer 11 is placed is moved at a predetermined pitch, and the chip D to be picked up next is placed at the pickup position.
The controller 8 places the substrate S on the conveyance path 52 by the substrate supply unit 6 (substrate loading (step P5)). The controller 8 moves the substrate transport claw 51 holding the transport substrate S to the mounting position (substrate transport (step P6)). The substrate is photographed and positioned by the substrate recognition camera 44 (substrate positioning (step P7)).
Next, the control unit 8 performs surface inspection of the sealing region P of the substrate S based on the image acquired by the substrate recognition camera 44 (step P8). Here, the control unit 8 determines whether or not there is a problem by surface inspection, and proceeds to the next step (step P9 described later) if it is determined that there is no problem on the surface of the package region P of the substrate S, but visually checks the surface image or performs inspection such as inspection with higher sensitivity and change of illumination conditions if it is determined that there is a problem, and performs skip processing if there is a problem and processing of the next step if there is no problem. The skip process is a process after the process P10 of skipping the corresponding piece of the package region P of the substrate S, and the defective registration is performed in the substrate working information.
After the chip D as the pickup object is accurately placed at the pickup position by the chip supply unit 1, the control unit 8 picks up the chip D from the dicing blue film 16 by the pickup head 21 including the collet 22 (chip processing (step P9)), and places the chip D on the intermediate stage 31 (step P10). The control unit 8 detects a positional deviation (rotational deviation) of the chip mounted on the intermediate stage 31 by imaging with the stage recognition camera 32 (step P11). When there is a deviation in the posture, the control unit 8 corrects the deviation in the posture by rotating the intermediate stage 31 in a plane parallel to the mounting surface having the mounting position by a rotation driving device (not shown) provided in the intermediate stage 31.
The control unit 8 performs surface inspection of the chip D based on the image acquired by the stage recognition camera 32 (step P12). Here, the control unit 8 determines whether or not there is a problem by surface inspection, and proceeds to the next step (step P13 described later) if it determines that there is no problem with the surface of the chip D, but visually checks the surface image or performs inspection with higher sensitivity or inspection with changed lighting conditions if it determines that there is a problem, places the chip on a defective tray or the like (not shown) if there is a problem, and performs the skip processing, and performs the processing of the next step if there is no problem. The skip process is a process after the step P13 of skipping the chip D, in which the wafer holding table 12 on which the wafer 11 is placed is moved at a predetermined pitch, and the chip D to be picked up next is placed at the pickup position.
The control unit 8 picks up the chip D from the intermediate stage 31 by the mounting head 41 including the collet 42, and mounts the chip D in the package region P of the substrate S or on a chip already mounted in the package region P of the substrate S (chip bonding ((step P13)).
After the chip D is mounted, the control unit 8 checks whether or not the mounting position is accurate (checks the relative position between the chip and the substrate (step P14)). At this time, the center of the chip and the center of the sheet portion are obtained in the same manner as the alignment of the chip described later, and whether the relative positions are accurate or not is checked.
Next, the control unit 8 performs surface inspection of the chip D and the substrate S based on the image acquired by the substrate recognition camera 44 (step P15). Here, the control unit 8 determines whether or not there is a problem by surface inspection, and proceeds to the next step (step P9 described later) if it determines that there is no problem on the surface of the mounted chip D, but visually checks the surface image or performs inspection such as inspection with higher sensitivity or change of illumination conditions if it determines that there is a problem, and performs skip processing if there is a problem and processing in the next step if there is no problem. In the skip process, a failure is registered in the substrate working information.
Thereafter, the chips D are mounted one by one to the package region P of the substrate S in the same step. When mounting of one substrate is completed, the substrate S is moved to the substrate carry-out section 7 by the substrate transport claw 51 (substrate transport (step P16)), and the substrate S is delivered to the substrate carry-out section 7 (substrate unloading (step P17)).
Thereafter, the chips D are individually peeled from the dicing blue film 16 in the same procedure (step P9). When the picking up of all the chips D except the defective products is completed, the dicing blue films 16, the wafer rings 14, and the like that hold the chips D in the outer shape of the wafer 11 are unloaded to the wafer cassette (step P18).
The appearance inspection of the crack is performed at least at one of the chip supply unit, the intermediate stage, and the mounting stage, which are the places where the chip position recognition is performed, but is more preferably performed at all places. If the detection is performed at the chip supply portion, the crack can be detected quickly. If the detection is performed on the intermediate stage, it is possible to detect a crack that cannot be detected in the chip supply unit before mounting or a crack that occurs after the pickup step (a crack that has not yet developed before the mounting step). Further, when the mounting is performed on the mounting stage, cracks (cracks that have not yet developed before the mounting step) that cannot be detected in the chip supply unit and the intermediate stage or cracks that have occurred after the mounting step can be detected before the next chip is stacked and mounted or before the substrate is discharged.
The present invention has been described specifically based on the embodiments and examples, but the present invention is not limited to the embodiments and examples described above, and various modifications can be made.
For example, in the embodiment, the chip position recognition is performed after the chip position recognition, but the chip position recognition may be performed after the chip position recognition.
In the embodiment, DAF is attached to the back surface of the wafer, but DAF may not be present.
In the embodiment, the pickup head and the mounting head are provided separately, but two or more heads may be provided separately. In the embodiment, the intermediate stage is provided, but the intermediate stage may not be provided. In this case, the pick-up head and the mounting head can be used in combination.
In addition, although the chip is mounted with the surface facing upward in the embodiment, the chip may be mounted with the back and front surfaces facing upward after the chip is picked up. In this case, the intermediate stage may not be provided. This device is called a flip chip mounter.
In the embodiment, the mounting head is provided, but the mounting head may not be provided. In this case, the picked-up chip is mounted on a container or the like. This device is called a pick-up device.

Claims (15)

1. A chip mounting device is provided with:
a shooting device for shooting the chip;
an illumination device for illuminating the chip obliquely with respect to an optical system axis of the imaging device; and
a control device for controlling the shooting device and the lighting device,
the control device is configured to irradiate the chip with light having a wavelength shorter than green in a visible light region by the illumination device and to image the chip by the imaging device in order to detect a crack formed in the chip.
2. The chip mounting apparatus according to claim 1,
the lighting device is configured to irradiate the chip with blue light using a blue LED as a light source.
3. The chip mounting apparatus according to claim 1,
the illumination device is configured to irradiate the chip with blue light by transmitting a white light source through a short-wavelength pass filter.
4. The chip mounting apparatus according to claim 1,
the control device is configured to, when recognizing the position of the chip, irradiate white light from a second illumination device and image the chip by the imaging device.
5. The chip mounting apparatus according to claim 1,
the illumination device is configured to irradiate the chip with blue light by transmitting light from a white light source through a short-wave pass filter,
the control device is configured to irradiate white light without transmitting light from the white light source through the short-wavelength pass filter when recognizing the position of the chip, and to image the chip by the imaging device.
6. The chip mounting apparatus according to claim 1,
further comprises a chip supply unit having a wafer ring holder for holding the dicing blue film to which the chip is attached,
the control device is configured to take an image of the chip attached to the cut blue film using the imaging device and the illumination device.
7. The chip mounting apparatus according to claim 1,
further comprises a mounting head for mounting the chip on a substrate or on a mounted chip,
the control device is configured to take an image of the chip attached to the substrate or the chip using the imaging device and the illumination device.
8. The die bonding apparatus according to claim 1, further comprising:
a pickup head picking up the chip; and
an intermediate stage on which the picked-up chip is placed,
the control device is configured to image the chip mounted on the intermediate stage using the imaging device and the illumination device.
9. The chip mounting apparatus according to claim 1,
in the chip, the area of the region constituted by the repeating pattern is larger than the area of the region not constituted by the repeating pattern.
10. The chip mounting apparatus according to claim 1,
the chip is a semiconductor memory device.
11. A method for manufacturing a semiconductor device, comprising the steps of:
(a) a step of carrying in a wafer ring holder for holding a dicing blue film to which a chip is attached to the die bonding apparatus according to any one of claims 1 to 5;
(b) a step of carrying in a substrate;
(c) a step of picking up the chip; and
(d) and a step of mounting the picked-up chip on the substrate or a chip already mounted on the substrate.
12. The method for manufacturing a semiconductor device according to claim 11,
in the step (c), the picked-up chip is placed on an intermediate stage,
in the step (d), the chip mounted on the intermediate stage is picked up.
13. The method for manufacturing a semiconductor device according to claim 11,
the method further includes, before the step (c), a step (e) of inspecting an appearance of the chip using the imaging device and the illumination device.
14. The method for manufacturing a semiconductor device according to claim 11,
the method further includes a step (f) of inspecting an appearance of the chip using the imaging device and the illumination device after the step (d).
15. The method for manufacturing a semiconductor device according to claim 12,
the method further includes a step (g) of inspecting an appearance of the chip using the imaging device and the illumination device after the step (c) and before the step (d).
CN202110197928.3A 2020-03-23 2021-02-22 Chip mounting apparatus and method for manufacturing semiconductor device Active CN113436986B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020051130A JP7437987B2 (en) 2020-03-23 2020-03-23 Die bonding equipment and semiconductor device manufacturing method
JP2020-051130 2020-03-23

Publications (2)

Publication Number Publication Date
CN113436986A true CN113436986A (en) 2021-09-24
CN113436986B CN113436986B (en) 2024-02-20

Family

ID=77752817

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110197928.3A Active CN113436986B (en) 2020-03-23 2021-02-22 Chip mounting apparatus and method for manufacturing semiconductor device

Country Status (4)

Country Link
JP (1) JP7437987B2 (en)
KR (1) KR102516586B1 (en)
CN (1) CN113436986B (en)
TW (1) TWI765517B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115312438A (en) * 2022-03-21 2022-11-08 北京芯士联半导体科技有限公司 Push pin structure of joint device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100920730B1 (en) * 2008-12-24 2009-10-07 주식회사 이큐스팜 Lighting apparatus and method for imaging device
CN106920762A (en) * 2015-12-24 2017-07-04 捷进科技有限公司 Semiconductor- fabricating device, the manufacture method of semiconductor devices and chip attachment machine
CN107086185A (en) * 2016-02-16 2017-08-22 三菱电机株式会社 The manufacture method of the check device of chip, the inspection method of chip and semiconductor device
JP2018011048A (en) * 2016-07-05 2018-01-18 キヤノンマシナリー株式会社 Defect detector, defect detection method, wafer, semiconductor chip, semiconductor device, die bonder, bonding method, semiconductor manufacturing method, and semiconductor device manufacturing method
JP2019029425A (en) * 2017-07-27 2019-02-21 ファスフォードテクノロジ株式会社 Die bonding apparatus, manufacturing method of semiconductor apparatus, and semiconductor manufacturing system
CN109524320A (en) * 2017-09-19 2019-03-26 捷进科技有限公司 The manufacturing method of semiconductor manufacturing apparatus and semiconductor devices
CN109564172A (en) * 2016-07-05 2019-04-02 佳能机械株式会社 Defect detecting device, defect inspection method, chip, semiconductor chip, semiconductor device, bare die jointing machine, joint method, semiconductor making method and manufacturing method for semiconductor device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03192800A (en) * 1989-12-21 1991-08-22 Sharp Corp Component mounting recognition method for printed board
JPH10209227A (en) * 1997-01-20 1998-08-07 Sony Corp System and device for inspecting semiconductor integrated circuit, and method for inspecting semiconductor circuit
JP3851468B2 (en) * 1999-07-09 2006-11-29 富士写真フイルム株式会社 Method and apparatus for bonding light emitting components
JP5525336B2 (en) * 2010-06-08 2014-06-18 株式会社日立ハイテクノロジーズ Defect inspection method and defect inspection apparatus
JP6120094B2 (en) * 2013-07-05 2017-04-26 ソニー株式会社 Solid-state imaging device, manufacturing method thereof, and electronic apparatus
KR101501129B1 (en) 2013-08-23 2015-03-12 주식회사 고영테크놀러지 Substrate inspection apparatus
JP5784796B2 (en) * 2014-06-02 2015-09-24 株式会社日立製作所 Surface inspection apparatus and method
US20170234837A1 (en) * 2014-10-24 2017-08-17 Renishaw Plc Acoustic apparatus and method
EP3926330A1 (en) * 2014-12-05 2021-12-22 Kla-Tencor Corporation Apparatus and method for defect detection in work pieces
JP6846958B2 (en) * 2017-03-09 2021-03-24 ファスフォードテクノロジ株式会社 Manufacturing method of die bonding equipment and semiconductor equipment
JP6975551B2 (en) * 2017-05-18 2021-12-01 ファスフォードテクノロジ株式会社 Semiconductor manufacturing equipment and methods for manufacturing semiconductor equipment
JP7018341B2 (en) * 2018-03-26 2022-02-10 ファスフォードテクノロジ株式会社 Manufacturing method of die bonding equipment and semiconductor equipment
JP7102271B2 (en) 2018-07-17 2022-07-19 ファスフォードテクノロジ株式会社 Semiconductor manufacturing equipment and manufacturing method of semiconductor equipment

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100920730B1 (en) * 2008-12-24 2009-10-07 주식회사 이큐스팜 Lighting apparatus and method for imaging device
CN106920762A (en) * 2015-12-24 2017-07-04 捷进科技有限公司 Semiconductor- fabricating device, the manufacture method of semiconductor devices and chip attachment machine
CN107086185A (en) * 2016-02-16 2017-08-22 三菱电机株式会社 The manufacture method of the check device of chip, the inspection method of chip and semiconductor device
JP2018011048A (en) * 2016-07-05 2018-01-18 キヤノンマシナリー株式会社 Defect detector, defect detection method, wafer, semiconductor chip, semiconductor device, die bonder, bonding method, semiconductor manufacturing method, and semiconductor device manufacturing method
CN109564172A (en) * 2016-07-05 2019-04-02 佳能机械株式会社 Defect detecting device, defect inspection method, chip, semiconductor chip, semiconductor device, bare die jointing machine, joint method, semiconductor making method and manufacturing method for semiconductor device
JP2019029425A (en) * 2017-07-27 2019-02-21 ファスフォードテクノロジ株式会社 Die bonding apparatus, manufacturing method of semiconductor apparatus, and semiconductor manufacturing system
CN109524320A (en) * 2017-09-19 2019-03-26 捷进科技有限公司 The manufacturing method of semiconductor manufacturing apparatus and semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李建平;邹中升;王福亮;: "热超声倒装键合机视觉系统的设计与实现", 中南大学学报(自然科学版), no. 01 *

Also Published As

Publication number Publication date
JP7437987B2 (en) 2024-02-26
JP2021150586A (en) 2021-09-27
CN113436986B (en) 2024-02-20
KR20210118742A (en) 2021-10-01
TW202138790A (en) 2021-10-16
KR102516586B1 (en) 2023-04-03
TWI765517B (en) 2022-05-21

Similar Documents

Publication Publication Date Title
CN106920762B (en) Semiconductor manufacturing apparatus, semiconductor device manufacturing method, and chip mounter
CN108573901B (en) Bare chip bonding apparatus and method for manufacturing semiconductor device
CN110729210B (en) Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
JP7225337B2 (en) Semiconductor manufacturing equipment and semiconductor device manufacturing method
CN109524320B (en) Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
KR102641333B1 (en) Die bonding apparatus and manufacturing method of semiconductor device
CN113436986B (en) Chip mounting apparatus and method for manufacturing semiconductor device
CN111725086B (en) Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
CN115410947A (en) Chip mounting device and method for manufacturing semiconductor device
CN116403936A (en) Semiconductor manufacturing apparatus, inspection apparatus, and method for manufacturing semiconductor device
JP2023100561A (en) Semiconductor manufacturing device, inspection device, and method for manufacturing semiconductor
JP2023100562A (en) Semiconductor manufacturing device, inspection device, and method for manufacturing semiconductor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant