CN113436986B - Chip mounting apparatus and method for manufacturing semiconductor device - Google Patents

Chip mounting apparatus and method for manufacturing semiconductor device Download PDF

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Publication number
CN113436986B
CN113436986B CN202110197928.3A CN202110197928A CN113436986B CN 113436986 B CN113436986 B CN 113436986B CN 202110197928 A CN202110197928 A CN 202110197928A CN 113436986 B CN113436986 B CN 113436986B
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China
Prior art keywords
chip
substrate
illumination
mounting
wafer
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CN202110197928.3A
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CN113436986A (en
Inventor
小桥英晴
保坂浩二
吉山仁晃
小野悠太
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Fasford Technology Co Ltd
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Fasford Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Abstract

The invention provides a technology capable of improving recognition accuracy of cracks. The chip mounting device is provided with: a shooting device for shooting the chip; an illumination device for illuminating the chip obliquely with respect to an optical system axis of the photographing device; and a control device for controlling the photographing device and the lighting device. The control device is configured to irradiate the chip with light having a wavelength shorter than green in a visible light region by the illumination device and to photograph the chip by the photographing device in order to detect a crack formed in the chip.

Description

Chip mounting apparatus and method for manufacturing semiconductor device
Technical Field
The present invention relates to a die attach apparatus, which can be applied to a die attach machine for detecting a die crack, for example.
Background
A step of mounting a semiconductor chip (hereinafter, simply referred to as a chip) on a wiring board, a lead frame, or the like (hereinafter, simply referred to as a board) and assembling and packaging is provided as part of a manufacturing process of a semiconductor device, and a step of dividing the chip from a semiconductor wafer (hereinafter, simply referred to as a wafer) (dicing step) and a mounting step of mounting the divided chip on a board are provided as part of a step of assembling and packaging. The semiconductor manufacturing apparatus used in the mounting process is a chip mounting apparatus such as a chip mounter.
In the dicing step, cracks may be generated in the chip extending from the dicing surface to the inside due to cutting resistance or the like at the time of dicing. Therefore, in the mounting step, the chip is photographed by a camera to perform surface inspection (appearance inspection).
Prior art literature
Patent literature
Patent document 1: japanese patent application laid-open No. 2019-54203
Disclosure of Invention
Since a protective film (surface protective film) formed of a polyimide film or the like on the surface of a chip is a layer that can transmit irradiation light from an illumination device, it is sometimes difficult to detect cracks formed from the upper surface or the lower surface of the surface protective film toward a substrate of silicon or the like, depending on the thickness of the surface protective film, the concave-convex pattern formed under the surface protective film, or the like.
The invention provides a technique capable of improving recognition accuracy of cracks.
The summary of the content representative of the present invention will be briefly described as follows:
that is, the chip mounting apparatus includes: a shooting device for shooting the chip; an illumination device for illuminating the chip obliquely with respect to an optical system axis of the photographing device; and a control device for controlling the photographing device and the lighting device. The control device is configured to: in order to detect cracks formed in the chip, the chip is irradiated with light having a wavelength shorter than green in the visible light region by the illumination device, and the chip is photographed by the photographing device.
Effects of the invention
According to the chip mounting device, the crack recognition accuracy can be improved.
Drawings
Fig. 1 is a schematic plan view showing an exemplary configuration of a chip mounter.
Fig. 2 is a diagram illustrating a schematic configuration when viewed from the arrow a direction in fig. 1.
Fig. 3 is a schematic cross-sectional view showing a main part of the chip supply unit of fig. 1.
Fig. 4 is a block diagram showing a schematic configuration of a control system of the chip mounter of fig. 1.
Fig. 5 is a flowchart illustrating a die attach process in the die attach machine of fig. 1.
Fig. 6 is a schematic diagram illustrating oblique illumination.
Fig. 7 is a diagram illustrating a crack and its background.
Fig. 8 is a diagram illustrating differences in visual performance of a pattern generated based on illumination colors.
Fig. 9 is a graph showing measurement results of coordinates in the field of view and crack and background illuminance on the chip surface.
Description of the reference numerals
BD … chip mounting device
CM … shooting device
CNT … control device
D … chip
LD … lighting device
Detailed Description
First, the technology studied by the present inventors will be described with reference to fig. 6 to 9. Fig. 6 is a schematic diagram illustrating oblique illumination. Fig. 7 is a diagram illustrating a crack and its background, where (a) of fig. 7 is a diagram illustrating an image in a case where a difference in brightness contrast between the crack and the background is large, and (b) of fig. 7 is a diagram illustrating an image in a case where a difference in brightness contrast between the crack and the background is small. Fig. 8 is a diagram illustrating differences in visual performance of a pattern generated based on an illumination color, where (a) of fig. 8 is an image in the case where the illumination color is blue, (b) of fig. 8 is an image in the case where the illumination color is green, and (c) of fig. 8 is an image in the case where the illumination color is red. Fig. 9 is a graph showing measurement results of coordinates in the field of view, cracks on the chip surface, and background illuminance, where (a) of fig. 9 is white illumination, (b) of fig. 9 is blue illumination, and (c) of fig. 9 is red illumination.
When the crack inspection function using an image obtained by a camera is designed, the illumination configuration includes a bright field system in which "the background is captured to be bright and the content to be observed is captured to be dark" and a dark field system in which "the background is captured to be dark and the content to be observed is captured to be bright". In general, dark-field method is preferable for inspecting microscopic flaws. When the wafer surface is close to the mirror surface and inspected by the dark field method, it is preferable to use oblique illumination, which is an illumination method of illuminating light from an oblique direction. As shown in fig. 6, when detecting a crack in the chip D, it is easier to illuminate the crack by making the incident angle (θ) of oblique illumination of the illumination device LD as close as possible to the axis of the optical system of the imaging device CM (making the incident angle (θ) as close as possible to 0). In this specification, this illumination is referred to as high angle crack detection illumination.
The spectral reflectance of the memory cell layer varies depending on the thinning of the surface protective film formed of a polyimide film or the like, the multilayering of the surface memory, and the like. Therefore, under the high angle crack detection illumination, as shown in fig. 7 (b), a pattern such as a stripe pattern may be exposed on the memory cells of the memory array MARY on the chip surface. When the fringe pattern appears in the background, it becomes difficult to distinguish the fringe pattern from the crack CRK. That is, the streak pattern prevents separation of a crack region from other regions by image processing, and makes it difficult to detect a crack having a small difference in brightness contrast from the background and accurately measure the crack length. In the case where the area of the region formed of the repeated pattern is larger than the area of the other region like the memory array MARY, the influence is large.
As shown in fig. 8, the longer the illumination wavelength of oblique illumination used in the present fringe pattern, the more conspicuous it is; the shorter the length, the less visible will disappear.
When the crack and background illuminance on the chip surface are measured, as shown in fig. 9 (a), a portion (a) whose local brightness is bright under white illumination is a crack, and (B) in fig. 9 (a) is the brightness of the background, (C) is a region where the memory cell is exposed and bright, and (D) is a region of total reflection. Regarding the area where the memory cell is exposed and becomes bright under the white illumination shown in (C) of fig. 9, the area becomes absent under the blue illumination of (b) of fig. 9, and there is an area where the memory cell is exposed and becomes extremely bright under the red illumination shown in (C) of fig. 9. Therefore, it is found that the portion where the background brightness is bright under white illumination is caused by the red component in white.
The above-mentioned differences based on illumination color are due to:
(a) Differences in absorption spectra of the surface protective films (blue light is more easily absorbed);
(b) Interference of light of the surface protective film (red light is more likely to interfere);
(c) The difference in the reflection spectrum of the short (shot) portion (chip surface) in the memory layer of the silicon surface layer (red light is more easily reflected).
That is, this is because the longer the wavelength in the visible light region, the higher the reflectance of the chip surface and the polyimide film interposed therebetween, and thus transmission and interference occur, so that the memory cell pattern on the chip surface is visible. In contrast, this is because the shorter the wavelength is, the less its characteristics are, and only the diffused light of the crack is reflected.
Therefore, as shown in fig. 6, the die attach device BD in the embodiment includes an imaging device CM and an illumination device LD. The illumination device LD uses illumination of light of a color shorter in wavelength than green in the visible light region so that the surface does not reveal the fringe pattern. For example, a blue LED or a violet LED is used as the light source. The light source to be used may be a white light source that transmits through a short-wavelength filter (short pass filter) in addition to a light source that emits blue light (for example, a blue LED). Here, the short-wavelength filter is a wavelength (color) separation filter that can transmit light on the short wavelength side and intercept light on the long wavelength side by sharp activation. The short-pass filter used as the optical filter is preferably, for example, a cyan filter (blue filter) that cuts red and transmits blue.
The illumination device LD is preferably a skew illumination. Further, oblique illumination is more preferably at a high angle. The illumination device LD may be a ring-shaped illumination with oblique light or a strip illumination with oblique light. The incident angle (θ) is, for example, preferably more than 0 degrees and 30 degrees or less, and more preferably 5 degrees or more and 15 degrees or less.
This can make the contrast between the crack and the background higher. Regarding a crack imaged by a camera as a contrast difference, separation of a crack imaged to be shallow (low contrast) from its background becomes easy, so that detection of a crack having a narrower width is enabled. In addition, the inspection sensitivity equivalent to that of a product having no background streak pattern can be obtained. Thereby, the inspection sensitivity is improved, and the inspection is stabilized.
In addition, in the case of performing positioning or position inspection (hereinafter, collectively referred to as position recognition) of the chip and the substrate, illumination of a white light source is used. Further, a white light source (white LED or the like) may be used for illumination, and blue light or violet light may be emitted through the short-pass filter when detecting a chip crack, and white light may be emitted without being emitted through the short-pass filter when performing position recognition. In addition, a light source different from that used for chip crack detection may be provided in positioning or position inspection of the chip and the substrate.
Hereinafter, embodiments will be described using the drawings. However, in the following description, the same reference numerals are given to the same components, and overlapping description may be omitted. In order to make the description more clear, the width, thickness, shape, and the like of each portion may be schematically shown in the drawings as compared with the actual form, but the explanation of the present invention is not limited to this.
Examples
Fig. 1 is a plan view schematically showing a die mounter of an embodiment. Fig. 2 is a diagram illustrating operations of the pick-up head and the mounting head when viewed from the arrow a direction in fig. 1.
The die mounter 10 basically has: a chip supply section 1 that supplies a chip D to be mounted on a substrate S; a pickup section 2; an intermediate stage section 3; a mounting part 4; a conveying unit 5; a substrate supply unit 6; a substrate carrying-out section 7; and a control unit 8 for monitoring and controlling the operation of each part. The Y-axis direction is the front-rear direction of the chip mounter 10, and the X-axis direction is the left-right direction. The chip supply unit 1 is disposed on the front side of the chip mounter 10, and the mounting unit 4 is disposed on the back side. Here, one or a plurality of product regions (hereinafter referred to as package regions P) which eventually become one package are printed on the substrate S.
First, the chip supply section 1 supplies the chip D to be mounted on the package region P of the substrate S. The chip supply unit 1 includes a wafer holding table 12 for holding a wafer 11, and a jack unit 13 shown by a broken line for jack up chips D from the wafer 11. The chip supply section 1 moves in the XY directions by a driving mechanism not shown, and moves the chip D to be picked up to the position of the lift unit 13.
The pickup section 2 includes: a pick-up head 21 that picks up the chip D; a pickup head Y drive section 23 for moving the pickup head 21 in the Y direction; and driving units (not shown) for moving the collet 22 in the X direction while lifting and rotating the collet. The pickup head 21 has a collet 22 (see also fig. 2) for holding the lifted chip D at the tip, picks up the chip D from the chip supply unit 1, and mounts the chip D on the intermediate stage 31. The pickup head 21 has driving parts, not shown, for lifting and lowering the collet 22, rotating it, and moving it in the X direction.
The intermediate stage unit 3 includes an intermediate stage 31 on which the chip D is temporarily placed, and a stage recognition camera 32 for recognizing the chip D on the intermediate stage 31.
The mounting unit 4 picks up the chip D from the intermediate stage 31 and mounts it on the package region P of the substrate S that has been carried, or mounts it so as to overlap the chip mounted on the package region P of the substrate S. The mounting portion 4 includes: the mounting head 41 includes a collet 42 (see also fig. 2) for holding the chip D at the tip in a suction manner, like the pickup head 21; a Y driving section 43 for moving the mounting head 41 in the Y direction; and a substrate recognition camera 44 for capturing a position recognition mark (not shown) of the package region P of the substrate S and recognizing the mounting position. According to this configuration, the mounting head 41 corrects the pickup position and posture based on the pickup data of the stage recognition camera 32, picks up the chip D from the intermediate stage 31, and mounts the chip D on the substrate based on the pickup data of the substrate recognition camera 44.
The conveying section 5 includes a substrate conveying claw 51 for holding and conveying the substrate S, and a conveying path (lane) 52 for moving the substrate S. The substrate S is moved by driving a nut (not shown) of the substrate conveyance claw 51 provided in the conveyance path 52 by a ball screw (not shown) provided along the conveyance path 52. According to this configuration, the substrate S is moved from the substrate supply unit 6 to the mounting position along the conveyance path 52, and after mounting, is moved to the substrate carry-out unit 7, and the substrate S is delivered to the substrate carry-out unit 7.
The control unit 8 includes: a memory storing a program (software) for monitoring and controlling the operations of the respective parts of the chip mounter 10; and a Central Processing Unit (CPU) executing the program stored in the memory.
Next, the structure of the chip supply unit 1 will be described with reference to fig. 3. Fig. 3 is a schematic cross-sectional view showing a main part of the chip supply unit of fig. 1.
The chip supply unit 1 includes a wafer holding table 12 that moves in the horizontal direction (XY direction) and a jack-up unit 13 that moves in the up-down direction. The wafer holding table 12 has an extension ring 15 for holding the wafer ring 14, and a support ring 17 for horizontally positioning a dicing film (dicing tape) 16 held by the wafer ring 14 and to which a plurality of chips D are bonded. The jack-up unit 13 is arranged inside the support ring 17.
The chip supply unit 1 lowers the extension ring 15 holding the wafer ring 14 when the chip D is lifted up. As a result, the dicing blue film 16 held by the wafer ring 14 is stretched to increase the pitch of the chips D, and the chips D are lifted up from below the chips D by the lifting unit 13, thereby improving the pick-up performance of the chips D. In addition, as the thickness of the adhesive agent for bonding the chip to the substrate becomes thinner, a film-like adhesive material called a film-on-film (DAF) 18 is attached between the wafer 11 and the dicing blue film 16. In the wafer 11 having the adhesive sheet film 18, dicing is performed on the wafer 11 and the adhesive sheet film 18. Therefore, in the peeling step, the wafer 11 and the adhesive sheet film 18 are peeled from the dicing blue film 16. Further, the presence of the adhesive sheet film 18 is omitted for explanation later.
The die mounter 10 has: a wafer recognition camera 24 for recognizing the posture of the chip D on the wafer 11; a stage recognition camera 32 for recognizing the posture of the chip D mounted on the intermediate stage 31; and a substrate recognition camera 44 for recognizing the mounting position on the mounting table BS. The cameras that must perform correction of the positional deviation between the recognition cameras are the stage recognition cameras 32 related to pickup by the mounting head 41 and the board recognition cameras 44 related to mounting to the mounting position by the mounting head 41. In the present embodiment, the illumination device described in the embodiment is used together with the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44 to detect the crack of the chip D.
The control unit 8 will be described with reference to fig. 4. Fig. 4 is a block diagram showing a schematic configuration of the control system. The control system 80 includes a control unit 8, a driving unit 86, a signal unit 87, and an optical system 88. The control unit 8 generally includes a control and arithmetic device 81 mainly composed of CPU (Central Processor Unit), a storage device 82, an input/output device 83, a bus 84, and a power supply unit 85. The storage device 82 includes a main storage device 82a made of RAM in which a processing program and the like are stored, and an auxiliary storage device 82b made of HDD in which control data, image data, and the like necessary for control are stored. The input/output device 83 includes: a monitor 83a for displaying device status, information, etc.; a touch panel 83b for inputting an instruction of an operator; a mouse 83c for operating the monitor; and an image taking-in device 83d that takes in the image data from the optical system 88. The input/output device 83 includes: a motor control device 83e for controlling a driving unit 86 such as a ZY drive shaft of an XY stage (not shown) and a mounting head stage of the chip supply unit 1; and an I/O signal control device 83f that takes in or controls various sensor signals and takes in or controls signals from a signal section 87 such as a switch of the lighting device or the like. The optical system 88 includes the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44. The control and arithmetic device 81 takes in necessary data via the bus 84, performs arithmetic operation, and transmits information to the control of the pickup head 21 and the like and the monitor 83a and the like.
The control unit 8 stores the image data captured by the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44 in the storage device 82 via the image capturing device 83d. The positioning of the package region P of the chip D and the substrate S and the surface inspection of the chip D and the substrate S are performed by software programmed based on the stored image data using the control and arithmetic device 81. The driving unit 86 is operated by software through the motor control device 83e based on the positions of the chip D and the package region P of the substrate S calculated by the control and calculation device 81. The positioning of the chips on the wafer is performed by this process, and the chips D are mounted on the package region P of the substrate S by the operation of the driving sections of the pick-up section 2 and the mounting section 4. The wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44 to be used are grayscale cameras, color cameras, and the like, and the light intensity is digitized.
Fig. 5 is a flowchart illustrating a die attach process in the die attach machine of fig. 1.
In the die attach process of the embodiment, first, the control unit 8 takes out the wafer ring 14 holding the wafer 11 from the cassette, places the wafer ring on the wafer holding table 12, and conveys the wafer holding table 12 to the reference position where the pick-up of the die D is performed (wafer loading (step P1)). Next, the control unit 8 performs fine adjustment based on the image acquired by the wafer recognition camera 24 so that the arrangement position of the wafer 11 accurately matches the reference position.
Next, the control unit 8 moves the wafer holding table 12 on which the wafer 11 is mounted at a predetermined pitch, and holds the wafer holding table at a horizontal level, thereby placing the chip D to be picked up at the pickup position (chip conveyance (step P2)). The wafer 11 is inspected for each chip by an inspection device such as a prober in advance, map data (map data) indicating pass or fail is generated for each chip, and stored in the storage device 82 of the control unit 8. Whether the chip D to be picked up is a good or a bad is determined based on the map data. When the chip D is a defective product, the control unit 8 moves the wafer holding table 12 on which the wafer 11 is mounted at a predetermined pitch, places the chip D to be picked up next at the pickup position, and skips the chip D of the defective product.
The control unit 8 photographs the main surface (upper surface) of the chip D, which is the object of pickup, with the wafer recognition camera 24, and calculates the amount of positional displacement of the chip D, which is the object of pickup, with respect to the pickup position from the acquired image. The control unit 8 moves the wafer holding table 12 on which the wafer 11 is mounted based on the positional deviation amount, and accurately positions the chip D, which is the object of pickup, to the pickup position (chip positioning (step P3)).
Next, the control unit 8 performs surface inspection of the chip D based on the image acquired by the wafer recognition camera 24 (step P4). Here, the control unit 8 determines whether there is a problem by surface inspection, and proceeds to the next process (process P9 described later) when it is determined that there is no problem on the surface of the chip D, but when it is determined that there is a problem, the control unit visually confirms the surface image, performs inspection with higher sensitivity, performs inspection with changing the illumination condition, or the like, and when there is a problem, performs skip processing, and when there is no problem, performs processing of the next process. The skip processing is to skip the processes P9 and subsequent steps of the chips D, to move the wafer holding table 12 on which the wafer 11 is mounted at a predetermined pitch, and to dispose the chips D to be picked up next at the pick-up position.
The control unit 8 places the substrate S on the transfer path 52 by the substrate supply unit 6 (substrate loading (step P5)). The control unit 8 moves the substrate transfer claw 51 that holds the transfer substrate S to the mounting position (substrate transfer (step P6)). The substrate is photographed and positioned by the substrate recognition camera 44 (substrate positioning (step P7)).
Next, the control unit 8 performs surface inspection of the package region P of the substrate S based on the image acquired by the substrate recognition camera 44 (step P8). Here, the control unit 8 determines whether there is a problem by surface inspection, and proceeds to the next process (process P9 described later) when it is determined that there is no problem on the surface of the package region P of the substrate S, but when it is determined that there is a problem, visually checks the surface image, or performs a higher-sensitivity inspection, an inspection for changing the illumination condition, or the like, and when there is a problem, skips, and when there is no problem, proceeds to the next process. The skip processing is processing after the step P10 of skipping the corresponding piece of the package region P of the substrate S, and performs reject registration in the substrate rework information.
After the chip D, which is the object of pickup, is accurately placed at the pickup position by the chip supply unit 1, the control unit 8 picks up the chip D from the dicing film 16 by the pickup head 21 including the collet 22 (chip processing (step P9)) and places the chip D on the intermediate stage 31 (step P10). The control unit 8 detects the posture deviation (rotational deviation) of the chip mounted on the intermediate stage 31 by shooting with the stage recognition camera 32 (step P11). When there is a posture deviation, the control unit 8 corrects the posture deviation by rotating the intermediate stage 31 in a plane parallel to the mounting surface having the mounting position by a rotation driving device (not shown) provided to the intermediate stage 31.
The control unit 8 performs surface inspection of the chip D based on the image acquired by the stage recognition camera 32 (step P12). Here, the control unit 8 determines whether there is a problem by surface inspection, and if it is determined that there is no problem on the surface of the chip D, proceeds to the next step (step P13 described later), but if it is determined that there is a problem, visually checks the surface image, or performs an inspection with higher sensitivity, an inspection with changing illumination conditions, or the like, and if there is a problem, places the chip on a defective tray or the like, which is not shown, and performs skip processing, and if there is no problem, proceeds to the next step. The skip processing is to skip the processes P13 and subsequent steps of the chips D, to move the wafer holding table 12 on which the wafer 11 is mounted at a predetermined pitch, and to dispose the chips D to be picked up next at the pick-up position.
The control section 8 picks up the chip D from the intermediate stage 31 by the mounting head 41 including the collet 42, and mounts the chip in the package region P of the substrate S or onto the chip already mounted in the package region P of the substrate S (chip mounting ((step P13)).
After mounting the chip D, the control unit 8 checks whether or not the mounting position is accurate (checks the relative position between the chip and the substrate (step P14)). In this case, the center of the chip and the center of the chip portion are obtained in the same manner as the alignment of the chip described later, and whether the relative position is accurate or not is checked.
Next, the control unit 8 performs surface inspection of the chip D and the substrate S based on the image acquired by the substrate recognition camera 44 (step P15). Here, the control unit 8 determines whether there is a problem by surface inspection, and proceeds to the next process (process P9 described later) when it is determined that there is no problem on the surface of the mounted chip D, but when it is determined that there is a problem, visually checks the surface image, or performs a higher sensitivity inspection, or an inspection to change the illumination condition, and when there is a problem, skips, and when there is no problem, proceeds to the next process. In the skip processing, reject registration is performed in the substrate rework information.
Thereafter, the chips D are mounted one by one to the package regions P of the substrate S in the same step. When mounting of one substrate is completed, the substrate S is moved to the substrate carrying-out section 7 by the substrate carrying claw 51 (substrate carrying-in (step P16)), and the substrate S is delivered to the substrate carrying-out section 7 (substrate unloading (step P17)).
Thereafter, the chips D are peeled off from the dicing blue film 16 one by one in the same manner (step P9). When the pickup of all chips D except for the defective products is completed, dicing blue film 16 and wafer ring 14, etc. which have been held by the chips D in the outer shape of wafer 11, are unloaded to a wafer cassette (step P18).
The appearance inspection of the crack is performed at least at one place of the chip supply unit, the intermediate stage, and the mounting stage, which are places where the chip position recognition is performed, but is more preferably performed at all places. If the chip supply part is provided, cracks can be detected quickly. If the detection is performed on the intermediate stage, it is possible to detect a crack that has not been detected by the chip supply unit before mounting or a crack that has occurred after the pick-up step (a crack that has not yet developed before the mounting step). Further, if the process is performed on the mounting table, it is possible to detect cracks (cracks that have not yet developed before the mounting process) that have not been detected on the chip supply unit and the intermediate table or cracks that have developed after the mounting process, before the mounting of the next chip is stacked or before the substrate is discharged.
The invention completed by the present inventors has been specifically described above based on the embodiments and examples, but the invention is not limited to the embodiments and examples, and various modifications are naturally possible.
For example, in the embodiment, the chip appearance inspection recognition is performed after the chip position recognition, but the chip position recognition may be performed after the chip appearance inspection recognition.
In the embodiment, the DAF is attached to the back surface of the wafer, but the DAF may be omitted.
In the embodiment, there is one pick-up head and one mounting head, respectively, but two or more pick-up heads and mounting heads may be provided, respectively. In the embodiment, the intermediate stage is provided, but the intermediate stage may be omitted. In this case, the pick-up head and the mounting head may be used together.
In the embodiment, the surface of the chip is mounted upward, but the back of the chip may be mounted upward by turning the front and back of the chip after the chip is picked up. In this case, the intermediate stage may not be provided. This device is called flip chip bonder (flip chip bonder).
In the embodiment, the mounting head is provided, but the mounting head may be omitted. In this case, the picked-up chip is mounted on a container or the like. This device is called a pick-up device.

Claims (11)

1. A chip mounting device is characterized by comprising:
a shooting device for shooting the chip;
an illumination device for illuminating the chip obliquely with respect to an optical system axis of the photographing device; and
a control device for controlling the photographing device and the illumination device,
the illumination device is configured to irradiate the chip with blue light by transmitting light from a white light source through a short-pass filter,
the control device is configured to:
in the case of detecting cracks formed in the chip, blue light is irradiated by the illumination device, and the chip is photographed by the photographing device,
when the position of the chip is recognized, the light from the white light source is irradiated with white light without being transmitted through the short-wavelength filter, and the chip is photographed by the photographing device.
2. The chip mounter according to claim 1, wherein,
the wafer carrier is further provided with a chip supply part, wherein the chip supply part is provided with a wafer ring holder for holding the dicing blue film attached with the chips,
the control device is configured to take an image of the chip attached to the dicing blue film using the imaging device and the illumination device.
3. The chip mounter according to claim 1, wherein,
further comprises a mounting head for mounting the chip on a substrate or on a mounted chip,
the control device is configured to take an image of a chip mounted on the substrate or the chip using the imaging device and the illumination device.
4. The chip mounter according to claim 1, further comprising:
a pick-up head picking up the chip; and
an intermediate stage on which the chip to be picked up is mounted,
the control device is configured to take an image of the chip mounted on the intermediate stage using the imaging device and the illumination device.
5. The chip mounter according to claim 1, wherein,
in the chip, the area of the region constituted by the repeated pattern is larger than the area of the region not constituted by the repeated pattern.
6. The chip mounter according to claim 1, wherein,
the chip is a semiconductor memory device.
7. A method for manufacturing a semiconductor device is characterized by comprising the steps of:
(a) A step of loading a wafer ring holder for holding a dicing blue film to which a chip is attached into the chip mounting apparatus according to claim 1;
(b) A step of loading a substrate;
(c) Picking up the chip; and
(d) And a step of mounting the picked-up chip on the substrate or on a chip mounted on the substrate.
8. The method for manufacturing a semiconductor device according to claim 7, wherein,
in the step (c), the picked-up chips are placed on an intermediate stage,
in the step (d), the chip mounted on the intermediate stage is picked up.
9. The method for manufacturing a semiconductor device according to claim 7, wherein,
and (e) before the step (c), checking the appearance of the chip by using the photographing device and the lighting device.
10. The method for manufacturing a semiconductor device according to claim 7, wherein,
and (f) after the step (d), inspecting the appearance of the chip by using the imaging device and the illumination device.
11. The method for manufacturing a semiconductor device according to claim 8, wherein,
and (g) after the step (c) and before the step (d), wherein the appearance of the chip is inspected by using the imaging device and the illumination device in the step (g).
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