CN113410293A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN113410293A
CN113410293A CN202110639755.6A CN202110639755A CN113410293A CN 113410293 A CN113410293 A CN 113410293A CN 202110639755 A CN202110639755 A CN 202110639755A CN 113410293 A CN113410293 A CN 113410293A
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metal silicide
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罗军
赵超
刘实
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Institute of Microelectronics of CAS
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Abstract

本发明涉及一种半导体器件及其制造方法。提供了一种半导体器件，包括：具有鳍的半导体衬底；与鳍相交的栅极以及位于栅极两侧的鳍内的源区和漏区；分别在源区和漏区处形成且与源区和漏区相接触的金属硅化物；其中在所述金属硅化物与源区、漏区接触的界面处存在能够降低金属硅化物与源区、漏区之间的肖特基势垒高度的杂质掺杂物。所提供的半导体器件能够降低金属硅化物与源区、漏区之间的肖特基势垒高度，进而减小接触的比电阻。

Description

半导体器件及其制造方法
本申请为分案申请，母案申请号为201710017569.2，申请日为2017-01-10，发明名称为：半导体器件及其制造方法。
技术领域
本公开涉及半导体领域，具体地，涉及一种半导体器件及其制造方法。
背景技术
随着平面型半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了立体型半导体器件如FinFET(鳍式场效应晶体管)。一般而言，FinFET包括在衬底上竖直形成的鳍以及与鳍相交的栅极。
随着FinFET的尺寸越来越小，其源漏串联寄生电阻对整个器件的性能影响越来越大。为了提高器件性能，需要进一步降低源漏串联寄生电阻。同时，因为随着FinFET的尺寸越来越小，源、漏区的接触电阻在整个源漏串联寄生电阻中占比越来越大，所以降低源、漏区的接触电阻将显著地降低源漏串联寄生电阻。因此，进一步降低接触的比电阻(ρc)将是本领域技术人员一直追求的目标。
在目前的主流FinFET工艺中，一般采用金属硅化物/硅接触来形成源、漏区的接触，例如，采用硅化钛(TiSix)与n型掺杂硅(n-Si)形成源、漏区的TiSix/n-Si接触。
为了进一步降低金属硅化物/硅接触的比电阻(ρc)，在目前的主流工艺中，本领域技术人员提高硅中的掺杂浓度以降低金属硅化物/硅接触的比电阻(ρc)，即采用各种方法(例如，原位掺杂P(Si：P)、动态表面退火(DSA)等)提高杂质激活浓度，从而降低金属硅化物/硅接触的比电阻(ρc)。而事实上，由于金属硅化物/硅接触是一种肖特基接触，因此，肖特基势垒高度也显著地影响比电阻(ρc)的大小。例如，TiSix/n-Si接触的费米能级钉扎在带隙中间，因此对电子的肖特基势垒高度较高，为0.6eV左右。因此，较高的肖特基势垒高度阻止了金属硅化物/硅接触的比电阻(ρc)的进一步降低。
因此，存在提供一种降低了金属硅化物与源、漏区之间的肖特基势垒高度的半导体器件的需要。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种降低了金属硅化物与源、漏区之间的肖特基势垒高度的半导体器件及其制造方法。
根据本公开的一方面，提供了一种半导体器件，包括：具有鳍的半导体衬底；与鳍相交的栅极以及位于栅极两侧的鳍内的源区和漏区；分别在源区和漏区处形成且与源区和漏区相接触的金属硅化物；其中在所述金属硅化物与源区、漏区接触的界面处存在能够降低金属硅化物与源区、漏区之间的肖特基势垒高度的杂质掺杂物。
进一步地，所述杂质掺杂物包括选自以下组中的至少一个：C、Ge、N、P、As、O、S、Se、Te、F、Cl。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在半导体衬底上形成鳍；形成与鳍相交的栅极；在栅极两侧的鳍内形成源区和漏区；在鳍上沉积电介质；刻蚀电介质以分别在源区和漏区上方形成接触沟槽，从而露出源区和漏区的至少部分上表面；通过接触沟槽对露出的至少部分上表面进行非晶化处理；通过接触沟槽对露出的至少部分上表面进行杂质掺杂物注入；在杂质掺杂物注入之后，在接触沟槽中沉积金属，并且执行退火以形成金属硅化物，其中杂质掺杂物能够降低金属硅化物与源区、漏区之间的肖特基势垒高度。
进一步地，在退火期间，注入的杂质掺杂物在金属硅化物与源区、漏区的界面处析出，从而降低金属硅化物与源区、漏区之间的肖特基势垒高度。
进一步地，在非晶化处理后形成的非晶硅区的深度小于等于10nm。
进一步地，在退火之后，非晶硅通过与所沉积的金属反应和/或固态相外延重新生长(SPER)而消失。
根据本公开的实施例，在金属硅化物和源区、漏区的硅之间的肖特基势垒高度由于在其接触界面处的杂质掺杂物的存在而降低，从而降低了接触的比电阻，进而减小了源漏串联寄生电阻，提高了器件性能。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出了根据现有技术的示例FinFET；
图2-10是示出了根据本公开实施例的沿图1中的A-A’方向得到的制造半导体器件的流程中多个阶段的示意截面图。
贯穿附图，相同的附图标记表示相同的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
图1中示出了现有技术的示例FinFET的透视图。如图1所示，该FinFET包括：衬底101；在衬底101上形成的鳍102；与鳍102相交的栅极103，栅极103与鳍102之间设有栅介质层；以及隔离层。在该示例中，鳍102与衬底101一体，由衬底101的一部分构成。在该FinFET中，在栅极103的控制下，可以在鳍102中具体地在鳍102的三个侧壁(图中左、右侧壁以及顶壁)中产生导电沟道，如图1中箭头所示。也即，鳍102位于栅极103之下的部分充当沟道区，源区、漏区则分别位于沟道区两侧。
根据本公开的实施例，提供了一种包括鳍的半导体器件(例如，FinFET，特别是3DFinFET)。该半导体器件可以包括：具有鳍的半导体衬底；与鳍相交的栅极以及位于栅极两侧的鳍内的源区和漏区；分别在源区和漏区处形成且与源区和漏区相接触的金属硅化物。在所述金属硅化物与源区、漏区接触的界面处存在能够降低金属硅化物与源区、漏区之间的肖特基势垒高度的杂质掺杂物。
杂质掺杂物在金属硅化物与源区、漏区的界面处析出，从而降低金属硅化物与源区、漏区之间的肖特基势垒高度。
所述杂质掺杂物包括选自以下组中的至少一个：C、Ge、N、P、As、O、S、Se、Te、F、Cl。
所述栅极包括高K栅介质和金属栅导体。
所述金属硅化物包括硅化钛。
本公开可以各种形式呈现，以下将描述其中一些示例，为方便说明，以下以硅系材料为例进行描述。
图2-10是示出了根据本公开实施例的制造半导体器件的流程中多个阶段的示意截面图。
如图2所示，提供了半导体衬底101。在该半导体衬底101上形成有鳍102。鳍102与衬底101一体，由衬底101的一部分构成。图2示出了沿鳍的纵向延伸方向(即，沿图1中的A-A’方向)得到的截面图。在衬底101上方，可以形成与鳍相交的牺牲栅叠层。牺牲栅叠层可以包括依次形成的牺牲栅介质层1006、牺牲栅导体1008和盖层1014。半导体衬底101包括例如硅晶片，牺牲栅介质层1006包括例如氧化物，牺牲栅导体1008包括例如多晶硅。在形成了牺牲栅叠层之后，可以进行离子注入(形成源/漏等)、侧墙(spacer)形成等。具体地，分别在牺牲栅叠层两侧的鳍中进行离子注入以形成源区1002和漏区1004。源区1002和漏区1004包括例如n型掺杂的硅(n-Si)。在牺牲栅叠层的侧壁上形成栅侧墙层1010。栅侧墙层1010可以包括单层或多层配置，且可以包括各种合适的电介质材料如SiO2、Si3N4、SiON中任一种或其组合。此外，可以分别在源区1002和漏区1004的外侧形成浅沟槽隔离(STI)1012以进行器件隔离。
在完成上述工艺之后，如图3所示，在鳍上方沉积电介质层1016，其覆盖整个源区1002和漏区1004。电介质层1016可以包括各种合适的电介质材料如SiO2、Si3N4、SiON中任一种或其组合。在应用替代栅工艺的情况下，如图4所示，可以对电介质层1014进行平坦化处理如化学机械抛光(CMP)。CMP可以进行到直至露出牺牲栅导体1008。
这样，随后可以应用替代栅工艺，以形成最终的栅叠层。具体地，例如可以通过选择性刻蚀去除牺牲栅导体1008且可选地去除牺牲栅介质层1006，在栅侧墙1012内侧形成栅槽。在栅槽中，例如通过淀积并回蚀工艺，可以依次形成真正的栅介质层和真正的栅导体。具体地，如图5所示，在鳍102上依次形成了栅介质层1018和栅导体1020。栅介质层1018可以包括高K栅介质如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中任一种或其组合；栅导体层1020可以包括金属栅导体如Ti、Co、Ni、Al、W或其合金或金属氮化物等。另外，栅介质层1020还可以包括一层薄的氧化物(高K栅介质形成于该氧化物上)。在栅介质层1006和栅导体1008之间，还可以形成功函数调节层(图中未示出)。
在形成栅介质层1018和栅导体1020之后，如图6所示，采用各向异性刻蚀工艺(例如，等离子体刻蚀、反应离子刻蚀等)在电介质层1016上开口，分别在源区1002和漏区1004上方形成接触沟槽1022和1024，以暴露源区1002和漏区1004的部分上表面。
在形成接触沟槽1022和1024之后，如图7所示，通过接触沟槽1022和1024，对暴露的源区1002和漏区1004的部分上表面进行非晶化处理，以在接触沟槽1022和1024下方分别形成在源区1002和漏区1004内的非晶化区。例如，非晶化处理可以如下进行。具体地，可以进行锗离子注入(即，Ge预先非晶化离子注入(PAI))，其使得源区1002和漏区1004表面浅层(≤10nm)非晶化，由此形成非晶化区。也可以进行Ge或Si预先非晶化离子注入来形成该非晶化区。在源区1002和漏区1004包括n型掺杂的硅的情况下，该非晶化区被形成为非晶硅区1026和1028。
在形成非晶硅区1026和1028之后，如图8所示，通过接触沟槽1022和1024，对所形成的非晶硅区1026和1028进行杂质掺杂物注入。杂质掺杂物包括选自以下组中的至少一个：C、Ge、N、P、As、O、S、Se、Te、F、Cl。进行杂质掺杂物注入的注入能量在0.5keV至5keV之间。所注入的杂质掺杂物进入非晶硅区1026和1028中，并且大多数杂质掺杂物被约束在非晶硅区1026和1028中。
在完成杂质掺杂物注入之后，如图9所示，在接触沟槽1022和1024内沉积金属层1030和1032，并且执行退火以在非晶硅区1026和1028形成金属硅化物，并由此形成金属硅化物与源/漏区的n型掺杂的硅的接触。所沉积的金属可以包括Ti/TiN，因此，所形成的金属硅化物可以包括硅化钛(TiSix)。在此情况下，形成了硅化钛与n型掺杂的硅(TiSix/n-Si)之间的接触。
在常规的主流工艺中，为了减小在金属硅化物与源/漏区的n型掺杂的硅之间的接触电阻，采用各种方法提高n型掺杂的硅中的掺杂浓度，比如：采用原位掺杂P(Si：P)、动态表面退火(DSA)等方法提高杂质激活浓度。然而，由于硅化钛/n型掺杂的硅接触的费米能级钉扎在带隙中间，因此对电子的肖特基势垒高度较高，为0.6eV左右。因此为了进一步减小在硅化钛与n型掺杂的硅之间的接触电阻，除了提高n型掺杂的硅中的掺杂浓度之外，还需要降低硅化钛与n型掺杂的硅之间的肖特基势垒高度。
根据本发明的原理，由于之前对非晶硅区1026和1028进行了杂质掺杂物注入，因此在形成金属硅化物期间，在退火期间，注入的杂质掺杂物在金属硅化物与源区、漏区的界面处析出，从而降低了金属硅化物与源区、漏区之间的肖特基势垒高度。具体地参见图9右侧放大图，在钛与非晶硅反应以形成硅化钛1034时，所注入的杂质掺杂物在硅化钛与n型掺杂的硅之间的界面处析出，该析出的杂质掺杂物1036将引起降低的肖特基势垒高度。因此，可以降低硅化钛与n型掺杂的硅之间的接触电阻，即降低硅化钛与n型掺杂的硅之间的接触的比电阻ρc。
此外，在退火之后，非晶硅区1026和1028的非晶硅通过与所沉积的金属反应和/或固态相外延重新生长(SPER)而消失。具体地，如上所述，在退火期间，非晶硅与钛反应以形成硅化钛，同时，至少部分非晶硅重新生长为晶体硅。因此，在退火之后，非晶硅区1026和1028的非晶硅通过与钛反应和/或重新生长而消失。
在形成具有降低的肖特基势垒高度的金属硅化物与源/漏区之间的接触之后，如图10所示，该方法还可以包括在接触沟槽中形成接触插塞。例如，可以在接触沟槽1022和1024内沉积钨(W)以在所沉积的金属层(例如，Ti/TiN)1030和1032上分别形成钨(W)层1038和1040；进行CMP以使钨层1038和1040的上表面平坦化。所述钨层可以用作接触插塞。
由此，得到了根据本公开实施例的半导体器件。如图10所示，该半导体器件可以包括：具有鳍的半导体衬底101，在鳍102上形成的栅介质1018和栅导体1020(其构成栅叠层)，在栅叠层的左右两侧的侧壁上形成的栅侧墙1010，以及在栅叠层两侧的鳍内形成的源区1002和漏区1004。在鳍102上方形成有电介质材料1016。电介质材料1016覆盖源区1002和漏区1004，并在其中形成接触沟槽以暴露源区1002和漏区1004的至少部分上表面。在接触沟槽中依次形成有金属层(例如，Ti/TiN)1030和1032以及钨层1038和1040。金属层(例如，Ti/TiN)1030和1032分别在源区1002和漏区1004处形成金属硅化物1034，金属硅化物1034与源区1002、漏区1004的界面处存在析出的杂质掺杂物1036。析出的杂质掺杂物1036显著地降低了金属硅化物1034与源区1002、漏区1004的n型掺杂的硅之间的肖特基势垒高度，从而有效地减小了接触的比电阻ρc。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (17)

1.一种半导体器件，其中，包括：
具有鳍的半导体衬底；
与鳍相交的栅极以及位于栅极两侧的鳍内的源区和漏区，所述源区和漏区包括n型掺杂的硅；
分别在源区和漏区的至少部分上表面形成且与源区和漏区相接触的金属硅化物；
其中，在源漏区域形成接触金属硅化物之前进行非晶化处理，以形成在源区和漏区内的非晶化区，所述金属硅化物是通过在非晶化区进行杂质掺杂物注入后沉积金属并退火之后形成的，其中所述杂质掺杂物存在于所述金属硅化物与源区、漏区接触的界面处，能够降低金属硅化物与源区、漏区之间的肖特基势垒高度；进行杂质掺杂物注入的注入能量在0.5keV至5keV之间。
2.根据权利要求1所述的半导体器件，其中，所述杂质掺杂物包括选自以下组中的至少一个：C、Ge、N、P、As、O、S、Se、Te、F、Cl。
3.根据权利要求1所述的半导体器件，其中，所述栅极包括高K栅介质和金属栅导体。
4.根据权利要求1所述的半导体器件，其中，所述金属硅化物包括硅化钛。
5.一种制造半导体器件的方法，其中，包括：
在半导体衬底上形成鳍；
形成与鳍相交的栅极；
在栅极两侧的鳍内形成源区和漏区，所述源区和漏区包括n型掺杂的硅；
在鳍上沉积电介质；
刻蚀电介质以分别在源区和漏区上方形成接触沟槽，从而露出源区和漏区的至少部分上表面；
通过接触沟槽对露出的至少部分上表面进行非晶化处理；
通过接触沟槽对露出的至少部分上表面进行杂质掺杂物注入；
在杂质掺杂物注入之后，在接触沟槽中沉积金属，并且执行退火以形成金属硅化物；
其中杂质掺杂物能够降低金属硅化物与源区、漏区之间的肖特基势垒高度；进行杂质掺杂物注入的注入能量在0.5keV至5keV之间。
6.根据权利要求5所述的方法，其中，在退火期间，注入的杂质掺杂物在金属硅化物与源区、漏区的界面处析出，从而降低金属硅化物与源区、漏区之间的肖特基势垒高度。
7.根据权利要求5所述的方法，其中，所述析出的杂质掺杂物选自以下组中的任何一个：C、Ge、N、P、As、O、S、Se、Te、F、Cl。
8.根据权利要求5所述的方法，其中，所述栅极包括高K栅介质和金属栅导体。
9.根据权利要求5所述的方法，其中，所沉积的金属包括Ti/TiN，所述金属硅化物包括硅化钛。
10.根据权利要求5所述的方法，其中，所述退火包括快速热退火、激光退火和/或动态表面退火。
11.根据权利要求5所述的方法，其中，所述非晶化处理包括：进行锗注入。
12.根据权利要求9所述的方法，其中，还包括：
在接触沟槽内沉积钨以在Ti/TiN上形成钨层；
进行化学机械抛光以使钨层的上表面平坦化。
13.根据权利要求5所述的方法，其中，在非晶化处理后形成的非晶硅区的深度小于等于10nm。
14.根据权利要求13所述的方法，其中，将所述杂质掺杂物注入到非晶硅区中。
15.根据权利要求14所述的方法，其中，注入的大多数杂质掺杂物被约束在非晶硅区中。
16.根据权利要求13所述的方法，其中，还包括：在退火期间，至少一部分非晶硅重新生长为晶体硅。
17.根据权利要求13所述的方法，其中，还包括：在退火之后，非晶硅通过与所沉积的金属反应和/或固态相外延重新生长而消失。
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