CN113394160B - Method for manufacturing semiconductor device - Google Patents
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- CN113394160B CN113394160B CN202110526799.8A CN202110526799A CN113394160B CN 113394160 B CN113394160 B CN 113394160B CN 202110526799 A CN202110526799 A CN 202110526799A CN 113394160 B CN113394160 B CN 113394160B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: providing a silicon substrate layer; forming a mask layer; selectively etching the mask layer to expose the silicon substrate layer at the position of the gate region from the first window; etching the silicon substrate layer based on the first window to enable the silicon substrate layer to form a groove structure at the position of the first window; back etching the mask layer at the edge position of the first window to form a step structure on the silicon substrate layer at the edge position of the groove; growing a silicon epitaxial layer by an epitaxial growth process according to the surface appearance of the substrate layer exposed in the second window after back etching, wherein the silicon epitaxial layer comprises a protrusion formed on the substrate layer at the position of the step structure; and oxidizing the silicon epitaxial layer in the second window through a rapid thermal annealing process, so that the oxidation reaction at the protruding position blocks oxygen from transversely permeating out of the second window to form a flat HVOX layer.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
In manufacturing a gate of a MOS device, usually, HVOX (High Voltage Oxide) is used as a gate Oxide layer, which affects current driving capability, switching performance and power characteristics of the MOS device, and a threshold Voltage of the device.
In the related art, a rapid oxidation thermal anneal is typically performed using an ISSG (In-situ Steam Generation) process, which causes oxidation of the exposed silicon In the first window, resulting In a thicker HVOX layer.
However, in the oxidation process, since the diffusion of oxygen in silicon dioxide is an isotropic process, oxygen also diffuses laterally and penetrates into the silicon not exposed at the edge of the first window, so that the silicon not exposed at the edge of the first window is oxidized to form silicon dioxide, forming a bird's beak-like defect, commonly referred to as a bird's beak. Referring to fig. 1, which shows an electron microscope structure diagram of a bird's beak shaped gate oxide layer, it can be seen from fig. 1 that due to the silicon layer number consumed by the bird's beak shaped oxide layer, the gate layer at this position will be raised, and the raised gate layer is prone to wire breakage during the subsequent planarization process, thereby causing device failure.
Disclosure of Invention
The application provides a manufacturing method of a semiconductor device, which can solve the bird's beak effect in the related art.
The application provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a silicon base layer, wherein the silicon base layer comprises a gate region for forming a gate electrode;
forming a mask layer on the upper surface of the silicon substrate layer;
selectively etching the mask layer to expose the silicon substrate layer at the position of the gate region from the first window;
etching the silicon substrate layer based on the first window, so that the silicon substrate layer forms a groove structure at the position of the first window;
back etching the mask layer at the edge position of the first window to enable the first window to expand towards the periphery to form a second window, and enabling the silicon substrate layer at the position between the edge of the first window and the edge of the second window to be exposed, so that a step structure is formed on the silicon substrate layer at the edge position of the groove;
growing a silicon epitaxial layer by an epitaxial growth process according to the surface appearance of the substrate layer exposed in the second window after back etching, wherein the silicon epitaxial layer comprises a protrusion formed on the substrate layer at the position of the step structure;
and oxidizing the silicon epitaxial layer in the second window through a rapid thermal annealing process, so that the oxidation reaction at the protruding position blocks oxygen from transversely permeating out of the second window to form a flat HVOX layer.
Optionally, in the step of providing a silicon base layer, the silicon base layer includes opposite upper and lower surfaces;
and a shallow trench isolation structure is formed in the silicon substrate layer, is positioned on at least one side of the gate region and extends downwards from the upper surface of the silicon substrate layer.
Optionally, in the step of selectively etching the mask layer to form the first window at the gate region, the upper surface of the silicon substrate layer at the gate region and the edge portion of the shallow trench isolation structure near the gate region are exposed in the first window.
Optionally, the step of etching the silicon base layer based on the first window so that the silicon base layer forms a groove structure at the position of the first window includes:
etching the edge part of the shallow trench isolation structure exposed in the first window to form a first groove on the edge part of the shallow trench isolation structure;
and etching the silicon substrate layer exposed in the first window at the position of the gate region to form a second groove in the silicon substrate layer at the position of the gate region.
Optionally, the mask layer is made of silicon nitride.
Optionally, the mask layer has a thickness of 700 to 1200 angstroms.
Optionally, the mask layer at the edge of the first window is etched back, so that the first window extends to the periphery to form a second window, and the silicon substrate layer at a position between the edge of the first window and the edge of the second window is exposed, so that in the step of forming the step structure on the silicon substrate layer at the edge of the groove, the second window is etched back by 100 to 500 angstroms on the basis of the first window.
The technical scheme at least comprises the following advantages: according to the method, the mask layer at the edge position of the first window is etched back, so that the first window is expanded to the periphery to form the second window, the silicon substrate layer at the edge position of the groove forms a step structure, the epitaxial layer grown through the epitaxial process forms a protrusion at the edge position of the groove, the protrusion can prevent oxygen in the subsequent epitaxial layer in the oxidation process from permeating outside the groove, and the formed HVOX layer is prevented from having a bird's beak structure.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a view showing an electron microscope structure of a bird's beak-shaped gate oxide layer;
fig. 2 is a flow chart illustrating a method for fabricating a semiconductor device according to an embodiment of the present application;
FIG. 2a is a schematic cross-sectional structural diagram of the device after step S1 is completed according to an embodiment;
FIG. 2b is a schematic cross-sectional structural diagram of the device after step S2 is completed according to an embodiment;
FIG. 2c is a schematic cross-sectional structural diagram of the device after step S3 is completed according to an embodiment;
FIG. 2d is a schematic cross-sectional structural diagram of the device after step S41 is completed according to an embodiment;
FIG. 2e is a schematic cross-sectional diagram of the device after step S42 is completed according to an embodiment;
FIG. 2f is a schematic cross-sectional structural diagram of the device after step S5 is completed according to an embodiment;
FIG. 2g shows an enlarged schematic view of section A of FIG. 2 f;
FIG. 2h is a schematic cross-sectional structural diagram of the device after step S6 is completed according to an embodiment;
fig. 2i shows a schematic cross-sectional structural diagram of the device after step S7 is completed according to an embodiment.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 2 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present application, and referring to fig. 2, the method includes the following steps:
step S1: a silicon substrate layer is provided that includes a gate region for forming a gate.
Referring to fig. 2a, which shows a schematic cross-sectional structure of the device after step S1 is completed, as can be seen from fig. 2a, the silicon substrate layer 210 includes a gate region 211, the gate region 211 is used for forming a gate structure of the device, and the silicon substrate layer 210 is provided with a shallow trench isolation structure 220 formed therein. The shallow trench isolation structure 220, which is located at one side of the gate region 211 of the silicon substrate layer 210, includes a shallow trench extending downward from the upper surface of the silicon substrate layer 210 and a dielectric layer filled in the shallow trench, so that the shallow trench isolation structure 220 extends downward from the upper surface of the silicon substrate layer. As can be seen in fig. 2a, the surface of the silicon base layer is oxidized to form a silicon oxide layer 230.
Step S2: a mask layer is formed on an upper surface of the silicon substrate layer.
Referring to fig. 2b, which shows a schematic cross-sectional structure of the device after step S2 is completed, in this embodiment, a mask layer 240 is formed on the upper surface of the silicon substrate layer 210, and the mask layer 240 covers at least the shallow trench isolation structure 220 and the silicon oxide layer 230 shown in fig. 2 b.
Alternatively, the material of the mask layer 240 may be silicon nitride, and the thickness may be 700 a to 1200 a.
And step S3: the mask layer is selectively etched such that the base layer is exposed from the first window at the location of the gate region.
Referring to fig. 2c, which shows a schematic cross-sectional structure of the device after step S3 is completed, in this embodiment, a first window 251 is formed by etching the mask layer 240 shown in fig. 2b, so that the remaining mask layer 240 is exposed from the first window 251, and the silicon substrate layer 210 at the position of the gate region 211 is also exposed from the first window 251 at the edge portion 221 of the shallow trench isolation structure near the gate region 211.
And step S4: and etching the silicon substrate layer based on the first window, so that the silicon substrate layer forms a groove structure at the position of the first window.
In this embodiment, the step S4 may include a step S41 and a step S42 performed in sequence:
step S41: the shallow trench isolation structure edge portion 221 exposed in the first window 251 shown in fig. 2c is etched, so that a first groove 261 shown in fig. 2d is formed in the shallow trench isolation structure edge portion 221.
Fig. 2d is a schematic cross-sectional structure diagram of the device after step S41 is completed according to an embodiment, and as can be seen from fig. 2d, the first groove 261 extends downward from the upper surface of the shallow trench isolation structure 220.
Step S42: the silicon substrate layer 210 exposed in the first window 251 in fig. 2c at the location of the gate region 211 is etched, so that a second groove 262 in fig. 2e is formed in the silicon substrate layer 210 at the location of the gate region 211.
Fig. 2e is a schematic cross-sectional structure diagram of the device after step S42 is completed according to an embodiment, and it can be seen from fig. 2e that the second groove 262 extends downward from the upper surface of the silicon substrate layer 210 at the location of the gate region 211.
With continued reference to fig. 2e, it can be seen that the silicon substrate layer 210 where the remaining mask layer 240 overlies is not etched, thereby forming a recess structure 260 comprising a first recess 261 and a second recess 262.
Step S5: and carrying out back etching on the mask layer at the edge position of the first window to enable the first window to expand towards the periphery to form a second window, and enabling the substrate layer at the position between the edge of the first window and the edge of the second window to be exposed, so that a step structure is formed on the silicon substrate layer at the edge position of the groove.
Referring to fig. 2f and fig. 2g, fig. 2f shows a schematic cross-sectional structural diagram of the device after step S5 is completed according to an embodiment, and fig. 2g shows an enlarged structural diagram of a portion a in fig. 2 f. As can be seen from fig. 2f and 2g, the second window 252 formed after etching back the mask layer 230 is expanded outward on the basis of the first window 251, and the expanded width d may be 100 a to 500 a, which is the width of the etch back in step S5. The etch back exposes the silicon substrate layer at a location between the edge of the first window 251 and the edge of the second window 252 such that the silicon substrate layer 270 at the location of the edge of the recess 260 forms a step structure 270. The lower surface of the step structure 270 is the bottom surface of the groove 260, and the upper surface of the step structure 270 is the upper surface of the silicon base layer 210 at a position between the edge of the first window 251 and the edge of the second window 252.
Step S6: and growing a silicon epitaxial layer by an epitaxial growth process according to the surface appearance of the substrate layer exposed in the second window after the back etching, wherein the silicon epitaxial layer comprises a protrusion formed on the substrate layer at the position of the step structure.
Referring to fig. 2h, which shows a schematic cross-sectional structure of the device after step S6 is completed, after the epitaxial process is completed, a silicon epitaxial layer 280 is formed on the upper surface of the silicon substrate layer 210 exposed to the second window 252, and the silicon epitaxial layer 280 forms a protrusion at the position of the step structure 270 shown in fig. 2g according to the topography of the upper surface of the silicon substrate layer 210 at the position of the second window 252.
Step S7: and oxidizing the silicon epitaxial layer in the second window through a rapid thermal annealing process, so that the oxidation reaction at the protruding position blocks oxygen from transversely permeating out of the second window to form a flat HVOX layer.
Referring to fig. 2i, a schematic cross-sectional structural diagram of the device after step S7 is completed is shown. An ISSG (In-situ Steam Generation) process may be used to perform a rapid oxidation thermal anneal such that the silicon epitaxial layer 280 shown In fig. 2h is oxidized to form the HVOX layer 290. When the protrusion 281 of the silicon epitaxial layer 280 shown in fig. 2h is oxidized, since it is thicker than other portions of the silicon epitaxial layer 280, the rich silicon can react with oxygen, so as to block oxygen from laterally penetrating through the lower portion of the mask layer 240 outside the second window 252, thereby avoiding the formation of the bird's beak structure as described in the background art.
To sum up, this application makes first window expand to form the second window all around through carrying out back the sculpture to the mask layer of first window border department, and the silicon substrate layer formation stair structure of recess border department makes the epitaxial layer through epitaxial technology growth form the arch in recess border department, and this arch can block follow-up epitaxial layer and permeate to the recess outward by the oxygen in oxidation process, thereby avoids the HVOX layer that forms to have the bird's beak structure.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. A manufacturing method of a semiconductor device is characterized by comprising the following steps:
providing a silicon base layer, wherein the silicon base layer comprises a gate region for forming a gate electrode;
forming a mask layer on the upper surface of the silicon substrate layer;
selectively etching the mask layer to expose the silicon substrate layer at the position of the gate region from the first window;
etching the silicon substrate layer based on the first window, so that the silicon substrate layer forms a groove structure at the position of the first window;
back etching the mask layer at the edge position of the first window to enable the first window to expand towards the periphery to form a second window, and enabling the silicon substrate layer at the position between the edge of the first window and the edge of the second window to be exposed, so that a step structure is formed on the silicon substrate layer at the edge position of the groove structure;
growing a silicon epitaxial layer by an epitaxial growth process according to the surface appearance of the substrate layer exposed in the second window after back etching, wherein the silicon epitaxial layer comprises a protrusion formed on the substrate layer at the position of the step structure;
and oxidizing the silicon epitaxial layer in the second window through a rapid thermal annealing process, so that the oxidation reaction at the protruding position blocks oxygen from transversely permeating out of the second window to form a flat HVOX layer.
2. The method of fabricating a semiconductor device according to claim 1, wherein in the step of providing a silicon base layer, the silicon base layer includes opposing upper and lower surfaces;
and a shallow trench isolation structure is formed in the silicon substrate layer, is positioned on at least one side of the gate region and extends downwards from the upper surface of the silicon substrate layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein in the step of selectively etching the mask layer so as to form the first window at the gate region, the upper surface of the silicon substrate layer at the gate region and the edge portion of the shallow trench isolation structure near the gate region are exposed in the first window.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the step of etching the silicon base layer based on the first window so that the silicon base layer forms a groove structure at the position of the first window comprises:
etching the edge part of the shallow trench isolation structure exposed in the first window to form a first groove on the edge part of the shallow trench isolation structure;
and etching the silicon substrate layer exposed in the first window at the position of the gate region, so that a second groove is formed in the silicon substrate layer at the position of the gate region.
5. The method of manufacturing a semiconductor device according to claim 1, wherein the mask layer is made of silicon nitride.
6. The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the mask layer has a thickness of 700 to 1200 angstroms.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the step of etching back the mask layer at the edge of the first window to expand the first window to form a second window, and exposing the silicon substrate layer at a position between the edge of the first window and the edge of the second window, so that the silicon substrate layer at the edge of the groove structure forms a step structure, and the second window is etched back by 100 to 500 angstroms on the basis of the first window.
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| CN111192850A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method for manufacturing isolation structure |
| CN112420721A (en) * | 2020-11-25 | 2021-02-26 | 华虹半导体(无锡)有限公司 | Control gate etching method of eflash device |
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| JPS588139B2 (en) * | 1979-05-31 | 1983-02-14 | 富士通株式会社 | Manufacturing method of semiconductor device |
| JP2001230315A (en) * | 2000-02-17 | 2001-08-24 | Mitsubishi Electric Corp | Semiconductor device and its fabricating method |
| CN104916532B (en) * | 2014-03-10 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of grid oxic horizon |
| CN110718479B (en) * | 2019-09-30 | 2022-10-18 | 上海华力集成电路制造有限公司 | Method for improving beak defect of asymmetric end of high-threshold-voltage device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111192850A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method for manufacturing isolation structure |
| CN112420721A (en) * | 2020-11-25 | 2021-02-26 | 华虹半导体(无锡)有限公司 | Control gate etching method of eflash device |
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