CN113380722A - 半导体封装件和制造半导体封装件的方法 - Google Patents

半导体封装件和制造半导体封装件的方法 Download PDF

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CN113380722A
CN113380722A CN202110090433.0A CN202110090433A CN113380722A CN 113380722 A CN113380722 A CN 113380722A CN 202110090433 A CN202110090433 A CN 202110090433A CN 113380722 A CN113380722 A CN 113380722A
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molding member
semiconductor chip
core substrate
redistribution
semiconductor
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朱昶垠
崔圭振
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体封装件包括：具有通孔的芯衬底；至少部分地填充所述通孔并且覆盖所述芯衬底的上表面的第一模制构件，所述第一模制构件在所述通孔内具有腔；位于在所述芯衬底的所述上表面上的所述第一模制构件上的第一半导体芯片；布置在所述腔内的第二半导体芯片；位于所述第一模制构件上并且覆盖所述第一半导体芯片的第二模制构件；填充所述腔并覆盖所述芯衬底的所述下表面的第三模制构件；位于所述第二模制构件上并且将所述第一半导体芯片的第一芯片焊盘与所述芯衬底的芯连接布线电连接的第一再分布布线；以及位于所述第三模制构件上并且将所述第二半导体芯片的第二芯片焊盘与所述芯衬底的所述芯连接布线电连接的第二再分布布线。

Description

半导体封装件和制造半导体封装件的方法
相关申请的交叉引用
通过引用的方式将于2020年2月25日在韩国知识产权局提交的题为“Semiconductor Package and Method of Manufacturing the Semiconductor Package”(半导体封装件和制造半导体封装件的方法)的韩国专利申请No.10-2020-0022838的全部内容合并于此。
技术领域
实施例涉及半导体封装件和制造半导体封装件的方法。
背景技术
在扇出封装件中，电连接端子可以布置在布置有半导体芯片的区域之外的扇出区域中。在扇出封装件的情况下，实现包括堆叠在其中的不同半导体芯片的堆叠封装件可能是困难且昂贵的。
发明内容
实施例涉及一种半导体封装件，其包括：芯衬底，所述芯衬底具有通孔；第一模制构件，所述第一模制构件至少部分地填充所述通孔并且覆盖所述芯衬底的上表面，所述第一模制构件具有设置在所述通孔内以从所述芯衬底的下表面沿厚度方向延伸的腔；第一半导体芯片，所述第一半导体芯片布置在位于所述芯衬底的所述上表面上的所述第一模制构件上；第二半导体芯片，所述第二半导体芯片布置在所述第一模制构件的所述腔内；第二模制构件，所述第二模制构件位于所述第一模制构件上并且覆盖所述第一半导体芯片；第三模制构件，所述第三模制构件填充所述腔并且覆盖所述芯衬底的所述下表面；第一再分布布线，所述第一再分布布线位于所述第二模制构件上，并且将所述第一半导体芯片的第一芯片焊盘与所述芯衬底的芯连接布线电连接；第二再分布布线，所述第二再分布布线位于所述第三模制构件上，并且将所述第二半导体芯片的第二芯片焊盘与所述芯衬底的所述芯连接布线电连接；以及下再分布布线层，所述下再分布布线层位于所述第三模制构件上，并且具有分别电连接到所述第二再分布布线的下再分布布线。所述第一模制构件、所述第二模制构件和所述第三模制构件中的至少一者可以包括光可成像电介质材料。
实施例还涉及一种半导体封装件，其包括：芯衬底，所述芯衬底具有彼此相对的第一表面和第二表面，并具有从所述第一表面延伸到所述第二表面的通孔；第一模制构件，所述第一模制构件具有覆盖所述芯衬底的所述第一表面的第一部分和覆盖所述通孔的内侧壁的第二部分，所述第二部分具有设置在所述通孔内以从所述芯衬底的所述第二表面暴露的腔；第一半导体芯片，所述第一半导体芯片布置在位于所述芯衬底的所述第一表面上的所述第一模制构件上；第二半导体芯片，所述第二半导体芯片布置在所述第一模制构件的所述腔内；第二模制构件，所述第二模制构件位于在所述芯衬底的所述第一表面上的所述第一模制构件上并且覆盖所述第一半导体芯片；第三模制构件，所述第三模制构件位于所述芯衬底的所述第二表面上，填充所述第一模制构件的所述腔，并且覆盖所述第二半导体芯片；第一再分布布线，所述第一再分布布线位于所述第二模制构件上并且将所述第一半导体芯片的第一芯片焊盘与所述芯衬底的芯连接布线电连接；第二再分布布线，所述第二再分布布线位于所述第三模制构件上，并且将所述第二半导体芯片的第二芯片焊盘与所述芯衬底的所述芯连接布线电连接；以及下再分布布线层，所述下再分布布线层位于所述第三模制构件上并且具有分别电连接到所述第二再分布布线的下再分布布线。
实施例还涉及一种半导体封装件，其包括：芯衬底，所述芯衬底具有通孔；第一模制构件，所述第一模制构件至少部分地填充所述通孔并且覆盖所述芯衬底的上表面，所述第一模制构件具有设置在所述通孔内以从所述芯衬底的下表面沿厚度方向延伸的腔；第一半导体芯片，所述第一半导体芯片布置在位于所述芯衬底的所述上表面上的所述第一模制构件上；第二半导体芯片，所述第二半导体芯片布置在所述第一模制构件的所述腔内；第二模制构件，所述第二模制构件位于所述第一模制构件上并覆盖所述第一半导体芯片；第三模制构件，所述第三模制构件填充所述腔并且覆盖所述芯衬底的所述下表面；第一再分布布线，所述第一再分布布线位于所述第二模制构件上并且将所述第一半导体芯片的第一芯片焊盘与所述芯衬底的芯连接布线电连接；以及第二再分布布线，所述第二再分布布线位于所述第三模制构件上，并且将所述第二半导体芯片的第二芯片焊盘与所述芯衬底的所述芯连接布线电连接。
附图说明
通过参考附图详细描述示例实施例，特征对于本领域技术人员将变得显而易见，在附图中：
图1是示出根据示例实施例的半导体封装件的截面图。
图2和图4至图18是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图，并且图3是图2的截面平面图。
图19是示出根据示例实施例的半导体封装件的截面图。
图20至图26是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。
图27是示出根据示例实施例的半导体封装件的截面图。
图28和图29是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。
图30是示出根据示例实施例的半导体封装件的截面图。
图31和图32是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。
图33是示出根据示例实施例的半导体封装件的截面图。
图34和图35是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。
具体实施方式
图1是示出根据示例实施例的半导体封装件的截面图。
参照图1，半导体封装件10可以包括：芯衬底(core substrate)100，第一至第三模制构件120、130、140，第一半导体芯片200和第二半导体芯片210，第一再分布布线170和第二再分布布线180，下再分布布线层300，以及外部连接构件。
在示例实施例中，半导体封装件10可以包括被设置为基础衬底的其上堆叠有第一半导体芯片200和第二半导体芯片210的芯衬底100。芯衬底100可以包括设置在第一半导体芯片200或第二半导体芯片210所在的区域外部的扇出区域中的芯连接布线112，以用作与第一半导体芯片和第二半导体芯片的电连接路径。因此，半导体封装件10可以被设置为扇出封装件。另外，半导体封装件10可以被设置为包括经由芯衬底100堆叠的第一半导体芯片200和第二半导体芯片210的堆叠封装件。
此外，半导体封装件10可以被设置为系统级封装件(SIP)。例如，第二半导体芯片210可以是包括逻辑电路的逻辑芯片，并且第一半导体芯片200可以是存储器芯片。逻辑芯片可以是用于控制存储器芯片的控制器。存储器芯片可以包括诸如DRAM、SRAM、闪存、PRAM、ReRAM、FeRAM、MRAM等的各种存储电路。
在示例实施例中，芯衬底100可以具有彼此相对的第一表面(上表面)102和第二表面(下表面)104。芯衬底100可以在其中间区域中具有通孔106。通孔106可以从芯衬底100的第一表面102延伸到第二表面104。通孔106可以完全穿透芯衬底100。
芯衬底100可以包括多个堆叠的绝缘层110a、110b和设置在绝缘层中的芯连接布线112。可以在设置有半导体芯片(裸片)的区域外部的扇出区域中设置多个芯连接布线112，以用于与半导体芯片电连接。
例如，芯衬底100可以包括第一绝缘层110a和堆叠在第一绝缘层110a上的第二绝缘层110b。芯连接布线112可以包括第一金属布线112a、第一接触112b、第二金属布线112c、第二接触112d和第三金属布线112e。第一金属布线112a可以设置在芯衬底100的第二表面104(即，第一绝缘层110a的下表面)中，并且第一金属布线112a的至少一部分可以从第二表面104暴露。第三金属布线112e可以设置在芯衬底100的第一表面102(即，第二绝缘层110b的上表面)中，并且第三金属布线112e的至少一部分可以从第一表面102暴露。可以理解的是，芯衬底100的绝缘层和芯连接布线的数目和布置可以改变。
第一模制构件120可以覆盖芯衬底100的第一表面102，并且可以例如部分地填充通孔106。第一模制构件120可以具有在厚度方向(图1中的垂直方向)上从芯衬底100的第二表面104朝向第二模制构件130延伸的腔126。例如，第一模制构件120可以设置在芯衬底100的通孔106中，使得第一模制构件在厚度方向上从芯衬底100的第二表面104延伸到芯衬底100的第一表面102或其上方。
第一模制构件120可以包括覆盖芯衬底100的第一表面102的第一部分和覆盖芯衬底100的通孔106的内侧壁的第二部分。第一模制构件120的第二部分可以具有设置在通孔106内并且延伸到芯衬底100的第二表面104的腔126。
第一模制构件120的上表面可以位于比芯衬底100的第一表面102高的平面上，并且第一模制构件120的下表面可以与芯衬底100的第二表面104共面。
腔126可以在厚度方向上从第一模制构件120的下表面(即，芯衬底100的第二表面104)延伸到预定深度。例如，腔126可以被设置成例如完全地穿透第一模制构件120。
第一模制构件120可以包括例如绝缘材料，诸如环氧树脂。第一模制构件120可以包括例如光可成像电介质(PID)材料。
第一半导体芯片200可以布置在位于芯衬底100的第一表面102上的第一模制构件120上。第一半导体芯片200可以包括位于第一表面202(即，其有源表面)上的第一芯片焊盘206。第一半导体芯片200可以被布置为使得背面(即，与其上形成有第一芯片焊盘206的第一表面202相对的第二表面204)面向第一模制构件120。第一半导体芯片200可以是通过粘附膜(未示出)粘合在第一模制构件120上。
第一半导体芯片200可以对应于芯衬底100的通孔106和第一模制构件120的腔126布置。第一半导体芯片200的面积可以大于第一模制构件120的腔126的面积。因此，第一半导体芯片200的第二表面204的中间区域可以通过腔126暴露。
第二半导体芯片210可以布置在第一模制构件120的腔126内。第二半导体芯片210可以对应于第一半导体芯片200布置。第二半导体芯片210可以布置成与腔126的内侧壁间隔开。
第二半导体芯片210可以在第一表面212(即，其有源表面)上包括第二芯片焊盘216。第二半导体芯片210可以布置在腔126内，使得其上形成有第二芯片焊盘216的第一表面212面向下或面向下再分布布线层300。第二芯片焊盘216可以从芯衬底100的第二表面104暴露。第二半导体芯片210的第一表面212可以与芯衬底100的第二表面104共面。
第一半导体芯片200的第二表面204(即，背面)和第二半导体芯片210的第二表面214(即，背面)可以彼此面对。粘附膜220可以布置在第一半导体芯片200的第二表面204与第二半导体芯片210的第二表面214之间。粘附膜220可以包括例如裸片附接膜(DAF)。
第二模制构件130可以设置在位于芯衬底100的第一表面102上的第一模制构件120上以覆盖第一半导体芯片200。因此，第一半导体芯片200的第一表面202可以被第二模制构件130覆盖。
第二模制构件130可以包括例如绝缘材料，诸如环氧树脂。第二模制构件130可以包括例如光可成像电介质(PID)材料。第二模制构件130可以包括与第一模制构件120相同或不同的材料。
第三模制构件140可以覆盖芯衬底100的第二表面104并填充腔126。第三模制构件140可以设置为填充第二半导体芯片210的侧壁与腔126的内侧壁之间的空间。第三模制构件140可以包括覆盖芯衬底100的第二表面104的第三部分、覆盖第一模制构件120的腔126的内侧壁的第四部分以及覆盖第二半导体芯片210的第一表面212的第五部分。
第三模制构件140可以包括例如绝缘材料，诸如环氧树脂。第三模制构件140可以包括例如光可成像电介质(PID)材料。第三模制构件140可以包括与第一模制构件120和第二模制构件130相同或不同的材料。
第一再分布布线170可以布置在第二模制构件130上，并且可以通过形成在第二模制构件130中的开口电连接到第一半导体芯片200的第一芯片焊盘206和芯衬底100的芯连接布线112。第一再分布布线170可以设置在芯衬底100的第一表面102上，以用作背面再分布布线。
一些第一再分布布线170可以仅电连接到芯连接布线112。第一再分布布线可以包括例如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、铂(Pt)或其合金。
第二再分布布线180可以布置在第三模制构件140上，并且可以通过形成在第三模制构件140中的开口电连接到第二半导体芯片210的第二芯片焊盘216和芯衬底100的芯连接布线112。第二再分布布线180可以设置在芯衬底100的第二表面104上，以用作正面再分布布线。
一些第二再分布布线180可以仅电连接到芯连接布线112或第二芯片焊盘216。第二再分布布线可以包括例如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、铂(Pt)或其合金。
在示例实施例中，下再分布布线层300可以设置在第三模制构件140上以覆盖第二半导体芯片210的第一表面212和芯衬底100的第二表面104。下再分布布线层300可以具有分别电连接到第二再分布布线180的下再分布布线312。
在示例实施例中，下再分布布线层300可以包括第一下绝缘层310a和第一下再分布布线312a，第一下绝缘层310a设置在第三模制构件140上并且具有暴露第二再分布布线180的开口，第一下再分布布线312a设置在第一下绝缘层310a上并且其至少一部分通过开口与第二再分布布线180接触。
下再分布布线层300可以包括设置在第一下绝缘层310a上并且具有暴露第一下再分布布线312a的开口的第二下绝缘层310b。下再分布布线层300可以包括设置在第二下绝缘层310b上并且其至少一部分通过开口与第一下再分布布线312a接触的第二下再分布布线312b。
下再分布布线层300可以包括位于第二下部绝缘层310b上并且暴露第二下再分布布线312b的至少一部分的保护层320。在示例实施例中，第二下再分布布线312b的该部分可以用作定位(landing)焊盘，即，封装焊盘。
可以理解，下再分布布线层的下绝缘层的数目、尺寸、布置等被示为示例并且可以改变。
外部连接构件400可以在下再分布布线层300的外表面上设置在封装焊盘上。例如，外部连接构件400可以包括焊料球。焊料球的直径可以为例如300μm至500μm。
下再分布布线层300的一些下再分布布线312和一些第二再分布布线180可以用作第二半导体芯片210的第一输入/输出信号线。下再分布布线层300的一些下再分布布线312、一些第二再分布布线180、一些芯连接布线112和一些第一再分布布线170可以用作第一半导体芯片200的第二输入/输出信号线。一些第二再分布布线180、一些芯连接布线112和一些第一再分布布线170可以用作第一半导体芯片200与第二半导体芯片210之间的电连接线。
如上所述，半导体封装件10可以是扇出面板级封装件，并且可以包括设置在第二半导体芯片210的外部区域中的芯衬底100和覆盖芯衬底100的第二表面104的下再分布布线层300。作为堆叠封装件的半导体封装件10可以包括堆叠在其中的第一半导体芯片200和第二半导体芯片210。
因此，半导体封装件10可以被设置为经由作为扇出面板级封装件的支撑框架的芯衬底100堆叠的第一半导体芯片200和第二半导体芯片210的堆叠封装件，从而实现高带宽和高密度。第一半导体芯片200和第二半导体芯片210可以通过位于芯衬底100的正面上的第一再分布布线170和位于芯衬底100的背面上的第二再分布布线180彼此电连接，使得信号传输长度缩短，从而优化了信号完整性(SI)。
在下文中，将描述制造图1中的半导体封装件的方法。
图2和图4至图18是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。图3是沿图2中的线A-A'截取的截面平面图。
参照图2至图4，可以将具有通孔106的芯衬底100粘合在阻挡带20上。
在示例实施例中，芯衬底100可以用作其上布置有多个半导体芯片的用于电连接的支撑框架，以制造具有扇出面板级封装构造的半导体封装件。
芯衬底100可以具有彼此相对的第一表面102和第二表面104。芯衬底100可以包括多个堆叠的绝缘层110a、110b和设置在绝缘层中的芯连接布线112。多个芯连接布线112可以设置为从芯衬底100的第一表面102穿透芯衬底100到第二表面104，以用作电连接路径。芯连接布线112可以设置在其中设置有半导体芯片(裸片)的区域之外的扇出区域中，以用于与安装在其中的半导体芯片电连接。
芯衬底100可以包括例如第一绝缘层110a和堆叠在第一绝缘层110a上的第二绝缘层110b。芯连接布线112可以包括第一金属布线112a、第一接触112b、第二金属布线112c、第二接触112d和第三金属布线112e。第一金属布线112a可以设置在芯衬底100的第二表面104(即，第一绝缘层110a的下表面)中，并且第一金属布线112a的至少一部分可以从第二表面104暴露。第三金属布线112e可以设置在芯衬底100的第一表面102(即，第二绝缘层110b的上表面)中，并且第三金属布线112e的至少一部分可以从第一表面102暴露。可以理解，绝缘层和芯连接布线的数目和布置可以改变。
芯衬底100可以布置在阻挡带20上。芯衬底100的第二表面104可以粘合在阻挡带20上。阻挡带20可以具有板状。例如，可以在芯衬底100的各个通孔106中布置大约200个至大约6,000个裸片。如稍后所描述的，可以执行切单(singulation)工艺以锯切芯衬底，从而完成扇出面板级封装件。
参照图5，可以在芯衬底100的第一表面102上形成第一模制构件120以填充通孔106。
例如，第一模制构件120可以形成在芯衬底100的第一表面102上以完全填充通孔106。因此，芯衬底100的第一表面102可以被第一模制构件120覆盖。
第一模制构件120可以包括例如绝缘材料，诸如环氧树脂。第一模制构件120可以包括例如光可成像电介质(PID)材料。
第一模制构件120的第一表面122可以位于比芯衬底100的第一表面102高的平面上，并且第一模制构件120的第二表面124可以与芯衬底100的第二表面104共面。
参照图6和图7，可以在第一模制构件120上设置第一半导体芯片200，然后，可以在位于芯衬底100的第一表面102上的第一模制构件120上形成第二模制构件130以覆盖第一半导体芯片200。
第一半导体芯片200可以包括第一衬底和位于有源表面(即，第一衬底的第一表面202)上的第一芯片焊盘206。第一半导体芯片200可以通过粘附膜(未示出)粘合在第一模制构件120上。第一半导体芯片200可以布置成使得背面(即，与其上形成有第一芯片焊盘206的第一表面202相对的第二表面204)面向第一模制构件120。第一半导体芯片200可以与芯衬底100的通孔106相对应地布置。
然后，如图7所示，可以在第一模制构件120(其位于芯衬底100的第一表面102上)的第一表面122上形成第二模制构件130以覆盖第一半导体芯片200。因此，第一半导体芯片200的第一表面102可以被第二模制构件130覆盖。
第二模制构件130可以包括例如绝缘材料，诸如环氧树脂。第二模制构件130可以包括例如光成像电介质(PID)材料。第二模制构件130可以包括与第一模制构件120相同或不同的材料。
参照图8和图9，在去除阻挡带20之后，可以将图8中的结构颠倒或倒置，然后可以在第一模制构件120中形成腔126。
通过去除阻挡带20，第一模制构件120的第二表面124可以通过芯衬底100的通孔106暴露。可以对第一模制构件120的通过通孔106暴露的第二表面124执行激光烧蚀工艺，以在第一模制构件120中形成腔126。
腔126可以形成为从第一模制构件120的第二表面124沿厚度方向延伸。腔126可以从第一模制构件120的第二表面124延伸到第一表面122以暴露第一半导体芯片200的第二表面204。
腔126的内侧壁可以与芯衬底100的通孔106的内侧壁间隔开。因此，第一模制构件120的第一部分可以形成在芯衬底100的第一表面102上，并且第一模制构件120的第二部分可以形成在芯衬底100的通孔106的内侧壁上。
参照图10和图11，可以在第一模制构件120的腔126内布置第二半导体芯片210，然后，可以在芯衬底100的第二表面104上形成第三模制构件140以覆盖第二半导体芯片210。
第二半导体芯片210可以设置在第一模制构件120的腔126内。第二半导体芯片210的侧壁可以与腔126的内侧壁间隔开。因此，可以在第二半导体芯片210的侧壁与腔126的内侧壁之间形成空间。
第二半导体芯片210可以包括第二衬底和位于有源表面(即，第二衬底的第一表面212)上的第二芯片焊盘216。第二半导体芯片210可以通过粘附膜220粘合在通过腔126暴露的第一半导体芯片200上。第二半导体芯片210可以布置成使得背面(即，与其上形成有第二芯片焊盘216的第一表面212相对的第二表面214)面向第一半导体芯片200的背面(即，第二表面204)。粘附膜220可以包括例如裸片附接膜(DAF)。
第二半导体芯片210的第一表面212可以与芯衬底100的第二表面104共面。
然后，可以在芯衬底100的第二表面104上形成第三模制构件140以覆盖第二半导体芯片210。第三模制构件140可以被形成为填充第二半导体芯片210的侧壁与腔126的内侧壁之间的空间。因此，第二半导体芯片210的第一表面212、芯衬底100的第二表面104和第一模制构件120的腔126的内侧壁可以被第三模制构件140覆盖。
因此，第三模制构件140的第一部分可以形成在芯衬底100的第二表面104上，第三模制构件140的第二部分可以形成在第一模制构件120的腔126的内侧壁上，并且第三模制构件140的第三部分可以形成在第二半导体芯片210的第一表面212上。
第三模制构件140可以包括例如绝缘材料，诸如环氧树脂。第三模制构件140可以包括例如光可成像电介质(PID)材料。第三模制构件140可以包括与第一模制构件120和第二模制构件130相同或不同的材料。
参照图12至图17，可以在第二模制构件130上形成将第一半导体芯片200和芯衬底100的芯连接布线112彼此电连接的第一再分布布线170，并且可以在第三模制构件140上形成将第二半导体芯片210和芯衬底100的芯连接布线112彼此电连接的第二再分布布线180。
如图12所示，可以对第二模制构件130和第一模制构件120执行第一光刻工艺，以形成暴露芯连接布线112的第三金属布线112e和第一半导体芯片200的第一芯片焊盘206的第一开口132，并且可以对第三模制构件140执行第二光刻工艺，以形成暴露芯连接布线112的第一金属布线112a和第二半导体芯片210的第二芯片焊盘216的第二开口142。在执行第一光刻工艺之后，可以将图12中的结构颠倒或倒置，然后，可以执行第二光刻工艺。
在另一实施方式中，可以对第二模制构件130和第一模制构件120执行激光钻孔工艺以形成第一开口，并且可以对第三模制构件140执行激光钻孔工艺以形成第二开口。可以使用例如UV激光来执行激光钻孔工艺。
如图13所示，可以在第二模制构件130和第一模制构件120上形成第一晶种层152，以电连接到通过第一开口132暴露的第三金属布线112e和第一半导体芯片200的第一芯片焊盘206，并且可以在第三模制构件140上形成第二晶种层150以电连接到通过第二开口142暴露的第一金属布线112a。
如图14和图15所示，可以在第一晶种层152上形成第一光刻胶层162，可以形成第一光刻胶图案166以部分地暴露第一晶种层152，可以在第二晶种层150上形成第二光刻胶层160，然后可以形成第二光刻胶图案164以部分地暴露第二晶种层150。
如图16所示，可以对第一晶种层152的被第一光刻胶图案166暴露的部分执行镀覆工艺以形成第一再分布布线170，然后可以对第二晶种层150的被第二光刻胶图案164暴露的部分执行镀覆工艺以形成第二再分布布线180。
如图17所示，可以去除第一光刻胶图案166，可以去除第一晶种层152的被第一再分布布线170暴露的部分，可以去除第二光刻胶图案164，然后可以去除第二晶种层150的被第二再分布布线180暴露的部分。例如，可以通过闪蚀(flash etching)工艺去除第一晶种层152的该部分和第二晶种层150的该部分。
参照图18，可以在第三模制构件140上形成具有与第二再分布布线180电连接的下再分布布线312的下再分布布线层300。
例如，在第三模制构件140上形成第一下绝缘层310a以覆盖第二再分布布线180之后，可以对第一下绝缘层310a进行图案化以形成分别暴露第二再分布布线180的第三开口。第一下绝缘层310a可以包括例如聚合物层、电介质层等。第一下绝缘层310a可以通过气相沉积工艺、旋涂工艺等形成。
可以在第一下绝缘层310a上形成第一下再分布布线312a，以分别通过第三开口与第二再分布布线180接触。可以在第一下绝缘层310a的一部分和第二再分布布线180的一部分上形成第一下再分布布线312a。可以通过在第一下绝缘层310a的该部分上和第三开口中形成晶种层、对晶种层进行图案化并且执行电镀工艺来形成第一下再分布布线。因此，第一下再分布布线312a的至少一部分可以通过第三开口与第二再分布布线180接触。
第一下再分布布线可以包括例如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、铂(Pt)或其合金。
类似地，在第一下绝缘层310a上形成第二下绝缘层310b以覆盖第一下再分布布线312a之后，可以对第二下绝缘层310b进行图案化以形成分别暴露第一下再分布布线312a的第四开口。
可以在第二下绝缘层310b上形成第二下再分布布线312b，以分别通过第四开口与第一下再分布布线312a接触。第二下再分布布线312b可以形成在第二下绝缘层310b的一部分和第一下再分布布线312a的一部分上。可以通过在第二下绝缘层310b的该部分上和第四开口中形成晶种层、对晶种层进行图案化并且执行电镀工艺来形成第二下再分布布线。因此，第二下再分布布线312b的至少一部分可以通过第四开口与第一下再分布布线312a接触。
可以在第二下绝缘层310b上形成保护层320以暴露第二下再分布布线312b的至少一部分。在示例实施例中，第二下再分布布线312b的该部分可以用作定位焊盘，即，封装焊盘。
因此，可以在位于芯衬底100的第二表面104上的第三模制构件140上形成具有电连接到各个第二再分布布线的下再分布布线312的下再分布布线层300。下再分布布线层的下绝缘层的数目、尺寸、布置等被示为示例并且可以改变。
然后，可以在下再分布布线层300的外表面上形成外部连接构件400(参见图1)，以电连接到下再分布布线312。例如，作为外部连接构件的焊料球可以设置在第二下再分布布线312b的该部分(即，封装焊盘)上。因此，外部连接构件400可以形成在具有扇出型焊料球定位焊盘的下再分布布线层300上。
然后，可以对芯衬底100执行锯切工艺以形成单个扇出面板级封装件，该封装件包括堆叠在其中的第一半导体芯片200和第二半导体芯片210以及外部连接构件，其中一些外部连接构件布置在扇出区域中，以电连接到第一半导体芯片200和第二半导体芯片210。
图19是示出根据示例实施例的半导体封装件的截面图。除了第二模制构件和第一再分布布线的构造之外，该半导体封装件可以与参照图1描述的半导体封装件基本相同或相似。因此，相同的附图标记将用于指代相同或相似的元件，并且将省略关于上述元件的任何进一步的重复说明。
参照图19，半导体封装件11的第一半导体芯片200可以通过第一再分布布线172电连接到芯衬底100的芯连接布线112。在示例实施例中，第一再分布布线172可以包括接合引线。
在示例实施例中，接合引线的第一端部可以通过第二模制构件120中的开口121接合到芯连接布线112，并且接合引线的第二端部可以接合到第一半导体芯片200的第一芯片焊盘206。
第二模制构件130可以包括第一部分和第二部分。接合引线可以设置在第二模制构件130的第一部分上，并且将第一芯片焊盘206和芯连接布线112电连接。第二模制构件130的第二部分可以布置在第一部分上以覆盖接合引线。第一部分和第二部分可以彼此一体地形成，以在第一模制构件120上完全覆盖第一半导体芯片200。
在下文中，将描述制造图19中的半导体封装件的方法。
图20至图26是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。
参照图20，首先，可以执行与参照图4至图6描述的工艺相同或相似的工艺，以将第一半导体芯片200粘合在位于芯衬底100的第一表面102上的第一模制构件120上。然后，可以在第一模制构件120中形成第一开口121以暴露芯连接布线112的至少一部分。在示例实施例中，可以对第一模制构件120执行光刻工艺以形成暴露芯连接布线112的第三金属布线112e的第一开口121。在另一实施方式中，可以对第一模制构件120执行钻孔工艺以形成第一开口。可以使用例如UV激光来执行激光钻孔工艺。
参照图21，可以形成第一再分布布线172以将第一半导体芯片200的第一芯片焊盘206与芯连接布线112电连接。在示例实施例中，可以执行布线接合工艺以形成将第一半导体芯片200的第一芯片焊盘206与芯连接布线112电连接的接合引线，并且接合引线可以被设置为第一再分布布线172。
接下来，可以在位于芯衬底100的第一表面102上的第一模制构件120上形成第二模制构件130以覆盖第一半导体芯片200。第二模制构件130可以形成在位于芯衬底100的第一表面102上的第一模制构件120的第一表面122上以覆盖第一半导体芯片200。因此，第一再分布布线172可以布置在第二模制构件130的第一部分上，并且第二模制构件130的第二部分可以设置在第二模制构件130的第一部分上以覆盖第一再分布布线172。
参照图22，可以将图21中的结构颠倒或倒置。然后，可以在第一模制构件120中形成腔126。例如，通过去除阻挡带20，第一模制构件120的第二表面124可以通过芯衬底100的通孔106而暴露。可以对第一模制构件120的通过通孔106暴露的第二表面124执行激光烧蚀工艺，以在第一模制构件120中形成腔126。
腔126可以形成为从第一模制构件120的第二表面124沿厚度方向延伸。腔126可以从第一模制构件120的第二表面124延伸到第一表面122以暴露第一半导体芯片200的第二表面204。
腔126的内侧壁可以与芯衬底100的通孔106的内侧壁间隔开。因此，第一模制构件120的第一部分可以形成在芯衬底100的第一表面102上，并且第一模制构件120的第二部分可以形成在芯衬底100的通孔106的内侧壁上。
参照图23和图24，可以执行与参照图10和图11描述的工艺相同或相似的工艺，使得第二半导体芯片210可以布置在第一模制构件120的腔126内，然后，可以在芯衬底100的第二表面104上形成第三模制构件140以覆盖第二半导体芯片210。
参照图25，可以在第三模制构件140上形成将第二半导体芯片210和芯衬底100的芯连接布线112彼此电连接的第二再分布布线180。例如，可以对第三模制构件140执行光刻工艺，以形成暴露芯连接布线112的第一金属布线112a的第二开口。然后，可以在第三模制构件140上形成第二再分布布线180，以电连接到通过开口暴露的第一金属布线112a。
参照图26，可以执行与参照图10和图11描述的工艺相同或相似的工艺，以在第三模制构件140上形成具有电连接到第二再分布布线180的下再分布布线312的下再分布布线层300。
然后，可以在下再分布布线层300的外表面上形成外部连接构件400(参见图19)，以电连接到下再分布布线312。
然后，可以对芯衬底100执行锯切工艺以形成单个扇出面板级封装件，该封装件包括堆叠在其中的第一半导体芯片200和第二半导体芯片210以及外部连接构件，一些外部连接构件布置在扇出区域中，以电连接到第一半导体芯片200和第二半导体芯片210。
图27是示出根据示例实施例的半导体封装件的截面图。除了上再分布布线层和额外的第二封装件之外，该半导体封装件可以与参照图1描述的半导体封装件基本相同或相似。因此，相同的附图标记将用于指代相同或相似的元件，并且可以省略关于上述元件的进一步的重复说明。
参照图27，半导体封装件12可以包括第一封装件和堆叠在第一封装上的第二封装件500。第一封装件可以包括：芯衬底100，第一至第三模制构件120、130、140，第一半导体芯片200和第二半导体芯片210，第一再分布布线170，第二再分布布线180，下再分布布线层300和上再分布布线层。
在示例实施例中，上再分布布线层可以布置在第二模制构件130上，并且可以包括分别电连接到第一再分布布线170的上再分布布线352。
上再分布布线层可以包括上绝缘层350和上再分布布线352，上绝缘层350形成在第二模制构件130上并且具有暴露第一再分布布线170的开口，上再分布布线352通过开口与第一再分布布线170直接接触。
可以理解的是，上再分布布线层的上绝缘层和上再分布布线的数目、尺寸、布置等被示为示例并且可以改变。
第二封装件500可以包括：第二封装衬底510，安装在第二封装衬底510上的第三半导体芯片520和第四半导体芯片530，以及位于第二封装衬底510上以覆盖第三半导体芯片520和第四半导体芯片530的模制构件550。
第二封装件500可以经由导电连接构件560堆叠在第一封装件上。例如，导电连接构件560可以包括焊料球、导电凸块等。导电连接构件560可以布置在上再分布布线352与第二封装衬底510的第一接合焊盘512之间。因此，第一封装件和第二封装件500可以通过导电连接构件560彼此电连接。
第三半导体芯片520和第四半导体芯片530可以通过粘附构件堆叠在第二封装衬底510上。接合引线540可以将第三半导体芯片520的芯片焊盘522和第四半导体芯片530的芯片焊盘532电连接到第二封装衬底510的第二接合焊盘514。第三半导体芯片520和第四半导体芯片530可以通过接合引线540电连接到第二封装衬底510。
尽管在图中示出了包括以引线接合方式安装的两个半导体芯片的第二封装件500，但是可以理解的是，第二封装件的半导体芯片的数目、安装方式等可以改变。
在下文中，将描述制造图27中的半导体封装件的方法。
图28和图29是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。
参照图28，首先，可以执行与参照图4至图18描述的工艺相同或相似的工艺，以在第三模制部件140上形成具有与第二再分布布线180电连接的下再分布布线312的下再分布布线层300，然后在第二模制构件130上形成具有电连接到第一再分布布线170的上再分布布线352的上再分布布线层。
例如，可以在第二模制构件130上形成上绝缘层350以覆盖第一再分布布线170，然后可以对上绝缘层350进行图案化以形成分别暴露第一再分布布线170的开口。上绝缘层350可以包括例如聚合物层、电介质层等。上绝缘层可以通过气相沉积工艺、旋涂工艺等形成。
可以在上绝缘层350上形成上再分布布线352以分别与第一再分布布线170接触。上再分布布线352可以形成在上绝缘层350的一部分和第一再分布布线170的一部分上。可以通过在上绝缘层350的该部分上和开口中形成晶种层、对晶种层进行图案化并执行电镀工艺来形成上再分布布线。因此，上再分布布线352的至少一部分可以通过开口与第一再分布布线170接触。例如，上再分布布线可以包括例如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、铂(Pt)或其合金。
可以理解的是，上再分布布线层的上绝缘层的数目、尺寸、布置等被示为示例并且可以改变。
然后，可以对芯衬底100执行锯切工艺以形成包括第一半导体芯片200和第二半导体芯片210的第一封装件。
参照图29，可以在第一封装件上堆叠第二封装件500。
在示例实施例中，第二封装件500可以包括：第二封装衬底510，安装在第二封装衬底510上的第三半导体芯片520和第四半导体芯片530，以及位于第二封装衬底510上以覆盖第三半导体芯片520和第四半导体芯片530的模制构件550。
第二封装件500可以经由导电连接构件560堆叠在第一封装件上。例如，导电连接构件560可以包括焊料球、导电凸块等。导电连接构件560可以布置在上再分布布线层的上再分布布线352与第二封装衬底510的第一接合焊盘512之间。因此，第一封装件和第二封装件500可以通过导电连接构件560彼此电连接。
第三半导体芯片520和第四半导体芯片530可以通过粘附构件堆叠在第二封装衬底510上。接合引线540可以将第三半导体芯片520的芯片焊盘522和第四半导体芯片530的芯片焊盘532电连接到第二封装衬底510的第二接合焊盘514。第三半导体芯片520和第四半导体芯片530可以通过接合引线540电连接到第二封装衬底510。
图30是示出根据示例实施例的半导体封装件的截面图。除了第一半导体芯片和第二半导体芯片的构造之外，该半导体封装件可以与参照图1描述的半导体封装件基本相同或相似。因此，相同的附图标记将用于指代相同或相似的元件，并且可以省略关于上述元件的进一步的重复说明。
参照图30，可以在第一半导体芯片200的第二表面204中设置凹部208。凹部208可以连接到第三模制构件140的腔126。
第二半导体芯片210可以布置在第一半导体芯片200的凹部208上。第二半导体芯片210可以通过粘附膜粘合在第一半导体芯片200的凹部208的通过腔126暴露的底表面上。可以考虑粘附膜220的厚度来确定凹部208的深度。
在下文中，将描述制造图30中的半导体封装件的方法。
图31和图32是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。
参照图31，首先，可以执行与参照图4至图9描述的工艺相同或相似的工艺以在第一模制构件120中形成腔126，并且可以部分地去除第一半导体芯片200的第二表面204。例如，可以对第一模制构件120的通过通孔106暴露的第二表面124执行激光烧蚀工艺，以在第一模制构件120中形成腔126。可以执行激光烧蚀工艺直到第一半导体芯片200的第二表面204被部分地去除。因此，腔126可以形成为穿透第一模制构件120，并且凹部208可以形成在第一半导体芯片200的第二表面204中以连接到腔126。考虑粘附膜的厚度来确定凹部208的深度，如下所述。
参照图32，可以在第一模制构件120的腔126内布置第二半导体芯片210，然后，可以在芯衬底100的第二表面104上形成第三模制构件140以覆盖第二半导体芯片210。例如，第二半导体芯片210可以布置在第一半导体芯片200的凹部208上，并且第二半导体芯片210可以通过粘附膜220粘合在第一半导体芯片200的凹部208的通过腔126暴露的底表面上。凹部208的深度可以例如与粘附膜220的厚度相同。
图33是示出根据示例实施例的半导体封装件的截面图。除了第一半导体芯片和第二半导体芯片的布置以及第三模制构件的构造之外，该半导体封装件可以与参照图1描述的半导体封装件基本相同或相似。因此，相同的附图标记将用于指代相同或相似的元件，并且可以省略关于上述元件的进一步的重复说明。
参照图33，半导体封装件14的第一模制构件120可以包括覆盖芯衬底100的第一表面102的第一部分、覆盖芯衬底100的通孔106的内侧壁的第二部分以及覆盖第一半导体芯片200的第二表面204的中间区域的第三部分。
在示例实施例中，腔126可以从芯衬底100的第二表面104沿厚度方向延伸到预定深度。腔126的侧壁可以由第一模制构件120的第二部分的外侧表面限定，并且腔126的底表面(底部相对于图33被颠倒，如下面结合图34和图35所描述的)可以由第一模制构件120的第三部分的表面限定。
第二半导体芯片210可以布置在第一模制构件120的腔126内。第二半导体芯片210可以通过粘附膜220粘合在腔126的底表面上。第一模制构件120的第三部分可以介于第一半导体芯片200与第二半导体芯片210之间。
在下文中，将描述制造图33中的半导体封装件的方法。
图34和图35是示出根据示例实施例的制造半导体封装件的方法中的各阶段的截面图。
参照图34，首先，可以执行与参照图4至图8描述的工艺相同或相似的工艺，可以将图8中的结构颠倒或倒置，然后可以在第一模制构件120中形成腔126。例如，可以对第一模制构件120的通过通孔106暴露的第二表面124执行激光烧蚀工艺，以在第一模制构件120中形成腔126。为了形成腔125，可以执行激光烧蚀工艺，然后在到达第一半导体芯片200的第二表面204之前停止，使得腔126具有底表面，并且从芯衬底100的第二表面104起在厚度方向上具有预定深度。因此，第一模制构件120的第一部分可以形成在芯衬底100的第一表面102上，第一模制构件120的第二部分可以形成在芯衬底100的通孔106的内侧壁上，并且第一模制构件120的第三部分可以形成在第一半导体芯片200的第二表面204的中间区域上。
参照图35，可以在第一模制构件120的腔126内布置第二半导体芯片210，然后，可以在芯衬底100的第二表面104上形成第三模制构件140以覆盖第二半导体芯片210。
第二半导体芯片210可以布置在第一模制构件120的腔126内。第二半导体芯片210可以通过粘附膜220粘合在腔126的底表面上。因此，第一模制构件120的第三部分可以介于第一半导体芯片200和第二半导体芯片210之间。
半导体封装件可以包括诸如逻辑器件或存储器件的半导体器件。半导体封装件可以包括诸如中央处理单元(CPU)、主处理单元(MPU)或应用处理器(AP)等的逻辑器件，以及诸如DRAM器件、HBM器件的易失性存储器件，或者诸如闪存器件、PRAM器件、MRAM器件、ReRAM器件等的非易失性存储器件。
如上所述，实施例涉及一种扇出面板级封装件及其制造方法。实施例可以提供一种能够减小制造成本并且具有堆叠封装结构的扇出半导体封装件。
根据示例实施例，作为扇出面板级封装件的半导体封装件可以包括：设置在第二半导体芯片的外部区域中的芯衬底；以及覆盖芯衬底的下表面的下再分布布线层。作为堆叠封装件的半导体封装件可以包括堆叠在第二半导体芯片上的第一半导体芯片。
因此，半导体封装件可以被设置为包括经由作为扇出面板级封装件的支撑框架的芯衬底堆叠的第一半导体芯片和第二半导体芯片的堆叠封装件。第一半导体芯片和第二半导体芯片可以通过位于芯衬底的正面上的第一再分布布线和位于芯衬底的背面上的第二再分布布线彼此电连接，从而缩短了信号传输长度，由此优化了信号完整性(SI)。
本文已经公开了示例实施例，并且尽管采用了特定术语，但是仅在一般和描述性意义上使用和解释它们，而不是出于限制的目的。在某些情况下，对于在提交本申请之时的本领域普通技术人员而言显而易见的是，除非另外特别指出，否则结合特定实施例描述的特征、特性和/或元件可以单独使用，或者与结合其他实施例描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离如所附权利要求书中阐述的本发明的精神和范围的情况下，可以做出形式和细节上的各种改变。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
芯衬底，所述芯衬底具有通孔；
第一模制构件，所述第一模制构件至少部分地填充所述通孔并且覆盖所述芯衬底的上表面，所述第一模制构件具有在所述通孔内并且从所述芯衬底的下表面沿厚度方向延伸的腔；
第一半导体芯片，所述第一半导体芯片位于在所述芯衬底的所述上表面上的所述第一模制构件上；
第二半导体芯片，所述第二半导体芯片位于所述第一模制构件的所述腔内；
第二模制构件，所述第二模制构件位于所述第一模制构件上并且覆盖所述第一半导体芯片；
第三模制构件，所述第三模制构件填充所述腔并且覆盖所述芯衬底的所述下表面；
第一再分布布线，所述第一再分布布线位于所述第二模制构件上，并且将所述第一半导体芯片的第一芯片焊盘与所述芯衬底的芯连接布线电连接；
第二再分布布线，所述第二再分布布线位于所述第三模制构件上，并且将所述第二半导体芯片的第二芯片焊盘与所述芯衬底的所述芯连接布线电连接；以及
下再分布布线层，所述下再分布布线层位于所述第三模制构件上，并且具有分别电连接到所述第二再分布布线的下再分布布线，
其中，所述第一模制构件、所述第二模制构件和所述第三模制构件中的至少一者包括光可成像电介质材料。
2.根据权利要求1所述的半导体封装件，其中，所述第一模制构件包括覆盖所述芯衬底的所述上表面的第一部分和覆盖所述通孔的内侧壁的第二部分，并且所述腔设置在所述第一模制构件的所述第二部分中。
3.根据权利要求1所述的半导体封装件，其中，所述第三模制构件包括覆盖所述芯衬底的所述下表面的第三部分、覆盖所述第一模制构件的所述腔的内侧壁的第四部分以及覆盖所述第二半导体芯片的第一表面的第五部分。
4.根据权利要求1所述的半导体封装件，其中，所述第二半导体芯片的其上形成有所述第二芯片焊盘的第一表面与所述芯衬底的所述下表面共面。
5.根据权利要求1所述的半导体封装件，其中，所述第一半导体芯片的与其上形成有所述第一芯片焊盘的第一表面相对的第二表面，面对所述第二半导体芯片的与其上形成有所述第二芯片焊盘的第一表面相对的第二表面。
6.根据权利要求5所述的半导体封装件，其中，粘附膜介于所述第一半导体芯片的所述第二表面与所述第二半导体芯片的所述第二表面之间。
7.根据权利要求1所述的半导体封装件，其中，所述腔穿透所述第一模制构件。
8.根据权利要求1所述的半导体封装件，其中，所述腔从所述芯衬底的所述下表面延伸到预定深度，并且所述第一模制构件的一部分介于所述第一半导体芯片与所述第二半导体芯片之间。
9.根据权利要求1所述的半导体封装件，其中，所述第一再分布布线包括接合引线，并且所述第二模制构件还包括覆盖所述接合引线的部分。
10.根据权利要求1所述的半导体封装件，所述半导体封装件还包括上再分布布线层，所述上再分布布线层位于所述第二模制构件上并且具有分别电连接到所述第一再分布布线的上再分布布线。
11.一种半导体封装件，所述半导体封装件包括：
芯衬底，所述芯衬底具有彼此相对的第一表面和第二表面，并具有从所述第一表面延伸到所述第二表面的通孔；
第一模制构件，所述第一模制构件具有覆盖所述芯衬底的所述第一表面的第一部分和覆盖所述通孔的内侧壁的第二部分，所述第二部分具有在所述通孔内并且延伸到所述芯衬底的所述第二表面的腔；
第一半导体芯片，所述第一半导体芯片位于所述第一模制构件的所述第一部分上；
第二半导体芯片，所述第二半导体芯片位于所述第一模制构件的所述腔内；
第二模制构件，所述第二模制构件位于所述第一模制构件的所述第一部分上并且覆盖所述第一半导体芯片；
第三模制构件，所述第三模制构件位于所述芯衬底的所述第二表面上，填充所述第一模制构件的所述腔，并且覆盖所述第二半导体芯片；
第一再分布布线，所述第一再分布布线位于所述第二模制构件上并且将所述第一半导体芯片的第一芯片焊盘与所述芯衬底的芯连接布线电连接；
第二再分布布线，所述第二再分布布线位于所述第三模制构件上，并且将所述第二半导体芯片的第二芯片焊盘与所述芯衬底的所述芯连接布线电连接；以及
下再分布布线层，所述下再分布布线层位于所述第三模制构件上并且具有分别电连接到所述第二再分布布线的下再分布布线。
12.根据权利要求11所述的半导体封装件，其中，所述第一半导体芯片的与其上形成有所述第一芯片焊盘的第一表面相对的第二表面，面对所述第二半导体芯片的与其上形成有所述第二芯片焊盘的第一表面相对的第二表面。
13.根据权利要求12所述的半导体封装件，其中，粘附膜介于所述第一半导体芯片的所述第二表面与所述第二半导体芯片的所述第二表面之间。
14.根据权利要求11所述的半导体封装件，其中，所述腔穿透所述第一模制构件。
15.根据权利要求11所述的半导体封装件，其中，所述腔从所述芯衬底的所述第二表面延伸到预定深度，并且所述第一模制构件的一部分介于所述第一半导体芯片与所述第二半导体芯片之间。
16.根据权利要求11所述的半导体封装件，其中，所述第三模制构件包括覆盖所述芯衬底的所述第二表面的第三部分、覆盖所述第一模制构件的所述腔的内侧壁的第四部分以及覆盖所述第二半导体芯片的第一表面的第五部分。
17.根据权利要求11所述的半导体封装件，其中，所述第二半导体芯片的其上形成有所述第二芯片焊盘的第一表面与所述芯衬底的所述第二表面共面。
18.根据权利要求11所述的半导体封装件，其中，所述第一再分布布线包括接合引线，并且所述第二模制构件还包括覆盖所述接合引线的部分。
19.根据权利要求11所述的半导体封装件，所述半导体封装件还包括外部连接构件，所述外部连接构件位于所述下再分布布线层的外表面上。
20.根据权利要求11所述的半导体封装件，所述半导体封装件还包括上再分布布线层，所述上再分布布线层位于所述第二模制构件上，并且具有分别电连接到所述第一再分布布线的上再分布布线。
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