CN113363324B - P沟道的平面型vdmos和平面型igbt - Google Patents

P沟道的平面型vdmos和平面型igbt Download PDF

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CN113363324B
CN113363324B CN202010149140.0A CN202010149140A CN113363324B CN 113363324 B CN113363324 B CN 113363324B CN 202010149140 A CN202010149140 A CN 202010149140A CN 113363324 B CN113363324 B CN 113363324B
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王学良
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GTA Semiconductor Co Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

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Abstract

本发明公开了一种P沟道的平面型VDMOS和平面型IGBT，其中，P沟道的平面型VDMOS包括n阱区，所述n阱区的沟道内埋有至少一个p岛，所述p岛为p型区，所述p型区采用p型半导体元素形成。本发明提供的P沟道的平面型VDMOS和平面型IGBT，通过在器件的n阱区的沟道内埋设p岛，能够有效调整器件的Vth的范围并且一致性更好。p岛的数量取决于具体的应用需求，相对而言，埋入的p岛的数量越多，器件的Vth值越高。

Description

P沟道的平面型VDMOS和平面型IGBT
技术领域
本发明属于集成电路技术领域，特别涉及一种P沟道的平面型VDMOS(verticaldouble-diffused metal oxide semiconductor field effect transistor，垂直双扩散金属氧化物半导体场效应晶体管)和平面型IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)。
背景技术
图1为现有技术中P沟道的平面型VDMOS的元胞结构的切面示意图，包括Gate(栅极)、Source(源级)、Drain(漏极)。另外，从下至上还依次包括p+区、p-drift(p-漂移区)、对称的n+体区，位于n+体区中的n-well(n阱)以及p+源区。
图2为现有技术中P沟道的平面型IGBT的元胞结构的切面示意图，包括Gate(栅极)、Cathode(阴级)、Anode(阳极)，从下至上还依次包括n+区、p-drift、对称的n+体区，位于n+体区中的n阱以及p+阳极区。
Vth(开启电压)是VDMOS器件和IGBT器件的一个重要参数，当栅源电压大于Vth时，栅极下面的n阱表面的空穴浓度会高于电子浓度，使得N型半导体反型为P型而形成反型层，从而进一步形成P沟道。如何调节器件的Vth的大小及一致性一直是业界关注的问题。
现有技术中调控Vth大小多从n阱的浓度和栅氧厚度着手。从n阱的浓度调整，其Vth的可调范围受限于LATCHUP(抗闩锁)能力；而从栅氧厚度调节的方式其Vth的可调范围受限于栅氧工艺技术。如何有效调整P沟道的平面型VDMOS和平面型IGBT的Vth的可控范围以及一致性是急需解决的问题。
发明内容
本发明要解决的技术问题是为了克服现有技术中调整P沟道的平面型VDMOS和平面型IGBT的Vth的可控范围以及一致性有待提高的缺陷，提供一种能够有效调整器件的Vth的范围并且一致性更好的P沟道的平面型VDMOS和平面型IGBT。
本发明是通过下述技术方案来解决上述技术问题：
本发明第一方面提供了一种P沟道的平面型VDMOS，包括n阱区，所述n阱区的沟道内埋有至少一个p岛，所述p岛为p型区，所述p型区采用p型半导体元素形成。
本方案中，通过在n阱区的沟道内埋设p岛，能够有效调整器件的Vth的范围并且一致性更好。可以利用器件的不同层的光刻板在适当层制作时形成p岛，也就是说，本方案对p岛的具体制作步骤不作限定，只要最终生成的p岛的位置处于n阱区的沟道内即可。p岛的数量取决于具体的应用需求，相对而言，埋入的p岛的数量越多，P沟道的平面型VDMOS的Vth值越高。一致性一方面体现在同一个晶圆上的P沟道的平面型VDMOS的Vth趋于一致，另外一方面体现在加入p岛的P沟道的平面型VDMOS的Vth值更加符合预期值。
较佳地，所述p型半导体元素包括硼、铝、镓、铟、铊中的至少一种。
较佳地，所述n阱区的沟道内埋有多个所述p岛，多个所述p岛间隔设置。
本方案中，p岛的数量有多个，多个p岛成间隔设置。通过调节p岛之间的间距、元素的剂量以及结深实现对需要的Vth的值的范围及一致性的调节。
较佳地，每个所述p岛采用硼、铝、镓、铟、铊中的至少一种形成。
本方案中，多个p岛中每个采用的元素可以相同，也可以不相同。
本发明第二方面提供了一种P沟道的平面型IGBT，包括n阱区，所述n阱区的沟道内埋有至少一个p岛，所述p岛为p型区，所述p型区采用p型半导体元素形成。
本方案中，通过在n阱区的沟道内埋设p岛，能够有效调整器件的Vth的范围并且一致性更好。可以利用器件的不同层的光刻板在适当层制作时形成p岛，也就是说，本方案对p岛的具体制作步骤不作限定，只要最终生成的p岛的位置处于n阱区的沟道内即可。p岛的数量取决于具体的应用需求，相对而言，埋入的p岛的数量越多，P沟道的平面型IGBT的Vth值越高。一致性一方面体现在同一个晶圆上的P沟道的平面型IGBT的Vth趋于一致，另外一方面体现在加入p岛的P沟道的平面型IGBT的Vth值更加符合预期值。
较佳地，所述p型半导体元素包括硼、铝、镓、铟、铊中的至少一种。
较佳地，所述n阱区的沟道内埋有多个所述p岛，多个所述p岛间隔设置。
本方案中，p岛的数量有多个，多个p岛成间隔设置。通过调节p岛之间的间距、元素的剂量以及结深实现对需要的Vth的值的范围及一致性的调节。
较佳地，每个所述p岛采用硼、铝、镓、铟、铊中的至少一种形成。
本方案中，多个p岛中每个采用的元素可以相同，也可以不相同。
本发明的积极进步效果在于：
本发明提供的P沟道的平面型VDMOS和平面型IGBT，通过在器件的n阱区的沟道内埋设p岛，能够有效调整器件的Vth的范围并且一致性更好。p岛的数量取决于具体的应用需求，相对而言，埋入的p岛的数量越多，器件的Vth值越高。
附图说明
图1为现有技术中P沟道的平面型VDMOS的元胞结构的切面示意图。
图2为现有技术中P沟道的平面型IGBT的元胞结构的切面示意图。
图3为本发明实施例1的P沟道的平面型VDMOS的元胞结构的切面示意图。
图4为本发明实施例2的P沟道的平面型IGBT的元胞结构的切面示意图。
具体实施方式
下面通过实施例的方式进一步说明本发明，但并不因此将本发明限制在所述的实施例范围之中。
实施例1
本实施例提供了一种P沟道的平面型VDMOS，图3为该P沟道的平面型VDMOS的元胞结构的切面示意图，包括Gate、Source和Drain，从下至上还依次包括p+区1、p-drift、对称的n+体区2，位于n+体区2中的n阱以及p+源区3。本实施例中，n阱区的沟道内埋有至少一个p岛4，p岛4为p型区，p型区采用p型半导体元素形成。其中，p型半导体元素包括硼、铝、镓、铟、铊中的至少一种。
本实施例中，n阱区的沟道内埋有多个p岛4，多个p岛4间隔设置。每个p岛4采用硼、铝、镓、铟、铊中的至少一种形成。通过调节p岛4之间的间距、元素的剂量以及结深实现对需要的Vth的值的范围及一致性的调节。本实施例中，多个p岛4中每个采用的元素可以相同，也可以不相同。
本实施例中，通过在n阱区的沟道内埋设p岛4，能够有效调整器件的Vth的范围并且一致性更好。可以利用器件的不同层的光刻板在适当层制作时形成p岛4，也就是说，本实施例对p岛4的具体制作步骤不作限定，只要最终生成的p岛4的位置处于n阱区的沟道内即可。p岛4的数量取决于具体的应用需求，相对而言，埋入的p岛4的数量越多，P沟道的平面型VDMOS的Vth值越高。一致性一方面体现在同一个晶圆上的P沟道的平面型VDMOS的Vth趋于一致，另外一方面体现在加入p岛4的P沟道的平面型VDMOS的Vth值更加符合预期值。
实施例2
本实施例提供了一种P沟道的平面型IGBT，图4为该P沟道的平面型IGBT的元胞结构的切面示意图，包括Gate、Cathode和Anode，从下至上还依次包括n+区5、p-drift、对称的n+体区6，位于n+体区6中的n阱以及p+阳极区7。本实施例中，n阱区的沟道内埋有至少一个p岛8，p岛8为p型区，p型区采用p型半导体元素形成。其中，p型半导体元素包括硼、铝、镓、铟、铊中的至少一种。
本实施例中，n阱区的沟道内埋有多个p岛8，多个p岛8间隔设置。每个p岛8采用硼、铝、镓、铟、铊中的至少一种形成。通过调节p岛8之间的间距、元素的剂量以及结深实现对需要的Vth的值的范围及一致性的调节。本实施例中，多个p岛8中每个采用的元素可以相同，也可以不相同。
本实施例中，通过在n阱区的沟道内埋设p岛8，能够有效调整器件的Vth的范围并且一致性更好。可以利用器件的不同层的光刻板在适当层制作时形成p岛8，也就是说，本实施例对p岛8的具体制作步骤不作限定，只要最终生成的p岛8的位置处于n阱区的沟道内即可。p岛8的数量取决于具体的应用需求，相对而言，埋入的p岛8的数量越多，P沟道的平面型IGBT的Vth值越高。一致性一方面体现在同一个晶圆上的P沟道的平面型IGBT的Vth趋于一致，另外一方面体现在加入p岛8的P沟道的平面型IGBT的Vth值更加符合预期值。
虽然以上描述了本发明的具体实施方式，但是本领域的技术人员应当理解，这仅是举例说明，本发明的保护范围是由所附权利要求书限定的。本领域的技术人员在不背离本发明的原理和实质的前提下，可以对这些实施方式做出多种变更或修改，但这些变更和修改均落入本发明的保护范围。

Claims (4)

1.一种P沟道的平面型VDMOS，包括n阱区，其特征在于，所述n阱区的沟道内埋有多个p岛，多个p岛间隔设置，所述p岛为p型区，所述p型区采用p型半导体元素形成，所述p岛用于通过间距、元素的剂量以及结深的调节实现对需要的开启电压Vth的值的范围及一致性的调节。
2.如权利要求1所述的P沟道的平面型VDMOS，其特征在于，所述p型半导体元素包括硼、铝、镓、铟、铊中的至少一种。
3.一种P沟道的平面型IGBT，包括n阱区，其特征在于，所述n阱区的沟道内埋有多个p岛，多个p岛间隔设置，所述p岛为p型区，所述p型区采用p型半导体元素形成，所述p岛用于通过间距、元素的剂量以及结深的调节实现对需要的开启电压Vth的值的范围及一致性的调节。
4.如权利要求3所述的P沟道的平面型IGBT，其特征在于，所述p型半导体元素包括硼、铝、镓、铟、铊中的至少一种。
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JP2001094097A (ja) * 1999-09-21 2001-04-06 Denso Corp 炭化珪素半導体装置及びその製造方法
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KR100843212B1 (ko) * 2006-11-29 2008-07-02 삼성전자주식회사 확산방지영역을 갖는 반도체 소자와 그의 제조 방법
JP5767430B2 (ja) * 2007-08-10 2015-08-19 ローム株式会社 半導体装置および半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0452817A1 (en) * 1990-04-20 1991-10-23 Kabushiki Kaisha Toshiba Semiconductor device with MOS-transistors and method of manufacturing the same
JP2001094097A (ja) * 1999-09-21 2001-04-06 Denso Corp 炭化珪素半導体装置及びその製造方法
CN109728097A (zh) * 2018-12-29 2019-05-07 中山汉臣电子科技有限公司 一种功率半导体mos器件及其制备方法

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