CN113363314B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113363314B CN113363314B CN202010149361.8A CN202010149361A CN113363314B CN 113363314 B CN113363314 B CN 113363314B CN 202010149361 A CN202010149361 A CN 202010149361A CN 113363314 B CN113363314 B CN 113363314B
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- 238000000034 method Methods 0.000 title claims abstract description 131
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000002955 isolation Methods 0.000 claims abstract description 112
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000010410 layer Substances 0.000 claims description 450
- 239000000463 material Substances 0.000 claims description 145
- 150000002500 ions Chemical class 0.000 claims description 95
- 230000008569 process Effects 0.000 claims description 89
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 29
- -1 silicon ions Chemical class 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 13
- 230000004048 modification Effects 0.000 claims description 9
- 238000012986 modification Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910001439 antimony ion Inorganic materials 0.000 claims description 4
- 229910001449 indium ion Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- 238000001312 dry etching Methods 0.000 description 17
- 238000005137 deposition process Methods 0.000 description 12
- 239000007772 electrode material Substances 0.000 description 12
- 238000001039 wet etching Methods 0.000 description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 229910021324 titanium aluminide Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000003054 catalyst Substances 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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Abstract
A semiconductor structure and method of forming the same, the semiconductor structure comprising: a substrate comprising a first region, a second region, and a third region between the first and second regions, the third region having a first opening therein and a first channel pillar on a surface of the first region and a second channel pillar on a surface of the second region; a first isolation structure within the first opening, a top surface of the first isolation structure being higher than the substrate surface; a first work function layer located on the first channel pillar surface and the first isolation structure top surface; and a second work function layer positioned on the surface of the second channel column and the top surface of the first isolation structure. Thus, the performance of the semiconductor device is improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and conventional fin field effect transistors have limitations in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a gate-all-around (GAA) structure field effect transistor is proposed, so that the volume for serving as a channel region is increased, and the operating current of the fin type field effect transistor with the channel gate-around structure is further increased, thereby improving the performance of the semiconductor device.
However, the performance of semiconductor devices is still in need of improvement.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of a semiconductor device.
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate comprising a first region, a second region, and a third region between the first and second regions, the third region having a first opening therein and a first channel pillar on a surface of the first region and a second channel pillar on a surface of the second region; a first isolation structure within the first opening, a top surface of the first isolation structure being higher than the substrate surface; a first work function layer located on the first channel pillar surface and the first isolation structure top surface; and a second work function layer positioned on the surface of the second channel column and the top surface of the first isolation structure.
Optionally, the method further comprises: and a gate electrode layer positioned on the surface of the first work function layer and the surface of the second work function layer.
Optionally, the method further comprises: a first gate dielectric layer between the first channel pillar and the first work function layer, and a second gate dielectric layer between the second channel pillar and the second work function layer.
Optionally, the material of the first work function layer includes titanium aluminide.
Optionally, the material of the second work function layer includes titanium nitride or tantalum nitride.
Optionally, the material of the first isolation structure includes silicon oxide, silicon oxynitride or silicon oxycarbonitride.
Optionally, the material of the first gate dielectric layer includes a combination of silicon oxide and a high dielectric constant material; the material of the second gate dielectric layer comprises a combination of silicon oxide and a high dielectric constant material.
Optionally, the substrate includes: a first source-drain doped layer located in the first region, wherein first ions are located in the first source-drain doped layer; and a second source-drain doped layer positioned in the second region, wherein second ions are arranged in the second source-drain doped layer, and the conductivity types of the first ions and the second ions are different.
Optionally, the first ion is an N-type ion, and the N-type ion includes a phosphorus ion, an arsenic ion or an antimony ion; the second ion is P-type ionA seed, the P-type ion including boron ion and BF 2 -ions or indium ions.
Optionally, the method further comprises: and the first dielectric layer is positioned on the surfaces of the first area and the second area.
Optionally, in a direction perpendicular to the substrate surface, a distance between the top surface of the first isolation structure and the surface of the first dielectric layer ranges from 3 nm to 20 nm.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first region, a second region and a third region positioned between the first region and the second region, a first channel column is formed on the surface of the first region, a second channel column is formed on the surface of the second region, and a first opening is formed in the third region; forming a first isolation structure in the first opening, wherein the top surface of the first isolation structure is higher than the surface of the substrate; forming a first work function layer on the surface of the first channel column and the surface of the first isolation structure; and forming a second work function layer on the surface of the second channel column and the surface of the first isolation structure.
Optionally, the method for forming the first opening includes: forming a first protection layer on the first channel column surface, the second channel column surface, the substrate of the first region and the substrate of the second region; and etching the substrate of the third region by taking the first protective layer as a mask.
Optionally, the method for forming the first isolation structure includes: forming a first isolation structure material layer in the first opening and on the surface of the first protective layer; modifying the first isolation structure material layer of the third region; and after the modification treatment, etching the first isolation structure material layer until the first protective layer on the surface of the substrate is exposed.
Optionally, the method for modifying the first isolation structure material layer of the third region includes: forming a first patterned layer on the surface of the first isolation structure material layer, wherein the first patterned layer exposes the first isolation structure material layer of the third region; and taking the first graphical layer as a mask, and performing an ion implantation process on the first isolation structure material layer.
Optionally, the process parameters of the ion implantation process include: the implanted ion species are silicon ions; the energy range of ion implantation is 1 KeV-30 KeV; the ion implantation dose range was 1e14atm/cm 2 ～2e16atm/cm 2 。
Optionally, the material of the first protection layer includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
Optionally, the method further comprises: and forming a first gate dielectric layer between the first work function layer and the surface of the first channel column, and forming a second gate dielectric layer between the second work function layer and the surface of the second channel column.
Optionally, the method further comprises: and forming a gate electrode layer on the surface of the first work function layer and the surface of the second work function layer.
Optionally, the method further comprises: and forming a first dielectric layer on the surface of the first region and the surface of the second region before forming the first isolation structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure provided by the technical scheme of the invention, as the first work function layer and the second work function layer are positioned on the top surface of the first isolation structure, namely the connection position between the first work function layer and the second work function layer is positioned on the top surface of the first isolation structure, the length of the diffusion path of ions in the first work function layer or ions in the second work function layer is increased, so that the number of the ions in the first work function layer on the surface of the first channel column or the ions in the second work function layer on the surface of the second channel column to diffuse towards each other is reduced, namely the change of the ion concentration in the first work function layer on the surface of the first channel column and the change of the ion concentration in the second work function layer on the surface of the second channel column are reduced, the change of the opening voltage of the semiconductor device is reduced, the electrical performance deviation of the semiconductor device is reduced, the stability of the electrical performance of the semiconductor device is improved, and the performance of the semiconductor device is improved.
Drawings
FIG. 1 is a schematic cross-sectional structure of a CMOS device;
Fig. 2 to 13 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices is still in need of improvement. The analysis will now be described with reference to specific examples.
It should be noted that the term "surface" in this specification is used to describe a relative positional relationship of a space, and is not limited to whether or not it is in direct contact.
Fig. 1 is a schematic cross-sectional structure of a CMOS device.
Referring to fig. 1, the CMOS device includes: a substrate comprising a first region I and a second region II, wherein the first region I is provided with a first base 11, the first base 11 is a P-type silicon substrate, the second region II is provided with a second base 12, and the second base 12 is an N-type silicon substrate; the first source-drain doped layer 20 is located on a part of the surface of the first substrate 11, and N-type ions are doped in the first source-drain doped layer 20; a second source-drain doped layer 30 located on a part of the surface of the second substrate 12, where P-type ions are doped in the second source-drain doped layer 30; a first channel pillar 40 located on a portion of the surface of the first source-drain doped layer 20; a second channel pillar 50 located on a portion of the surface of the second source-drain doped layer 30; a first dielectric layer 60 located on the surface of the first source-drain doped layer 20, the surface of the second source-drain doped layer 30, between the first source-drain doped layer 20 and the second source-drain doped layer 30, and between the first substrate 11 and the second substrate 12; a first gate structure located on a portion of the sidewall surface of the first channel pillar 40 and a portion of the surface of the first dielectric layer 60 in the first region I; and a second gate structure located on a portion of the sidewall surface of the second channel pillar 50 and a portion of the surface of the first dielectric layer 60 in the second region II.
Specifically, the first gate structure includes: the first gate dielectric layer 71 is located on a part of the sidewall surface of the first channel pillar 40, and the first work function layer 72 is located on the surface of the first gate dielectric layer 71 and a part of the surface of the first dielectric layer 60 in the first region I.
The second gate structure includes: the second gate dielectric layer 73 is located on a part of the side wall surface of the second channel pillar 50, and the second work function layer 74 is located on the surface of the second gate dielectric layer 73 and a part of the surface of the first dielectric layer 60 in the second region II.
The material of the first work function layer 72 comprises titanium aluminide.
The material of the second work function layer 74 includes titanium nitride.
The first gate structure and the second gate structure further include a common gate electrode layer 70, the gate electrode layer 70 being located on the surface of the first work function layer 72, the surface of the second work function layer 74, a portion of the first dielectric layer 60 in the first region I, and a portion of the first dielectric layer 60 in the second region II.
In the above embodiment, the field effect transistor of the gate-all-around (GAA) structure is used as the channel region, so that the volume is increased, the operating current of the fin field effect transistor of the channel gate-around structure is further increased, and the performance of the semiconductor device is improved.
However, since the first work function layer 72 and the second work function layer 74 are connected in the structure of the CMOS device described above, when the CMOS device is heated at the time of subsequent formation of other devices or use, aluminum ions in the first work function layer 72 are easily thermally diffused into the second work function layer 74, and thus, the concentration of aluminum ions in the first work function layer 72 is lowered, so that the turn-on voltage of the first gate structure becomes large; meanwhile, the concentration of aluminum ions in the second work function layer 74 increases, so that the turn-on voltage of the second gate structure becomes large, resulting in deviation of the electrical performance of the CMOS device, that is, deterioration of the stability of the electrical performance of the CMOS device, and poor performance of the CMOS device.
To solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a first region, a second region, and a third region between the first and second regions, the third region having a first opening therein and a first channel pillar on a surface of the first region and a second channel pillar on a surface of the second region; a first isolation structure within the first opening, a top surface of the first isolation structure being higher than the substrate surface; a first work function layer located on the first channel pillar surface and the first isolation structure top surface; and a second work function layer positioned on the surface of the second channel column and the top surface of the first isolation structure. Thereby improving the performance of the semiconductor device.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 13 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate 100 is provided, the substrate 100 includes a first region I, a second region II, and a third region III between the first region I and the second region II, and a first channel pillar 110 is formed on a surface of the first region I, and a second channel pillar 120 is formed on a surface of the second region II.
The material of the substrate 100 is a semiconductor material.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, the substrate 100 includes: an initial first source-drain doped layer 101 located in the first region I and part of the third region III, and an initial second source-drain doped layer 102 located in the second region II and part of the third region III.
The initial first source-drain doped layer 101 has first ions therein, the initial second source-drain doped layer 102 has second ions therein, and the first ions and the second ions are different in conductivity type.
The initial first source-drain doped layer 101 is used for forming a first source-drain doped layer in the first region I later, and the initial second source-drain doped layer 102 is used for forming a second source-drain doped layer in the second region II later.
Specifically, in this embodiment, the surface of the substrate 100 in the first region I includes the surface of the first source-drain doped layer, and the surface of the substrate 100 in the second region II includes the surface of the second source-drain doped layer.
In this embodiment, the first ions are N-type ions and the second ions are P-type ions, so that an N-type device can be formed in the first region I and a P-type device can be formed in the second region II subsequently, and thus a CMOS device can be formed in the semiconductor structure.
In other embodiments, the first ion is a P-type ion and the second ion is an N-type ion.
The N-type ion comprises phosphorus ion, arsenic ion or antimony ion, and the P-type ion comprises boron ion, BF 2 -ions or indium ions.
In this embodiment, the process of forming the initial first source-drain doped layer 101 and the initial second source-drain doped layer 102 includes an epitaxial growth process.
In this embodiment, the materials of the first channel pillar 110 and the second channel pillar 120 are the same as the material of the substrate 100, and will not be described herein.
In this embodiment, the method of forming the first channel pillar 110 and the second channel pillar 120 includes: forming a channel pillar material layer (not shown) on the surface of the substrate 100; forming a second patterned layer 111 on a part of the surface of the channel pillar material layer in the first region I and a part of the surface of the channel pillar material layer in the second region II; and etching the channel column material layer by taking the second patterned layer 111 as a mask until the surface of the substrate 100 is exposed.
In this embodiment, the material of the second patterned layer 111 includes silicon nitride.
In other embodiments, the material of the second patterned layer includes silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
Referring to fig. 3, after forming the first channel pillar 110 and the second channel pillar 120, an initial first dielectric layer 130 is formed on the surface of the substrate 100.
The initial first dielectric layer 130 is used for forming a first dielectric layer later.
In this embodiment, the method for forming the initial first dielectric layer 130 includes: forming a first dielectric material layer (not shown) on the surface of the substrate 100; the first dielectric material layer is etched back until the initial first dielectric layer 130 is formed.
By etching back the first dielectric material layer, the thickness of the initial first dielectric layer 130 in the direction perpendicular to the substrate surface 100 is easier to control, so that a first dielectric layer with higher precision can be formed later.
In another embodiment, the initial first dielectric layer is formed directly on the surface of the substrate 100. Thus, steps and time of the semiconductor manufacturing process are reduced.
The process of forming the first dielectric material layer includes a deposition process.
In this embodiment, the deposition process is an atomic layer deposition process.
In other embodiments, the deposition process comprises a chemical vapor deposition process.
The process of etching back the first dielectric material layer comprises a dry etching process or a wet etching process.
In this embodiment, the process of etching back the first dielectric material layer includes a wet etching process.
In this embodiment, the material of the initial first dielectric layer 130 includes silicon oxide.
Referring to fig. 4, a first protective layer 141 is formed on the surface of the first channel pillar 110, the surface of the second channel pillar 120, the substrate 100 of the first region I, and the substrate 100 of the second region II.
The first protection layer 141, on the one hand, is used as a mask for subsequently forming the first opening, and on the other hand, is used for protecting the first channel pillar 110 and the second channel pillar 120, so as to reduce the influence of subsequent ion implantation, etching and other processes on the first channel pillar 110 and the second channel pillar 120, and improve the performance of the semiconductor device.
In this embodiment, the method of forming the first protective layer 141 includes: forming a first protective material layer (not shown) on the first channel pillar 110 surface, the second channel pillar 120 surface, and the substrate 100; forming a third patterned layer (not shown) on the surface of the first protective material layer, the third patterned layer exposing the first protective material layer of the third region III; and etching the first protective material layer by taking the third patterned layer as a mask until the surface of the initial first dielectric layer 130 of the third region III is exposed.
The process of forming the first protective material layer includes a deposition process.
In this embodiment, the process of forming the first protective material layer includes an atomic layer deposition process.
In other embodiments, the process of forming the first protective material layer includes a chemical vapor deposition process.
In this embodiment, the material of the first protection layer 141 includes silicon nitride.
In other embodiments, the material of the first protective layer includes silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
Referring to fig. 5, a first opening 140 is formed in the third region III.
The first opening 140 is used to provide space for a first isolation structure to be formed later.
The method of forming the first opening 140 includes: and etching the initial first dielectric layer 130 of the third region III and the substrate 100 of the third region III with the first protective layer 141 as a mask until the first opening 140 is formed.
Thus, by removing the initial first dielectric layer 130 of the third region III, the first dielectric layer 131 is formed on the surfaces of the first region I and the second region II.
The first dielectric layer 131 can insulate between the first channel pillar 110 and the second channel pillar 120, and insulate between the subsequently formed first work function layer, second work function layer, and gate electrode layer and the substrate 100 to form a CMOS device in the semiconductor structure.
The process of etching the initial first dielectric layer 130 of the third region III includes: a dry etching process or a wet etching process.
The process of etching the substrate 100 of the third region III includes: a dry etching process or a wet etching process.
In this embodiment, the process of etching the substrate 100 of the third region III includes a dry etching process, and the process parameters of the dry etching process include: the gas comprising CF 4 、H 2 、CH 3 F and He, where CF 4 The flow range of (2) is 30-200 ml/min, H 2 The flow rate of the catalyst is in the range of 20-500 standard milliliters/minute, CH 3 F flow rate ranges from 60 to 800 standard milliliters/min, and He flow rate ranges from 60 to 200 standard milliliters/min.
In this embodiment, in a direction perpendicular to the surface of the substrate 100, the initial first source-drain doped layer 101 has a first thickness H1, the initial second source-drain doped layer 102 has a second thickness H2, a distance between the bottom surface of the first opening 140 and the surface of the substrate 100 is a third distance H3, and the third distance H3 is greater than the first thickness H1, and the third distance H3 is greater than the second thickness H2. Thus, the initial first source-drain doped layer 101 and the initial second source-drain doped layer 102 in the third region III are removed at the same time as the first opening 140 is formed. Thus, by removing the initial first source drain doped layer 101 in the third region III, a first source drain doped layer 103 is formed in said first region I, and by removing the initial second source drain doped layer 102 in the third region III, a second source drain doped layer 104 is formed in said second region II.
Since the first source-drain doped layer 103 is formed by using the initial first source-drain doped layer 101 as a material and the second source-drain doped layer 104 is formed by using the initial second source-drain doped layer 102 as a material, the first source-drain doped layer 103 has first ions therein, the second source-drain doped layer 104 has second ions therein, and the conductivity types of the first ions and the second ions are different.
In this embodiment, after the first opening 140 is formed, a first isolation structure is formed in the first opening 140, and a top surface of the first isolation structure is higher than a surface of the substrate 100, specifically please refer to fig. 6 to 7.
Referring to fig. 6, a first isolation structure material layer 142 is formed on the surface of the first protection layer 141 in the first opening 140; the first isolation structure material layer 142 of the third region III is subjected to a modification treatment.
By the modification treatment, the etchant can have different etching ratios to the first isolation structure material layer 142 in the third region III and the first isolation structure material layer 142 in the first region I and the second region II when the first isolation structure material layer 142 is etched back later, so that the speed of etching the first isolation structure material layer 142 in the first region I and the second region II is greater than the speed of etching the first isolation structure material layer 142 in the third region III to form the first isolation structure later.
In this embodiment, the material of the first isolation structure material layer 142 includes silicon oxide.
In other embodiments, the material of the first isolation structure material layer includes silicon oxynitride or silicon oxycarbonitride.
In this embodiment, the method for modifying the first isolation structure material layer 142 of the third region III includes: forming a first patterned layer 143 on the surface of the first isolation structure material layer 142, where the first patterned layer 143 exposes the first isolation structure material layer 142 of the third region III; and performing an ion implantation process on the first isolation structure material layer 142 by using the first patterned layer 143 as a mask.
In this embodiment, the process parameters of the ion implantation process include: the implanted ion species are silicon ions; the energy range of ion implantation is 1 KeV-30 KeV; the ion implantation dose range was 1e14atm/cm 2 ～2e16atm/cm 2 。
In this embodiment, after the ion implantation process, the first patterned layer 143 is removed.
Referring to fig. 7, after the modification process, the first isolation structure material layer 142 is etched back until the first protection layer 131 on the surface of the substrate 100 is exposed, so as to form a first isolation structure 144.
The process of etching back the first isolation structure material layer 142 includes a dry etching process or a wet etching process.
In this embodiment, the process of etching back the first isolation structure material layer 142 includes a dry etching process, and the process parameters of the dry etching process include: the gas comprising CF 4 、N 2 And O 2 Wherein CF is as follows 4 The flow rate of the catalyst is in the range of 8-200 standard milliliters/minute, N 2 The flow rate of the catalyst is in the range of 100-400 standard milliliters/minute, O 2 The flow range of (2) is 10-200 standard milliliters/minute; the pressure ranges from 5 millitorr to 200 millitorr.
In this embodiment, the material of the first isolation structure 144 includes silicon oxide.
In another embodiment, the material of the first isolation structure is boron doped silicon oxide.
In other embodiments, the material of the first isolation structure includes silicon oxynitride or silicon oxycarbonitride.
In this embodiment, in the direction perpendicular to the surface of the substrate 100, the distance H4 between the top surface of the first isolation structure 144 and the surface of the first dielectric layer 131 ranges from 3 nm to 20 nm.
The excessive spacing H4 results in a structure with a large depth-to-width ratio between the first isolation structure 144 and the first trench pillar 110 and between the first isolation structure 144 and the second trench pillar 120, which increases the difficulty of the subsequent deposition process and is not beneficial to the subsequent formation of the first work function layer and the second work function layer with good morphology; the spacing H4 is too small, and after the first work function layer and the second work function layer are formed subsequently, the length of the diffusion path of the ions in the increased first work function layer or the ions in the second work function layer is limited, which is not beneficial to reducing the variation of the ion concentration in the first work function layer on the first channel pillar 110 and the variation of the ion concentration in the second work function layer on the second channel pillar 120. In summary, when the pitch H4 ranges from 3 nm to 20 nm, on one hand, a structure with a smaller aspect ratio is formed between the first isolation structure 144 and the first channel pillar 110 and between the first isolation structure 144 and the second channel pillar 120, so as to be beneficial to forming a first work function layer and a second work function layer with good morphology, and on the other hand, the length of the diffusion path of the ions in the first work function layer or the ions in the second work function layer can be increased more, so that the variation of the ion concentration in the first work function layer on the first channel pillar 110 and the variation of the ion concentration in the second work function layer on the second channel pillar 120 can be reduced better.
In this embodiment, after the first isolation structure 144 is formed, the second patterned layer 111 and the first protective layer 141 are removed.
The process of removing the second patterned layer 111 and the first protective layer 141 includes a dry etching process or a wet etching process.
In this embodiment, the process of removing the second patterned layer 111 and the first protection layer 141 includes a wet etching process, and the etching solution of the wet etching process is hot phosphoric acid, so that during the process of etching the second patterned layer 111 and the first protection layer 141, the materials of the second patterned layer 111 and the first protection layer 141 have a larger selective etching ratio to the materials of the first channel pillar 110, and the materials of the second patterned layer 111 and the first protection layer 141 have a larger selective etching ratio to the materials of the second channel pillar 120, thereby reducing the influence of the wet etching process to the first channel pillar 110 and the second channel pillar 120.
In this embodiment, a first work function layer is formed on the first channel pillar 110 and the surface of the first isolation structure 144, and a second work function layer is formed on the second channel pillar 120 and the surface of the first isolation structure 144.
Since the first work function layer and the second work function layer are formed on the top surface of the first isolation structure 144, that is, the junction between the first work function layer and the second work function layer is located on the top surface of the first isolation structure 144, the length of the diffusion path of the ions in the first work function layer or the ions in the second work function layer is increased, so that the number of the ions in the first work function layer on the first channel pillar 110 or the ions in the second work function layer on the second channel pillar 120 diffusing to each other is reduced, that is, the variation of the ion concentration in the first work function layer on the first channel pillar 110 and the variation of the ion concentration in the second work function layer on the second channel pillar 120 are reduced, thereby reducing the variation of the opening voltage of the semiconductor device, reducing the deviation of the electrical performance of the semiconductor device, improving the stability of the electrical performance of the semiconductor device, and improving the performance of the semiconductor device.
In this embodiment, before forming the first work function layer and the second work function layer, a first gate dielectric layer is formed on the surface of the first channel pillar 110, and a second gate dielectric layer is formed on the surface of the second channel pillar 120; and forming a gate electrode layer on the surface of the first work function layer and the surface of the second work function layer. The steps of forming the first work function layer, the second work function layer, the first gate dielectric layer, the second gate dielectric layer and the gate electrode layer are specifically shown in fig. 8 to 12.
Referring to fig. 8, an initial first gate dielectric layer 161 is formed on the surface of the first channel pillar 110, and an initial second gate dielectric layer 171 is formed on the surface of the second channel pillar 120.
The initial first gate dielectric layer 161 is used for forming a first gate dielectric layer subsequently, and the initial second gate dielectric layer 171 is used for forming a second gate dielectric layer subsequently.
In this embodiment, the process of forming the initial first gate dielectric layer 161 includes a thermal oxidation process.
In this embodiment, the process of forming the initial second gate dielectric layer 171 includes a thermal oxidation process.
The technological parameters of the thermal oxidation process comprise: the temperature range is 800-1050 ℃; the gas comprises oxygen and nitrogen, wherein the flow rate of the oxygen ranges from 50 standard milliliters/minute to 2000 standard milliliters/minute, and the flow rate of the nitrogen ranges from 300 standard milliliters/minute to 8000 standard milliliters/minute.
In this embodiment, the material of the initial first gate dielectric layer 161 includes a combination of silicon oxide and a high dielectric constant material.
Therefore, a better interface state can be provided between the initial first gate dielectric layer 161 and the first channel pillar 110 through silicon oxide, and meanwhile, the insulation property (dielectric constant is higher) of the initial first gate dielectric layer 161 can be better through the high dielectric constant material.
In other embodiments, the material of the initial first gate dielectric layer 161 includes silicon oxide.
In this embodiment, the material of the initial second gate dielectric layer 171 includes a combination of silicon oxide and a high dielectric constant material.
Thus, a better interface state between the initial second gate dielectric layer 171 and the second channel pillar 120 can be provided by the silicon oxide, and meanwhile, the insulation property (dielectric constant) of the initial first gate dielectric layer 161 can be better (dielectric constant is higher) by the high dielectric constant material.
In other embodiments, the material of the initial second gate dielectric layer 171 includes silicon oxide.
The material with high dielectric constant is a material with dielectric constant greater than 3.9.
The high dielectric constant material comprises titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide, lanthanum oxide and the like.
In this embodiment, the high dielectric constant material comprises hafnium oxide.
Referring to fig. 9, an initial second work function layer 172 is formed on the surface of the initial second gate dielectric layer 171, the second region II, and the surface of the first isolation structure 144.
In this embodiment, the method of forming the initial second work function layer 172 includes: forming an initial second work function material layer (not shown) on the substrate 100, on the surface of the first isolation structure 144, on the surface of the initial first gate dielectric layer 161, and on the surface of the initial second gate dielectric layer 171; forming a fourth patterned layer (not shown) on the surface of the initial second work function material layer on the second region II and a portion of the surface of the first isolation structure 144; and etching the initial second work function material layer by taking the fourth patterned layer as a mask until the surface of the first dielectric layer 131 of the first region I and part of the surface of the first isolation structure 144 are exposed.
In this embodiment, the material of the initial second work function layer 172 includes titanium nitride or tantalum nitride.
In another embodiment, the material of the initial second work function layer comprises titanium aluminide.
The process of forming the initial second work function material layer includes a deposition process.
In this embodiment, the deposition process is an atomic layer deposition process, and the process parameters of the atomic layer deposition process include: the reaction gas comprises nitrogen-containing substances and precursors of titanium-containing substances, the temperature range is 200-650 ℃, and the pressure range is 1-200 millitorr.
In other embodiments, the deposition process comprises a chemical vapor deposition process.
The process of etching the initial second work function material layer includes a dry etching process or a wet etching process.
In this embodiment, the process of etching the initial second work function material layer includes a dry etching process, and process parameters of the dry etching process include: the gas comprising SF 6 And Cl 2 Wherein SF is 6 The flow rate of (C) is in the range of 20-300 standard milliliters/minute, and Cl 2 The flow rate range of (1) is 60 standard milliliters/min-150 standardQuasi milliliters per minute; the pressure ranges from 2 millitorr to 200 millitorr.
In this embodiment, after the initial second work function layer 172 is formed, the fourth patterned layer is removed.
Referring to fig. 10, an initial first work function layer 162 is formed on the surface of the initial first gate dielectric layer 161, the first region I, and the surface of the first isolation structure 144.
In this embodiment, the method of forming the initial first work function layer 162 includes: an initial first work function material layer (not shown) is formed on the substrate 100, on the surface of the first isolation structures 144, on the surface of the initial first gate dielectric layer 161, and on the surface of the initial second work function layer 172.
In this embodiment, the method of forming the initial first work function layer 162 further includes: forming a fifth patterned layer (not shown) on the first region I and the initial first work function material layer surface of a portion of the first isolation structure 144 surface; and etching the initial first work function material layer by taking the fifth patterned layer as a mask until the surface of the initial second work function layer 172 and part of the surface of the first isolation structure 144 are exposed.
In another embodiment, the initial second work function layer is formed after the initial first work function layer is formed.
In yet another embodiment, the initial second work function layer includes a fourth region in a direction perpendicular to the substrate surface, and a fifth region located on the fourth region; and before the initial first work function material layer is formed, carrying out modification treatment on the initial second work function layer of the fifth region to form a fifth isolation region, and after the initial first work function material layer is formed, etching the initial first work function material layer without taking the fifth patterned layer as a mask, namely, removing the initial first work function material layer on the surface of the initial second work function layer.
On the one hand, even if the initial first work function material layer on the surface of the initial second work function layer is not removed, since the fifth isolation region is formed, ions of the initial first work function material layer or the initial second work function layer 172 can be reduced through the fifth isolation region when the temperature of the subsequent manufacturing process is high, and diffused toward each other through the top surface of the initial second work function layer, thereby reducing the variation of ion concentration in the subsequently formed second work function layer, reducing the variation of the turn-on voltage of the semiconductor device, that is, reducing the deviation of the electrical properties of the semiconductor device, so that the stability of the electrical properties of the semiconductor device is improved, and the performance of the semiconductor device is improved. On the other hand, since the modification treatment is performed on the fifth region, the portion of the initial second work function layer to be modified is small, and thus, the modification treatment has less influence on the electrical properties such as the turn-on voltage of the second work function layer to be formed later.
In this embodiment, the material of the initial first work function layer 162 comprises titanium aluminide.
In another embodiment, the material of the initial first work function layer comprises titanium nitride or tantalum nitride.
The process of forming the initial first work function material layer includes a deposition process.
In this embodiment, the deposition process is an atomic layer deposition process, and the process parameters of the atomic layer deposition process include: the reaction gas comprises precursors containing aluminum and titanium, the temperature range is 250-650 ℃, and the pressure is 5-200 mTorr.
In other embodiments, the deposition process comprises a chemical vapor deposition process.
The process of etching the initial first work function material layer includes a dry etching process or a wet etching process.
In this embodiment, the process of etching the initial first work function material layer includes a dry etching process, and process parameters of the dry etching process include: the gas comprising SF 6 、Cl 2 And CF (compact F) 4 Wherein SF is 6 The flow rate of (C) is in the range of 30-300 standard milliliters/minute, and Cl 2 The flow rate of the catalyst is in the range of 60-150 standard milliliters/minute, CF 4 The flow range of (2) is 10-600 standard milliliters/minute; pressure intensityRanging from 2 millitorr to 200 millitorr.
In this embodiment, after the initial first work function layer 162 is formed, the fifth patterned layer is removed.
Referring to fig. 11, a gate electrode material layer 190 is formed on the surface of the initial first work function layer 162 and the surface of the initial second work function layer 172.
The gate electrode material layer 190 is used for the subsequent formation of a gate electrode layer.
In this embodiment, the material of the gate electrode material layer 190 includes a metal material, such as one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the process of forming the gate electrode material layer includes an atomic layer deposition process or a chemical vapor deposition process.
Referring to fig. 12, the gate electrode material layer 190 on top of the first channel pillar 110 and on top of the second channel pillar 120 is etched to form a gate electrode layer 191; after forming the gate electrode layer 191, the exposed surface of the initial first work function layer 162, the initial second work function layer 172, the initial first gate dielectric layer 161, and the initial second gate dielectric layer 171 are etched.
Accordingly, a first gate dielectric layer 163 is formed on the sidewall surface of the first channel pillar 110, a second gate dielectric layer 173 is formed on the sidewall surface of the second channel pillar 120, a first work function layer 164 is formed on the surface of the first gate dielectric layer 163 and the surface of the first isolation structure 144, a second work function layer 174 is formed on the surface of the second gate dielectric layer 173 and the surface of the first isolation structure 144, and a gate electrode layer 191 is formed on the surface of the first work function layer 164 and the surface of the second work function layer 174.
In this embodiment, the method of forming the gate electrode layer 191 includes: forming a sixth patterned layer (not shown) on the surface of the gate electrode material layer 190, the sixth patterned layer exposing the gate electrode material layer 190 on top of the first channel pillar 110 and on top of the second channel pillar 120; the gate electrode material layer 190 is etched using the sixth patterned layer as a mask until the initial first work function layer 162 surface and the initial second work function layer 172 are exposed.
In this embodiment, the sixth patterned layer also exposes a portion of the gate electrode material layer 190 on the sidewalls of the first channel pillar 110, a portion of the sidewalls of the second channel pillar 120, a portion of the first region I substrate 100, and a portion of the second region II substrate 100.
In another embodiment, the sixth patterned layer does not expose the gate electrode material layer on the sidewalls of the first channel pillar 110 and on the sidewalls of the second channel pillar 120.
The process of etching the gate electrode material layer 190 includes a dry etching process or a wet etching process.
In this embodiment, the process of etching the gate electrode material layer 190 includes a dry etching process.
Referring to fig. 13, after forming the first gate dielectric layer 163 and the second gate dielectric layer 173, a first plug 201 is formed on the top surface of the first channel pillar 110, a second plug 202 is formed on the surface of the first source/drain doped layer 101 in the first region I, a third plug 201 is formed on the top surface of the second channel pillar 120, a fourth plug 204 is formed on the surface of the second source/drain doped layer 102 in the second region II, a fifth plug 205 is formed on the surface of the gate electrode layer 191, and a second dielectric layer 210 surrounding the gate electrode layer 191, the first channel pillar 110, the second channel pillar 120, the first plug 201, the second plug 202, the third plug 203, the fourth plug 204, and the fifth plug 205 is formed on the surface of the first dielectric layer 131.
In this embodiment, the materials of the first plug 201, the second plug 202, the third plug 203, the fourth plug 204 and the fifth plug 205 include metal materials, such as one or more of tungsten, cobalt, copper, nickel, titanium and titanium nitride.
In this embodiment, the material of the second dielectric layer 210 includes silicon oxide.
Accordingly, in an embodiment of the present invention, a semiconductor structure is further provided, please continue to refer to fig. 13, which includes: a substrate 100, the substrate 100 comprising a first region I, a second region II, and a third region III between the first region I and the second region II, the third region III having a first opening 140 (as shown in fig. 5) therein, and having a first channel pillar 110 on a surface of the first region I, and a second channel pillar 120 on a surface of the second region II; a first isolation structure 144 located within the first opening 140, a top surface of the first isolation structure 144 being higher than the surface of the substrate 100; a first work function layer 164 located on the surface of the first channel pillar 110 and the top surface of the first isolation structure 144; a second work function layer 174 located on the surface of the second channel pillar 120 and the top surface of the first isolation structure 144.
Because the first work function layer 164 and the second work function layer 174 are located on the top surface of the first isolation structure 144, that is, the connection between the first work function layer 164 and the second work function layer 174 is located on the top surface of the first isolation structure 144, the length of the diffusion path of the ions in the first work function layer 164 or the ions in the second work function layer 174 is increased, so that the number of the ions in the first work function layer 164 on the first channel pillar 110 or the ions in the second work function layer 174 on the second channel pillar 120 diffusing to each other is reduced, that is, the variation of the ion concentration in the first work function layer 164 on the first channel pillar 110 and the variation of the ion concentration in the second work function layer 174 on the second channel pillar 120 is reduced, thereby reducing the variation of the turn-on voltage of the semiconductor device, reducing the deviation of the electrical performance of the semiconductor device, so that the stability of the electrical performance of the semiconductor device is improved, and the performance of the semiconductor device is improved.
In yet another embodiment, the second work function layer includes a fourth region and a fifth isolation region on the fourth region in a direction perpendicular to the substrate surface, and a portion of the first work function layer is also on the second work function layer surface.
On the one hand, since there is the fifth isolation region, even if a part of the first work function layer is still located on the surface of the second work function layer, ions of the first work function layer or the second work function layer can diffuse toward each other through the fifth isolation region and through the top surface of the second work function layer, thereby reducing the variation of ion concentration in the first work function layer and the second work function layer, reducing the variation of the turn-on voltage of the semiconductor device, that is, reducing the deviation of the electrical properties of the semiconductor device, so that the stability of the electrical properties of the semiconductor device is improved, and the performance of the semiconductor device is improved. On the other hand, since only part of the second work function layer has the fifth isolation region in the direction perpendicular to the surface of the second work function layer, the second work function layer near the second channel pillar is not modified, and therefore, the fifth isolation region has less influence on the electrical properties such as the turn-on voltage of the second work function layer.
The material of the substrate 100 is a semiconductor material.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, the substrate 100 includes: a first source-drain doped layer 103 located in the first region I, and a second source-drain doped layer 104 located in the second region II.
The first source-drain doped layer 103 has first ions therein, the second source-drain doped layer 104 has second ions therein, and the first ions and the second ions are different in conductivity type.
Specifically, in this embodiment, the surface of the substrate 100 in the first region I includes the surface of the first source-drain doped layer 103, and the surface of the substrate 100 in the second region II includes the surface of the second source-drain doped layer 104.
In this embodiment, the first ion is an N-type ion, and the second ion is a P-type ion.
In other embodiments, the first ion is a P-type ion and the second ion is an N-type ion.
The N-type ion comprises phosphorus ion, arsenic ion or antimony ion, and the P-type ion comprises boron ion, BF 2- Ions or indium ions.
In this embodiment, the material of the first work function layer 164 includes titanium aluminide.
In another embodiment, the material of the first work function layer comprises titanium nitride or tantalum nitride.
In this embodiment, the material of the second work function layer 174 includes titanium nitride or tantalum nitride.
In another embodiment, the material of the second work function layer comprises titanium aluminide.
In this embodiment, the material of the first isolation structure 144 includes silicon oxide.
In another embodiment, the material of the first isolation structure is boron doped silicon oxide.
In other embodiments, the material of the first isolation structure is silicon oxynitride or silicon oxycarbonitride.
In this embodiment, the semiconductor structure further includes: a first dielectric layer 131 is located on the surface of the substrate 100.
In this embodiment, the material of the first dielectric layer 131 includes silicon oxide.
In this embodiment, the semiconductor structure further includes: a first gate dielectric layer 163 located between the sidewall surface of the first channel pillar 110 and the first work function layer 164, a second gate dielectric layer 173 located between the sidewall surface of the second channel pillar 120 and the second work function layer 174, and a gate electrode layer 191 located on the surface of the first work function layer 164 and the surface of the second work function layer 174.
In this embodiment, the material of the first gate dielectric layer 163 includes a combination of silicon oxide and a high dielectric constant material.
In other embodiments, the material of the first gate dielectric layer 163 includes silicon oxide.
In this embodiment, the material of the second gate dielectric layer 173 includes a combination of silicon oxide and a high-k material.
In other embodiments, the material of the second gate dielectric layer 173 includes silicon oxide.
The material with high dielectric constant is a material with dielectric constant greater than 3.9.
The high dielectric constant material comprises titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide, lanthanum oxide and the like.
In this embodiment, the high dielectric constant material comprises hafnium oxide.
In this embodiment, the material of the gate electrode layer 191 includes a metal material, such as one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, in the direction perpendicular to the surface of the substrate 100, the distance H4 (as shown in fig. 7) between the top surface of the first isolation structure 144 and the surface of the first dielectric layer 131 ranges from 3 nm to 20 nm.
The excessive spacing H4 results in a structure with a large depth-to-width ratio between the first isolation structure 144 and the first trench pillar 110 and between the first isolation structure 144 and the second trench pillar 120, which increases the difficulty of the deposition process and is not beneficial to forming a first work function layer and a second work function layer with good morphology; the spacing H4 is too small, and the length of the diffusion path of the ions in the increased first work function layer or the ions in the second work function layer is limited, which is disadvantageous in reducing the variation of the ion concentration in the first work function layer on the first channel pillar 110 and in reducing the variation of the ion concentration in the second work function layer on the second channel pillar 120. In summary, when the pitch H4 ranges from 3 nm to 20 nm, on one hand, a structure with a smaller aspect ratio is formed between the first isolation structure 144 and the first channel pillar 110 and between the first isolation structure 144 and the second channel pillar 120, so as to be beneficial to forming a first work function layer and a second work function layer with good morphology, and on the other hand, the length of the diffusion path of the ions in the first work function layer or the ions in the second work function layer can be increased more, so that the variation of the ion concentration in the first work function layer on the first channel pillar 110 and the variation of the ion concentration in the second work function layer on the second channel pillar 120 can be reduced better.
In this embodiment, the semiconductor structure further includes: a first plug 201 located on the top surface of the first channel pillar 110, a second plug 202 located on the surface of the first source/drain doped layer 101 in the first region I, a third plug 201 located on the top surface of the second channel pillar 120, a fourth plug 204 located on the surface of the second source/drain doped layer 102 in the second region II, a fifth plug 205 located on the surface of the gate electrode layer 191 in the third region, and a second dielectric layer 210 located on the surface of the first dielectric layer 131 and surrounding the gate electrode layer 191, the first channel pillar 110, the second channel pillar 120, the first plug 201, the second plug 202, the third plug 203, the fourth plug 204, and the fifth plug 205.
In this embodiment, the materials of the first plug 201, the second plug 202, the third plug 203, the fourth plug 204 and the fifth plug 205 include metal materials, such as one or more of tungsten, cobalt, copper, nickel, titanium and titanium nitride.
In this embodiment, the material of the second dielectric layer 210 includes silicon oxide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region, a second region and a third region positioned between the first region and the second region, a first channel column is formed on the surface of the first region, a second channel column is formed on the surface of the second region, and a first opening is formed in the third region;
forming a first isolation structure in the first opening, wherein the top surface of the first isolation structure is higher than the surface of the substrate;
forming a first work function layer on the surface of the first channel column and the surface of the first isolation structure;
forming a second work function layer on the surface of the second channel column and the surface of the first isolation structure;
wherein a junction between the first work function layer and the second work function layer is located on a top surface of the first isolation structure; the first isolation structure is used for increasing the length of a diffusion path of ions in the first work function layer or ions in the second work function layer;
the method for forming the first opening comprises the following steps: forming a first protection layer on the first channel column surface, the second channel column surface, the substrate of the first region and the substrate of the second region; etching the substrate of the third region by taking the first protective layer as a mask;
The method for forming the first isolation structure comprises the following steps: forming a first isolation structure material layer in the first opening and on the surface of the first protective layer; modifying the first isolation structure material layer of the third region; and after the modification treatment, etching the first isolation structure material layer until the first protective layer on the surface of the substrate is exposed.
2. The method of forming a semiconductor structure of claim 1, wherein modifying the first isolation structure material layer of the third region comprises: forming a first patterned layer on the surface of the first isolation structure material layer, wherein the first patterned layer exposes the first isolation structure material layer of the third region; and taking the first graphical layer as a mask, and performing an ion implantation process on the first isolation structure material layer.
3. The method of forming a semiconductor structure of claim 2, wherein the process parameters of the ion implantation process comprise: the implanted ion species are silicon ions; the energy range of ion implantation is 1 KeV-30 KeV; the ion implantation dose range was 1e14atm/cm 2 ~2e16 atm/cm 2 。
4. The method of forming a semiconductor structure of claim 1, wherein the material of the first protective layer comprises silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
5. The method of forming a semiconductor structure of claim 1, further comprising: and forming a first gate dielectric layer between the first work function layer and the surface of the first channel column, and forming a second gate dielectric layer between the second work function layer and the surface of the second channel column.
6. The method of forming a semiconductor structure of claim 1, further comprising: and forming a gate electrode layer on the surface of the first work function layer and the surface of the second work function layer.
7. The method of forming a semiconductor structure of claim 1, further comprising: and forming a first dielectric layer on the surface of the first region and the surface of the second region before forming the first isolation structure.
8. The method of forming a semiconductor structure of claim 1, wherein the material of the first isolation structure comprises silicon oxide, silicon oxynitride, or silicon oxycarbonitride.
9. The method of forming a semiconductor structure of claim 5, wherein the material of the first gate dielectric layer comprises a combination of silicon oxide and a high dielectric constant material; the material of the second gate dielectric layer comprises a combination of silicon oxide and a high dielectric constant material.
10. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: a first source-drain doped layer located in the first region, wherein first ions are located in the first source-drain doped layer; and a second source-drain doped layer positioned in the second region, wherein second ions are arranged in the second source-drain doped layer, and the conductivity types of the first ions and the second ions are different.
11. The method of claim 10, wherein the first ions are N-type ions including phosphorus ions, arsenic ions, or antimony ions; the second ion is a P-type ion, and the P-type ion comprises boron ion and BF 2- Ions or indium ions.
12. The method of forming a semiconductor structure of claim 1, further comprising: and forming a first dielectric layer on the surface of the first region and the surface of the second region.
13. The method of claim 7 or 12, wherein a spacing between a top surface of the first isolation structure and a surface of the first dielectric layer in a direction perpendicular to the substrate surface is in a range of 3 nm to 20 nm.
14. A semiconductor structure formed by the method of forming a semiconductor structure according to any one of claims 1 to 13.
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| CN107492551A (en) * | 2016-06-12 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
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