CN113327923B - Heterojunction semiconductor device with electrostatic discharge self-protection function - Google Patents
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- CN113327923B CN113327923B CN202110598471.7A CN202110598471A CN113327923B CN 113327923 B CN113327923 B CN 113327923B CN 202110598471 A CN202110598471 A CN 202110598471A CN 113327923 B CN113327923 B CN 113327923B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 3
- JUWSSMXCCAMYGX-UHFFFAOYSA-N gold platinum Chemical compound [Pt].[Au] JUWSSMXCCAMYGX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 230000003068 static effect Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 6
- 238000010030 laminating Methods 0.000 abstract description 2
- 230000001052 transient effect Effects 0.000 abstract 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 7
- 229910002601 GaN Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000007599 discharging Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- FFEARJCKVFRZRR-UHFFFAOYSA-N methionine Chemical compound CSCCC(N)C(O)=O FFEARJCKVFRZRR-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to a heterojunction semiconductor device with electrostatic discharge self-protection, which comprises: a buffer layer, a channel layer, a heterojunction channel and a barrier layer; the upper surface of the barrier layer is provided with a metal drain electrode and a metal source electrode; a gate protection region formed by alternately forming a first p-type semiconductor layer, a first n-type semiconductor layer and a second p-type semiconductor layer is arranged between the metal drain electrode and the metal source electrode and close to the metal source electrode at intervals, and a gate control region formed by laminating a third p-type semiconductor layer and the metal gate electrode is arranged between the metal drain electrode and the metal source electrode; the gate protection region a and the gate control region b are isolated by a high-resistance dielectric layer; the gate protection region provides an ESD current bleed channel protecting the gate from transient high current. Compared with the traditional external ESD protection circuit, the invention has the advantages of high integration level, small occupied area, small parasitic capacitance and the like.
Description
Technical Field
The invention belongs to the field of reliability research of power electronics and semiconductor devices, and particularly relates to a heterojunction semiconductor device with an electrostatic protection function by integrating a bidirectional diode between a grid electrode and a source electrode of the device.
Background
During the last decades, the first generation of semiconductor materials, represented by silicon, has supported a high-speed development of the electronic information society, and as technology advances, silicon-based devices have been studied close to their theoretical limit. Currently, through the development of second generation semiconductors such as gallium arsenide (GaAs), indium antimonide (InSb), etc., third generation semiconductors such as silicon carbide (SiC), gallium nitride (GaN), etc., are being developed and applied in large quantities with their superior characteristics. The third-generation semiconductor gallium nitride is a wide-bandgap semiconductor, has the advantages of high heat conductivity, high temperature resistance, radiation resistance, acid and alkali resistance, high strength, high hardness and the like, and is a hot spot in the research direction of semiconductor materials in the world at present. Gallium nitride as a novel semiconductor material has wide prospect in the application fields of photoelectrons, high-temperature high-power devices and high-frequency microwave devices. Gallium nitride high electron mobility transistor (GaN high-electron-mobility transistor, gaN HMET) devices have the advantages of low on-resistance, high working frequency, high conversion efficiency, low parasitic capacitance and the like because a heterojunction channel formed by a barrier layer and a channel layer of the GaN high electron mobility transistor has extremely high electron mobility; currently, gaN HMET devices are also used as core switching components in many power system circuits, and the corresponding reliability is also continually improved in product update iterations.
Nevertheless, there are still some reliability issues that are of concern. Among them, electrostatic discharge (ESD) is a common phenomenon in life, and for a semiconductor device, electrostatic charges accumulated on a human body or metal contact pins of a chip, a very large instantaneous current or voltage spike is generated in a very short time (several tens to several hundreds of nanoseconds) enough to burn the device to permanently fail the device. Although the gallium nitride heterojunction device has a very high breakdown electric field, the special device structure does not have PN structure in the interior to assist in discharging charge energy impact, so that the traditional enhanced heterojunction semiconductor device is usually connected with an ESD protection branch outside the device in parallel to improve the overall ESD impact resistance, and the commonly used ESD protection branch mainly comprises a diode, a triode (Bipolar JunctionTransistor, BJT), a grid Grounded NMOS (GGMOS), a silicon controlled device (Silicon Controlled Rectifier, SCR) and the like. However, these methods have the disadvantages of low integration level, complex circuit design, large parasitic capacitance, large occupied area and high cost. Therefore, from the perspective of improving the system integration level and the robustness of the device, the method has important significance for improving the self antistatic impact capability of the device.
Disclosure of Invention
Technical problems: ESD is one of the primary factors affecting the reliability of the device, and electrostatic charges accumulated on a human body or metal contact pins of the chip, so that a great instantaneous current or voltage spike is generated in a very short time, which is enough to burn out the device and permanently disable the device. The invention aims at the problems and provides a heterojunction semiconductor device with electrostatic discharge self-protection.
The technical scheme is as follows: the invention adopts a heterojunction semiconductor device with electrostatic discharge self-protection, which is sequentially provided with a buffer layer, a channel layer and a barrier layer from bottom to top; the channel layer is contacted with the barrier layer to form a heterojunction channel; one side of the upper surface of the barrier layer is provided with a metal drain electrode, and the other opposite side is provided with a metal source electrode; the gate protection region is arranged between the metal drain electrode and the metal source electrode and is close to the metal source electrode in sequence and consists of a first p-type semiconductor layer, a first n-type semiconductor layer and a second p-type semiconductor layer; the third p-type semiconductor layer and the first p-type semiconductor layer are coaxial in the length direction, the metal gate electrode is positioned above the third p-type semiconductor layer and the first p-type semiconductor layer, and the third p-type semiconductor layer and the metal gate electrode are laminated to form a gate control region; the gate protection area and the gate control area are isolated by a high-resistance dielectric layer; the metal source electrode is in direct contact with the second p-type semiconductor layer in the gate protection region; the metal gate electrode is simultaneously in direct contact with the first p-type semiconductor layer in the gate protection region, the high-resistance dielectric layer and the third p-type semiconductor layer in the gate control region.
The first n-type semiconductor layer is lightly doped, and the doping concentration of the second p-type semiconductor layer is higher than that of the first p-type semiconductor layer; the first p-type semiconductor layer and the second p-type semiconductor layer are designed to be thicker than the first n-type semiconductor layer.
The thickness of the first n-type semiconductor layer is 10nm-100nm.
The gate protection regions are of alternating combination structures formed by sequentially contacting a plurality of first p-type semiconductor layers, first n-type semiconductor layers and second p-type semiconductor layers, and the gate protection regions can be distributed at intervals along the extending direction of the metal source electrode.
The gate protection region alternating combination structure is replaced by a high-resistance region, and a plurality of high-resistance regions can be distributed at intervals along the extending direction of the metal source electrode.
The metal gate electrode forms ohmic contact with the first p-type semiconductor layer in the gate protection region and forms Schottky contact with the third p-type semiconductor layer in the gate control region; the metal drain electrode and the metal source electrode form ohmic contact with the barrier layer.
The metal gate electrode is one or more of nickel, platinum, nickel gold or platinum gold.
The metal drain electrode and the metal source electrode are one or a plurality of combinations of titanium, aluminum, platinum, gold or nickel.
The beneficial effects are that: the device integrates an ESD protection circuit inside, and can effectively protect the grid electrode and the source electrode simultaneously by doping between the grid electrode and the source electrode to form an alternate combined structure as an electrostatic discharge passage. The working principle is as follows: when the device works normally, the grid electrode is opened, the device is conducted, the conducting voltage is insufficient for opening the electrostatic discharge passage, and the electrostatic discharge passage is equivalent to open circuit, so that the normal work of the device is not influenced; when the grid electrode of the device is subjected to electrostatic impact, a pn junction formed by the first p-type semiconductor layer and the first n-type semiconductor layer below the metal grid electrode is conducted in the forward direction, the instant large voltage enables the pn junction formed by the first n-type semiconductor layer and the second p-type semiconductor layer to be broken down in the reverse direction, the on-resistance is rapidly reduced, and the electrostatic discharge path is equivalent to short circuit so as to rapidly discharge large electrostatic discharge current; similarly, when the source electrode of the device is subjected to electrostatic impact, the electrostatic discharge passage is opened, so that the grid electrode and the source electrode of the device are protected. The invention has the following advantages:
(1) Providing an electrostatic discharge path
On the premise of not influencing the normal operation of the device, the electrostatic discharge path between the grid electrode and the source electrode of the device is turned off when the device normally operates, and is rapidly turned on when the grid electrode or the source electrode is subjected to ESD impact to provide a path for discharging instant large current, so that the device is prevented from being directly broken down or burnt. Thereby protecting the safety of the device and the whole circuit and improving the robustness of the device and the circuit.
(2) Small external parasitic capacitance
Compared with the traditional external ESD protection circuit, the invention integrates the electrostatic discharge path inside the device, reduces parasitic capacitance introduced between metal interconnection lines, and reduces adverse effects of the device caused by the parasitic capacitance in application. The parasitic capacitance is small, so that the device can work at a higher frequency, the switching speed is improved, and the power consumption is reduced; and meanwhile, the risk of system oscillation caused by parasitic capacitance and inductance is reduced.
(3) High integration level
The gate protection area additionally arranged between the gate electrode and the source electrode of the device is used as an electrostatic discharge path, can replace an external parallel ESD protection circuit, and has higher integration level. The high integration level means small occupied area, more chips can be produced under the same area, the cost is saved, and the efficiency is higher.
(4) Good process compatibility
The first p-type semiconductor layer, the first n-type semiconductor layer and the second p-type semiconductor layer in the gate protection region can be formed in a step-by-step epitaxial mode in the traditional process and finally subjected to unified annealing activation.
Drawings
Fig. 1 is a block diagram of a conventional enhanced heterojunction semiconductor device;
fig. 2 (a) is a 3D diagram of a heterojunction semiconductor device with electrostatic discharge self-protection according to the present invention;
fig. 2 (b) is a top view of a heterojunction semiconductor device with electrostatic discharge self-protection according to the present invention, in which the metal gate electrode is not shown;
fig. 2 (c) is a cross-sectional view of a heterojunction semiconductor device with electrostatic discharge self-protection according to the present invention along the schematic A-A' section in fig. 2 (b);
fig. 2 (d) is a cross-sectional view of a heterojunction semiconductor device with electrostatic discharge self-protection according to the present invention taken along the schematic B-B' section in fig. 2 (B);
fig. 2 (e) is a cross-sectional view of a heterojunction semiconductor device with electrostatic discharge self-protection according to the present invention along the schematic C-C' section in fig. 2 (b);
fig. 2 (f) is an equivalent circuit diagram of a heterojunction semiconductor device with electrostatic discharge self-protection according to the present invention;
fig. 3 is a top view of embodiment 2 of a self-protecting heterojunction semiconductor device with electrostatic discharge according to the present invention, in which the metal gate electrode is not shown;
fig. 4 is a top view of embodiment 3 of a self-protecting heterojunction semiconductor device with electrostatic discharge according to the present invention, in which the metal gate electrode is not shown;
fig. 5 is a graph of a breakdown voltage simulation comparison of a heterojunction semiconductor device with self-protection of electrostatic discharge and a conventional heterojunction semiconductor device, wherein the graph shows that the heterojunction semiconductor device with self-protection of electrostatic discharge has better gate protection effect and higher ESD breakdown voltage.
The drawings are as follows: the semiconductor device comprises a buffer layer 1, a channel layer 2, a heterojunction channel 3, a barrier layer 4, a metal drain electrode 5, a high-resistance dielectric layer 6, a first p-type semiconductor layer 7, a first n-type semiconductor layer 8, a second p-type semiconductor layer 9, a metal gate electrode 10, a metal source electrode 11, a third p-type semiconductor layer 12, a gate protection region a and a gate control region b.
Detailed Description
The embodiments of the present invention are described below with reference to the drawings, and the embodiments described herein are only for illustrating and explaining the present invention, not for limiting the present invention.
Example 1
Referring to fig. 2 (a), 2 (b), fig. 2 (a) shows a 3D diagram of a self-protecting heterojunction semiconductor device with electrostatic discharge, and fig. 2 (b) shows a top view of a self-protecting heterojunction semiconductor device with electrostatic discharge, the device according to this example includes:
a buffer layer 1, a channel layer 2 and a barrier layer 4; the channel layer 2 contacts the barrier layer 4 to form a heterojunction channel 3; the upper surface of the barrier layer 4 is provided with a metal drain electrode 5 and a metal source electrode 11; a gate protection region a formed by alternately forming a first p-type semiconductor layer 7, a first n-type semiconductor layer 8 and a second p-type semiconductor layer 9 and a gate control region b formed by laminating a third p-type semiconductor layer 12 and a metal gate electrode 10 are arranged between the metal drain electrode 5 and the metal source electrode 11 and close to the metal source electrode 11 in the extending direction of the metal source electrode 5 on the upper surface of the barrier layer 4; the gate protection region a and the gate control region b are isolated by a high-resistance dielectric layer 6; the metal source electrode 11 is in direct contact with the second p-type semiconductor layer 9 in the gate protection region; the metal gate electrode 10 is simultaneously in direct contact with the first p-type semiconductor layer 7, the high-resistance dielectric layer 6 and the third p-type semiconductor layer 12 in the gate control region b in the gate protection region a; in the present embodiment of the present invention, in the present embodiment,
the first n-type semiconductor layer 8 is lightly doped, and the second p-type semiconductor layer 9 has higher doping concentration than the first p-type semiconductor layer 7; the thickness of the first n-type semiconductor layer 8 can be 10nm-100nm as the thinnest, and the first p-type semiconductor layer 7 and the second p-type semiconductor layer 9 are designed to be thicker than the first n-type semiconductor layer 8;
the metal gate electrode 10 forms ohmic contact with the first p-type semiconductor layer 7 in the gate protection region a and forms schottky contact with the third p-type semiconductor layer 12 in the gate control region b; the metal drain electrode 5 and the metal source electrode 11 form ohmic contact with the barrier layer 4; the metal gate electrode 10 may be one or more combinations of nickel, platinum or nickel-gold, platinum-gold alloy, and the metal drain electrode 5 and the metal source electrode 11 may be one or more combinations of titanium, aluminum, platinum, gold, nickel.
Example 2
Referring to fig. 3, compared with embodiment 1, the gate protection region a of the present embodiment may be an alternating combination structure formed by sequentially contacting a plurality of first p-type semiconductor layers 7, first n-type semiconductor layers 8 and second p-type semiconductor layers 9, and may be distributed at intervals along the extending direction of the metal source electrode 11;
example 3
Referring to fig. 4, compared with embodiment 1, the gate protection region a alternating combination structure of the present embodiment may be replaced by a high-resistance region 13, and a plurality of high-resistance regions 13 may be also distributed at intervals along the extending direction of the metal source electrode 11, and other structures are the same as embodiment 1. The high-resistance region 13 is made of p-type semiconductor material with extremely low concentration, is connected with the heterojunction HEMT device in parallel, not only provides an electrostatic discharge current discharging passage, but also plays a role in shunting when the device works normally, so that a gate electrode is protected, and gate leakage is reduced.
Claims (9)
1. The self-protection heterojunction semiconductor device for electrostatic discharge is characterized in that a buffer layer (1), a channel layer (2) and a barrier layer (4) are sequentially arranged on the heterojunction semiconductor device from bottom to top; the channel layer (2) is contacted with the barrier layer (4) to form a heterojunction channel (3); one side of the upper surface of the barrier layer (4) is provided with a metal drain electrode (5), and the opposite side is provided with a metal source electrode (11); a gate protection region (a) consisting of a first p-type semiconductor layer (7), a first n-type semiconductor layer (8) and a second p-type semiconductor layer (9) is sequentially arranged between the metal drain electrode (5) and the metal source electrode (11) and close to the metal source electrode (11) in the extending direction of the metal source electrode (5) on the upper surface of the barrier layer (4); the third p-type semiconductor layer (12) and the first p-type semiconductor layer (7) are coaxial in the length direction, the metal gate electrode (10) is positioned above the third p-type semiconductor layer (12) and the first p-type semiconductor layer (7), and the third p-type semiconductor layer (12) and the metal gate electrode (10) are laminated to form a gate control region (b); the gate protection area (a) and the gate control area (b) are isolated by a high-resistance dielectric layer (6); the metal source electrode (11) is in direct contact with the second p-type semiconductor layer (9) in the gate protection region; the metal gate electrode (10) is simultaneously in direct contact with the first p-type semiconductor layer (7) in the gate protection region (a), the high-resistance dielectric layer (6) and the third p-type semiconductor layer (12) in the gate control region (b).
2. The self-protecting heterojunction semiconductor device of claim 1, wherein: the first n-type semiconductor layer (8) is lightly doped, and the doping concentration of the second p-type semiconductor layer (9) is higher than that of the first p-type semiconductor layer (7); the first p-type semiconductor layer (7) and the second p-type semiconductor layer (9) are thicker than the first n-type semiconductor layer (8).
3. The self-protecting heterojunction semiconductor device as claimed in claim 1, wherein said first n-type semiconductor layer (8) has a thickness of 10nm-100nm.
4. The self-protection heterojunction semiconductor device for static discharge according to claim 1, wherein the gate protection region (a) is an alternating combination structure formed by sequentially contacting a plurality of first p-type semiconductor layers (7), first n-type semiconductor layers (8) and second p-type semiconductor layers (9), and a plurality of gate protection regions (a) can be distributed at intervals along the extending direction of the metal source electrode (11).
5. A self-protected heterojunction semiconductor device as claimed in claim 4, wherein said alternating combination of gate protection regions (a) is replaced by high resistance regions (13).
6. The self-protecting heterojunction semiconductor device as claimed in claim 5, wherein said high-resistance regions (13) are arranged in a plurality at intervals along the extending direction of the metal source electrode (11).
7. A self-protecting heterojunction semiconductor device as claimed in claim 1, wherein said metal gate electrode (10) forms an ohmic contact with the first p-type semiconductor layer (7) in the gate protection region (a) and a schottky contact with the third p-type semiconductor layer (12) in the gate control region (b); the metal drain electrode (5) and the metal source electrode (11) form ohmic contact with the barrier layer (4).
8. An electrostatic discharge self-protecting heterojunction semiconductor device as claimed in claim 1, wherein said metal gate electrode (10) is one or more combinations of nickel, platinum, nickel gold or platinum gold.
9. An electrostatic discharge self-protecting heterojunction semiconductor device as claimed in claim 1, wherein said metal drain electrode (5) and metal source electrode (11) are one or more combinations of titanium, aluminum, platinum, gold or nickel.
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| CN103151374A (en) * | 2011-12-07 | 2013-06-12 | 三星电子株式会社 | High electron mobility transistor |
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| CN106169507A (en) * | 2015-05-18 | 2016-11-30 | 丰田自动车株式会社 | Heterojunction semiconductor device and the method manufacturing heterojunction semiconductor device |
| CN107046030A (en) * | 2016-02-09 | 2017-08-15 | 三菱电机株式会社 | Field-effect transistor with protection diode |
| US10128228B1 (en) * | 2017-06-22 | 2018-11-13 | Infineon Technologies Americas Corp. | Type III-V semiconductor device with integrated diode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9035318B2 (en) * | 2013-05-03 | 2015-05-19 | Texas Instruments Incorporated | Avalanche energy handling capable III-nitride transistors |
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- 2021-05-31 CN CN202110598471.7A patent/CN113327923B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151374A (en) * | 2011-12-07 | 2013-06-12 | 三星电子株式会社 | High electron mobility transistor |
| CN104979342A (en) * | 2014-04-14 | 2015-10-14 | 英飞凌科技德累斯顿有限责任公司 | Semiconductor Device with Electrostatic Discharge Protection Structure |
| CN106169507A (en) * | 2015-05-18 | 2016-11-30 | 丰田自动车株式会社 | Heterojunction semiconductor device and the method manufacturing heterojunction semiconductor device |
| CN107046030A (en) * | 2016-02-09 | 2017-08-15 | 三菱电机株式会社 | Field-effect transistor with protection diode |
| US10128228B1 (en) * | 2017-06-22 | 2018-11-13 | Infineon Technologies Americas Corp. | Type III-V semiconductor device with integrated diode |
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