CN113327923A - Heterojunction semiconductor device with electrostatic discharge self-protection function - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 229910052751 metal Inorganic materials 0.000 claims abstract description 69
- 239000002184 metal Substances 0.000 claims abstract description 69
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 3
- JUWSSMXCCAMYGX-UHFFFAOYSA-N gold platinum Chemical compound [Pt].[Au] JUWSSMXCCAMYGX-UHFFFAOYSA-N 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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Abstract
The invention relates to a heterojunction semiconductor device with self-protection in electrostatic discharge, comprising: the buffer layer, the channel layer, the heterojunction channel and the barrier layer; the upper surface of the barrier layer is provided with a metal drain electrode and a metal source electrode; a gate protection region formed by alternately arranging a first p-type semiconductor layer, a first n-type semiconductor layer and a second p-type semiconductor layer and a gate control region formed by laminating a third p-type semiconductor layer and a metal gate electrode are arranged between the metal drain electrode and the metal source electrode and close to the metal source electrode at intervals; the gate protection area a and the gate control area b are isolated by a high-resistance dielectric layer; the gate protection region provides an ESD current discharge channel to protect the gate from the impact of transient large current. Compared with the traditional external ESD protection circuit, the invention has the advantages of high integration level, small occupied area, small parasitic capacitance and the like.
Description
Technical Field
The invention belongs to the field of power electronics and semiconductor device reliability research, and particularly relates to a heterojunction semiconductor device integrating a bidirectional diode between a grid electrode and a source electrode of the device to play a role in electrostatic protection.
Background
During the last decades, the first generation of semiconductor materials, represented by silicon, has supported the rapid growth of the electronic information society, and as technology advances, the research on silicon-based devices has approached their theoretical limit. Currently, through the development of second-generation semiconductors such as gallium arsenide (GaAs) and indium antimonide (InSb), third-generation semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) are being developed and applied in large quantities with their excellent characteristics. The third generation semiconductor gallium nitride is a wide band gap semiconductor, has the advantages of high thermal conductivity, high temperature resistance, radiation resistance, acid and alkali resistance, high strength, high hardness and the like, and is a hot spot in the research direction of semiconductor materials all over the world at present. Gallium nitride as a novel semiconductor material has wide prospect in the application aspects of photoelectrons, high-temperature high-power devices and high-frequency microwave devices. Because a heterojunction channel formed by a barrier layer and a channel layer through a polarization effect of a gallium nitride high-electron-mobility transistor (GaN HMET) device has extremely high electron mobility, the GaN device has the advantages of low on resistance, high working frequency, high conversion efficiency, low parasitic capacitance and the like; at present, GaN HMET devices are also used as core switch components in many power system circuits, and the corresponding reliability is continuously improved in product update iterations.
Nevertheless, there are still some reliability issues that are of concern. Among them, electrostatic discharge (ESD) is a common phenomenon in life, and for a semiconductor device, Static charges accumulated on a human body or metal contact pins of a chip, and a very large transient current or voltage spike is generated in a very short time (tens to hundreds of nanoseconds) to burn out the device, so that the device is permanently disabled. Although the gan heterojunction device has a high breakdown electric field, the inside of the gan heterojunction device has no PN structure to assist leakage charge energy impact, so that the conventional enhancement heterojunction semiconductor device is usually connected with an ESD protection branch outside the device in parallel to improve the overall ESD impact resistance, and the commonly used ESD protection branch mainly includes a diode, a triode (BJT), a Grounded Gate NMOS (GGMOS), a Silicon Controlled Rectifier (SCR), and the like. However, these methods have the disadvantages of low integration level, complex circuit design, large parasitic capacitance, large occupied area and high cost. Therefore, from the viewpoints of improving the system integration level and increasing the device robustness, the improvement of the self anti-static impact capability of the device has important significance.
Disclosure of Invention
The technical problem is as follows: ESD is one of the primary factors affecting the reliability of the device, and static charges accumulated on human bodies or metals contact pins of the chip, so that a large instantaneous current or voltage spike is generated in a very short time, and the device is burnt out to permanently fail. The present invention provides a heterojunction semiconductor device with self-protection of electrostatic discharge.
The technical scheme is as follows: the heterojunction semiconductor device with the electrostatic discharge self-protection function is provided with a buffer layer, a channel layer and a barrier layer from bottom to top in sequence; the channel layer is in contact with the barrier layer to form a heterojunction channel; one side of the upper surface of the barrier layer is provided with a metal drain electrode, and the other opposite side is provided with a metal source electrode; a gate protection region which is arranged in the extending direction of the metal source electrode on the upper surface of the barrier layer, is arranged between the metal drain electrode and the metal source electrode and is close to the metal source electrode in sequence and consists of a first p-type semiconductor layer, a first n-type semiconductor layer and a second p-type semiconductor layer; the third p-type semiconductor layer and the first p-type semiconductor layer are coaxial in the length direction, the metal gate electrode is positioned above the third p-type semiconductor layer and the first p-type semiconductor layer, and the third p-type semiconductor layer and the metal gate electrode are laminated to form a gate control area; the gate protection region is isolated from the gate control region through a high-resistance dielectric layer; the metal source electrode is in direct contact with the second p-type semiconductor layer in the gate protection region; the metal gate electrode is simultaneously in direct contact with the first p-type semiconductor layer in the gate protection region, the high-resistance dielectric layer and the third p-type semiconductor layer in the gate control region.
The first n-type semiconductor layer is lightly doped, and the doping concentration of the second p-type semiconductor layer is higher than that of the first p-type semiconductor layer; the first p-type semiconductor layer and the second p-type semiconductor layer are designed to be thicker than the first n-type semiconductor layer.
The thickness of the first n-type semiconductor layer is 10nm-100 nm.
The gate protection region is an alternate combination structure formed by sequentially contacting a plurality of first p-type semiconductor layers, a first n-type semiconductor layer and a second p-type semiconductor layer, and a plurality of gate protection regions can be distributed at intervals along the extending direction of the metal source electrode.
The gate protection area alternate combination structure is replaced by a high-resistance area, and a plurality of high-resistance areas can be distributed at intervals along the extending direction of the metal source electrode.
The metal gate electrode forms ohmic contact with the first p-type semiconductor layer in the gate protection region and forms Schottky contact with the third p-type semiconductor layer in the gate control region; the metal drain electrode and the metal source electrode form ohmic contact with the barrier layer.
The metal gate electrode is one or more of nickel, platinum, nickel gold or platinum gold.
The metal drain electrode and the metal source electrode are one or more of titanium, aluminum, platinum, gold or nickel.
Has the advantages that: the device disclosed by the invention is internally integrated with an ESD protection circuit, and an alternating combined structure is formed by doping between the grid and the source to be used as an electrostatic discharge path, so that the grid and the source can be effectively protected against ESD simultaneously. The working principle is as follows: when the device works normally, the grid electrode is opened, the device is conducted, the conducting voltage is not enough to open the electrostatic discharge path, the electrostatic discharge path is equivalent to open circuit, and the normal work of the device is not influenced; when the grid of the device is subjected to electrostatic impact, the first p-type semiconductor layer below the metal grid electrode is in forward conduction with the pn junction formed by the first n-type semiconductor layer, instantaneous high voltage enables the pn junction formed by the first n-type semiconductor layer and the second p-type semiconductor layer to be in reverse breakdown, the on-resistance is rapidly reduced, and an electrostatic discharge path is equivalent to short circuit so as to rapidly discharge large electrostatic discharge current; similarly, when the source of the device is subjected to electrostatic impact, the electrostatic discharge path is also opened, so that the gate and the source of the device are protected. The invention has the following advantages:
(1) providing an electrostatic discharge path
On the premise of not influencing the normal operation of the device, the electrostatic discharge path between the grid and the source of the device is switched off when the device works normally, and is rapidly switched on when the grid or the source is impacted by ESD to provide a path for discharging instantaneous large current, so that the device is prevented from being directly broken down or burnt. Therefore, the safety of the device and the whole circuit is protected, and the robustness of the device and the circuit is improved.
(2) Small external parasitic capacitance
Compared with the traditional external ESD protection circuit, the electrostatic discharge circuit is integrated in the device, so that parasitic capacitance introduced between metal interconnection lines is reduced, and adverse effects of the device caused by the parasitic capacitance in application are reduced. The parasitic capacitance is small, so that the device can work at higher frequency, the switching speed is improved, and the power consumption is reduced; meanwhile, the risk of system oscillation caused by parasitic capacitance and inductance is reduced.
(3) High integration level
The device provided by the invention has the advantages that the gate protection area additionally arranged between the grid electrode and the source electrode is used as an electrostatic discharge path, an external parallel ESD protection circuit can be replaced, and the integration level is higher. The high integration level means that the occupied area is small, more chips can be produced in the same area, the cost is saved, and the efficiency is higher.
(4) Good process compatibility
The first p-type semiconductor layer, the first n-type semiconductor layer and the second p-type semiconductor layer in the gate protection region can be formed in a step-by-step epitaxial mode in the traditional process, and finally, annealing and activation are unified.
Drawings
FIG. 1 is a block diagram of a conventional enhanced heterojunction semiconductor device;
FIG. 2(a) is a 3D diagram of a heterojunction semiconductor device with electrostatic discharge self-protection according to the present invention;
FIG. 2(b) is a top view of a heterojunction semiconductor device with electrostatic discharge self-protection according to the present invention, without showing a metal gate electrode;
FIG. 2(c) is a cross-sectional view of an ESD self-protected heterojunction semiconductor device of the present invention taken along section A-A' of FIG. 2 (b);
FIG. 2(d) is a cross-sectional view of an ESD self-protected heterojunction semiconductor device of the present invention taken along section B-B' of FIG. 2 (B);
FIG. 2(e) is a cross-sectional view of an ESD self-protected heterojunction semiconductor device of the present invention taken along section C-C' of FIG. 2 (b);
FIG. 2(f) is an equivalent circuit diagram of a self-protected heterojunction semiconductor device with electrostatic discharge in accordance with the present invention;
fig. 3 is a top view of embodiment 2 of an esd self-protected heterojunction semiconductor device in accordance with the present invention, without showing a metal gate electrode;
fig. 4 is a top view of embodiment 3 of an electrostatic discharge self-protected heterojunction semiconductor device in accordance with the present invention, without showing a metal gate electrode;
fig. 5 is a simulation comparison graph of breakdown voltages of a self-protected heterojunction semiconductor device with electrostatic discharge according to the present invention and a conventional heterojunction semiconductor device, which shows that the self-protected heterojunction semiconductor device with electrostatic discharge according to the present invention has a better gate protection effect and a higher ESD breakdown voltage.
The figure shows that: the semiconductor device comprises a buffer layer 1, a channel layer 2, a heterojunction channel 3, a barrier layer 4, a metal drain electrode 5, a high-resistance medium layer 6, a first p-type semiconductor layer 7, a first n-type semiconductor layer 8, a second p-type semiconductor layer 9, a metal gate electrode 10, a metal source electrode 11, a third p-type semiconductor layer 12, a gate protection region a and a gate control region b.
Detailed Description
The embodiments of the present invention will be described below with reference to the accompanying drawings, and the embodiments described herein are only for the purpose of illustrating and explaining the present invention and are not intended to limit the present invention.
Example 1
Referring to fig. 2(a), 2(b), fig. 2(a) shows a diagram of a heterojunction semiconductor device 3D which is self-protecting against electrostatic discharge, and fig. 2(b) shows a top view of a heterojunction semiconductor device which is self-protecting against electrostatic discharge, this example device comprising:
a buffer layer 1, a channel layer 2 and a barrier layer 4; the channel layer 2 is in contact with the barrier layer 4 to form a heterojunction channel 3; the upper surface of the barrier layer 4 is provided with a metal drain electrode 5 and a metal source electrode 11; a gate protection region a which is formed by alternately arranging a first p-type semiconductor layer 7, a first n-type semiconductor layer 8 and a second p-type semiconductor layer 9 and a gate control region b which is formed by laminating a third p-type semiconductor layer 12 and a metal gate electrode 10 are arranged between the metal drain electrode 5 and the metal source electrode 11 and close to the metal source electrode 11 at intervals in the extending direction of the metal source electrode 5 on the upper surface of the barrier layer 4; the gate protection area a and the gate control area b are isolated by a high-resistance dielectric layer 6; the metal source electrode 11 is in direct contact with the second p-type semiconductor layer 9 in the gate protection region; the metal gate electrode 10 is simultaneously in direct contact with the first p-type semiconductor layer 7 in the gate protection region a, the high-resistance dielectric layer 6 and the third p-type semiconductor layer 12 in the gate control region b; in the present embodiment, it is preferred that,
the first n-type semiconductor layer 8 is lightly doped, and the second p-type semiconductor layer 9 is higher in doping concentration and higher in doping concentration than the first p-type semiconductor layer 7; the thickness of the first n-type semiconductor layer 8 can be 10nm-100nm, and the first p-type semiconductor layer 7 and the second p-type semiconductor layer 9 are designed to be thicker than the first n-type semiconductor layer 8;
the metal gate electrode 10 forms ohmic contact with the first p-type semiconductor layer 7 in the gate protection region a and forms Schottky contact with the third p-type semiconductor layer 12 in the gate control region b; the metal drain electrode 5 and the metal source electrode 11 form ohmic contact with the barrier layer 4; the metal gate electrode 10 may be one or more combinations of nickel, platinum or nickel-gold, platinum-gold alloy, and the metal drain electrode 5 and the metal source electrode 11 may be one or more combinations of titanium, aluminum, platinum, gold, nickel.
Example 2
Referring to fig. 3, compared to embodiment 1, the gate protection region a of this embodiment may be an alternating combination structure formed by sequentially contacting a plurality of first p-type semiconductor layers 7, a plurality of first n-type semiconductor layers 8, and a plurality of second p-type semiconductor layers 9, and a plurality of gate protection regions a may be distributed at intervals along the extending direction of the metal source electrode 11;
example 3
Referring to fig. 4, compared with embodiment 1, the alternating combination structure of the gate protection region a of this embodiment may be replaced by the high resistance region 13, and a plurality of high resistance regions 13 may be distributed at intervals along the extending direction of the metal source electrode 11, and the other structures are the same as those of embodiment 1. The high resistance region 13 is made of p-type semiconductor material with extremely low concentration, is connected with the heterojunction HEMT device in parallel, provides an electrostatic discharge current leakage path, and also plays a role in shunting when the device works normally, thereby protecting a gate electrode and reducing gate leakage.
Claims (8)
1. A heterojunction semiconductor device with electrostatic discharge self-protection is characterized in that the heterojunction semiconductor device is sequentially provided with a buffer layer (1), a channel layer (2) and a barrier layer (4) from bottom to top; the channel layer (2) is in contact with the barrier layer (4) to form a heterojunction channel (3); one side of the upper surface of the barrier layer (4) is provided with a metal drain electrode (5), and the other opposite side is provided with a metal source electrode (11); a gate protection region (a) which is positioned in the extending direction of the metal source electrode (5) on the upper surface of the barrier layer (4), is arranged between the metal drain electrode (5) and the metal source electrode (11) and is close to the metal source electrode (11) in sequence and consists of a first p-type semiconductor layer (7), a first n-type semiconductor layer (8) and a second p-type semiconductor layer (9); the third p-type semiconductor layer (12) and the first p-type semiconductor layer (7) are coaxial in the length direction, the metal gate electrode (10) is located above the third p-type semiconductor layer (12) and the first p-type semiconductor layer (7), and the third p-type semiconductor layer (12) and the metal gate electrode (10) are stacked to form a gate control region (b); the gate protection region (a) is isolated from the gate control region (b) through a high-resistance dielectric layer (6); the metal source electrode (11) is in direct contact with the second p-type semiconductor layer (9) in the gate protection region; the metal gate electrode (10) is simultaneously in direct contact with the first p-type semiconductor layer (7) in the gate protection region (a), the high-resistance dielectric layer (6) and the third p-type semiconductor layer (12) in the gate control region (b).
2. The heterojunction semiconductor device of claim 1, wherein: the first n-type semiconductor layer (8) is lightly doped, and the doping concentration of the second p-type semiconductor layer (9) is higher than that of the first p-type semiconductor layer (7); the first p-type semiconductor layer (7) and the second p-type semiconductor layer (9) are designed to be thicker than the first n-type semiconductor layer (8).
3. An electrostatic discharge self-protected heterojunction semiconductor device according to claim 1, wherein said first n-type semiconductor layer (8) has a thickness of 10nm to 100 nm.
4. The semiconductor device of claim 1, wherein the gate protection region (a) is an alternating combination structure of a plurality of first p-type semiconductor layers (7), first n-type semiconductor layers (8) and second p-type semiconductor layers (9) in contact with each other, and a plurality of gate protection regions (a) are distributed at intervals along the extension direction of the metal source electrode (11).
5. A self-protected heterojunction semiconductor device with electrostatic discharge according to claim 4, wherein said alternating combination of gate protection regions (a) is replaced by high resistance regions (13), and a plurality of high resistance regions (13) are further spaced along the extension direction of the metal source electrode (11).
6. An electrostatic discharge self-protected heterojunction semiconductor device according to claim 1, wherein said metal gate electrode (10) forms an ohmic contact with the first p-type semiconductor layer (7) in the gate protection region (a) and a schottky contact with the third p-type semiconductor layer (12) in the gate control region (b); the metal drain electrode (5), the metal source electrode (11) and the barrier layer (4) form ohmic contact.
7. An electrostatic discharge self-protected heterojunction semiconductor device according to claim 1, wherein said metal gate electrode (10) is one or more combinations of nickel, platinum, nickel-gold or platinum-gold.
8. A self-protecting heterojunction semiconductor device of electrostatic discharge according to claim 1, wherein the metal drain electrode (5) and the metal source electrode (11) are one or more combinations of titanium, aluminum, platinum, gold or nickel.
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| CN107046030A (en) * | 2016-02-09 | 2017-08-15 | 三菱电机株式会社 | Field-effect transistor with protection diode |
| US10128228B1 (en) * | 2017-06-22 | 2018-11-13 | Infineon Technologies Americas Corp. | Type III-V semiconductor device with integrated diode |
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2021
- 2021-05-31 CN CN202110598471.7A patent/CN113327923B/en active Active
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| CN103151374A (en) * | 2011-12-07 | 2013-06-12 | 三星电子株式会社 | High electron mobility transistor |
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