CN113257760A - 与使用混合间隔件的功率模块相关的结构和方法 - Google Patents

与使用混合间隔件的功率模块相关的结构和方法 Download PDF

Info

Publication number
CN113257760A
CN113257760A CN202110072148.6A CN202110072148A CN113257760A CN 113257760 A CN113257760 A CN 113257760A CN 202110072148 A CN202110072148 A CN 202110072148A CN 113257760 A CN113257760 A CN 113257760A
Authority
CN
China
Prior art keywords
spacer block
block
device die
solid
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110072148.6A
Other languages
English (en)
Inventor
陈良彪
刘勇
程子轩
S·圣日尔曼
R·阿巴斯诺特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Publication of CN113257760A publication Critical patent/CN113257760A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2089—Modifications to facilitate cooling, ventilating, or heating for power electronics, e.g. for inverters for controlling motor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thermal Sciences (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明涉及与使用混合间隔件的功率模块相关的结构和方法。实施例公开了一种功率模块，该功率模块包括间隔块、耦接到该间隔块的一侧的导热衬底以及耦接到该间隔块的相背对侧的半导体器件管芯。该间隔块包括实心间隔块和邻近柔性间隔块。该器件管芯的内部部分耦接到该实心间隔块，并且该半导体器件管芯的外部部分耦接到该邻近柔性间隔块。

Description

与使用混合间隔件的功率模块相关的结构和方法
相关申请
本专利申请要求于2020年2月7日提交的美国专利申请号16/784,999 的优先权和权益，该专利申请据此全文以引用方式并入本文。
技术领域
本说明书涉及功率器件的封装。
背景技术
现代高功率器件可使用先进的硅技术来制造以满足高功率要求。这些高功率器件(例如，诸如绝缘栅双极晶体管(IGBT)、快速恢复二极管 (FRD)等硅功率器件)可封装在单侧冷却(SSC)或双侧冷却(DSC)功率模块中。可递送或切换高水平功率的高功率器件可用于例如以电力为动力的车辆(例如，电动车辆(EV)、混合动力车辆(HEV)和插电式混合动力车辆(PHEV))。在电路封装件或功率模块(例如，SSC或DSC功率模块)中使用的高功率器件的封装期间，或者在所制造的高功率器件的应力测试期间，该高功率器件管芯的较大尺寸和厚度可能产生诸如管芯翘曲和管芯损坏的问题。
发明内容
在一般方面，模块(例如，功率器件模块)包括耦接到半导体器件管芯的间隔块。导热衬底(例如，直接接合铜(DBC)衬底)耦接到间隔块的第一侧。半导体器件管芯耦接到间隔块的与第一侧相背对的第二侧。间隔块包括实心间隔块和邻近柔性间隔块。半导体器件管芯的内部部分耦接到实心间隔块，并且半导体器件管芯的外部部分耦接到邻近柔性间隔块。邻近柔性间隔块被配置为适应由模块部件的热膨胀系数(CTE)失配引起的模块中的半导体器件管芯的机械位移。
在一个方面，邻近柔性间隔块至少部分地围绕实心间隔块。
在一个方面，邻近柔性间隔块是附接到实心间隔块的一侧并且从该侧朝向器件管芯的边缘延伸的条带。
在一个方面，邻近柔性间隔块在器件管芯的边缘处耦接到信号焊盘区域。
在示例性实施方式中，邻近柔性间隔块具有由直鳍片、倾斜鳍片、弯折鳍片、弯曲鳍片或S形鳍片中的至少一者制成的波状(corrugated)结构。
一个或多个实施方式的细节在附图和以下描述中阐明。其他特征将从说明书和附图中以及从权利要求书中显而易见。
附图说明
图1A是示出示例性混合间隔块的框图。
图1B是示出利用用于管芯-支撑间隔块组合的混合间隔块的示例性功率模块的框图。
图2A示出了实心块。
图2B至图2F示出了可用于混合间隔块的不同类型的柔性间隔件构型。
图3示出了示例性混合间隔块。
图4示出了用于组装混合间隔块的示例性方法。
图5A至图5I示出了通过图4的方法在不同组装阶段的混合间隔块。
图6示出了用于组装混合间隔块的示例性方法。
图7A至图7D示出了通过图6的方法在不同组装阶段的混合间隔块。
图8示出了描绘单个管芯、实心间隔块和柔性间隔块的相对尺寸的示意图。
图9是在多管芯功率模块中使用的混合间隔块的示意图。
图10是可单独耦接到多管芯功率模块中的第一器件管芯和第二器件管芯的混合间隔块的布置的示意图。
图11是耦接到多管芯功率模块中的第一器件管芯和第二器件管芯的混合间隔块的示意图。
图12是耦接到多管芯功率模块中的第一器件管芯和第二器件管芯的混合间隔块的示意图。
图13示出了使用功率模块中的柔性间隔块的示例性方法。
具体实施方式
现代高功率半导体器件可使用先进的硅技术来制造以满足高功率要求。可使用例如硅(Si)、碳化硅(SiC)和氮化镓(GaN)材料或其他半导体材料中的一者或多者来制造功率器件(例如，绝缘栅双极晶体管 (IGBT)、快速恢复二极管(FRD)等)。可在例如仅约100微米厚或更少的减薄半导体晶圆(例如，硅晶圆)上制造功率器件。这导致与使用常规硅技术在常规基板上(即，在未减薄的硅晶圆上)制造的传统功率器件的功率器件管芯尺寸相比，高功率器件管芯尺寸更大并且更薄。
在电路封装件(例如，双侧冷却(DSC)功率模块)中，半导体器件管芯可被放置在有助于将热量从半导体器件管芯传导出去的直接接合铜 (DBC)衬底对之间。可通过将支撑间隔块(即，导热间隔块)接合(例如，焊接)到管芯的背面来在机械上并在结构上增强单个减薄的器件管芯。间隔件还提供良好的电隔离和热性能。支撑间隔块的另一侧可接合到 DBC衬底。支撑间隔块为从半导体器件管芯到DBC衬底的热流动提供热通路。在DSC功率模块中，管芯-支撑块组合被放置在DBC衬底对之间并且包封在模塑材料(例如，环氧模塑料(EMC))中。在其中管芯以倒装芯片构型放置在DBC衬底上的情况下，可引入模塑底部填充(MUF)模塑材料以对倒装芯片管芯下方的窄间隙进行底部填充，并且对管芯-支撑块组合进行包覆成型以用于包封。
在一些实施方式中，支撑间隔块是实心(solid)导热材料件(例如，具有横截面积A和厚度T的矩形实心铜块)。薄型器件管芯的厚度通过管芯-支撑间隔块组合中的实心铜块的厚度来增加。实心铜块可具有比器件管芯的面积小的横截面积，或者可具有可相当于器件管芯的面积的较大横截面积。然而，当块面积小于管芯面积时，可在实心铜块周围形成管芯中的裂纹。已提出使用具有较大面积(例如，大于或相当于器件管芯的面积) 的实心铜块作为补救措施，但大面积实心铜块也导致管芯开裂。焊料空隙可在管芯-支撑间隔块组合中的较大面积的实心铜块与管芯之间形成。这些焊料空隙可在管芯拐角处引起管芯拐角裂纹。
管芯拐角裂纹的原因可为管芯-支撑间隔块组合中所用的间隔块(例如，铜块)和MUF(或EMC)之间的热膨胀系数(CTE)失配。由于铜间隔块在冷却时比MUF(或EMC)收缩得更快，因此MUF(或EMC)将对抗由实心铜间隔块在管芯拐角处利用焊料空隙的收缩引起的管芯运动，并且导致产生管芯拐角裂纹的应力。
根据本公开的原理，用于管芯-支撑间隔块组合的混合间隔块具有混合结构，该混合结构包括实心块间隔件部分和机械弹性或柔性块间隔件部分。实心间隔块部分可具有小于管芯面积的横截面积。实心间隔块部分可为混合间隔块的内部部分(中心部分)。柔性块间隔件部分可在实心间隔块部分周围(例如，围绕或邻近)设置。柔性间隔块部分和实心间隔块部分组合可具有相当于或大于管芯面积的横截面积。在管芯-支撑间隔块组合中，柔性间隔块部分可延伸到管芯拐角，并且可柔性地适应由于部件(例如，金属、EMC和管芯半导体)之间的CTE失配而引起的任何机械位移。由于CTE失配引起的机械位移的这种灵活适应可以防止管芯拐角处的管芯开裂，并且减少利用管芯-支撑间隔块组合的DSC功率模块中的器件焊盘 (例如，信号焊盘)下方的焊料剥离故障的情况。
图1A示出了根据本公开的原理的示例性混合间隔块140的剖视图。混合间隔块140可包括由柔性间隔块144(例如，机械柔性铜块)围绕(例如，完全围绕、至少部分围绕)的实心金属块142(例如，实心铜块)。实心金属块142可具有宽度Ws。包括柔性间隔块144的混合间隔块140可具有宽度Wf。实心金属块142和柔性间隔块144可设置在金属片146和147 (例如，铜片或铜箔)之间，并且通过焊料(例如，焊料14)在金属片 146和147之间保持到位。
图1B示出了根据本公开的原理的利用管芯-支撑间隔块组合中的混合间隔块140的示例性DSC功率模块100的剖视图。示例性DSC功率模块 100可利用结合至少图1A讨论的混合间隔块140。
DSC功率模块100可将器件管芯130和混合间隔块140包封在两个 DBC衬底(例如，DBC衬底110和DBC衬底120)之间。在一侧上，混合间隔块(例如，混合间隔块140)耦接到器件管芯130，并且在另一侧上，混合间隔块接合到两个DBC衬底中的一者(例如，DBC衬底110)。混合间隔块为在器件管芯中生成的耗散在DBC衬底110上方的热量提供热通路。
混合间隔块140可包括由柔性间隔块144(例如，机械柔性铜块)围绕的实心金属块142(例如，实心铜块)。实心金属块142和柔性间隔块 144可设置在金属片146和147(例如，铜片或铜箔)之间，并且通过焊料 (例如，焊料14)在金属片146和147之间保持到位。器件管芯130(例如，IGBT器件)可经由焊料层15接合(例如，焊接)到混合间隔块140，从而形成DSC功率模块100的管芯-间隔块组合150。器件管芯130的内部部分可接合到实心金属块142。器件管芯的外部部分(例如，从器件管芯的内部部分延伸到边缘E)可接合到柔性间隔块144。在示例性实施方式中，如图1B所示，混合间隔块140可具有与器件管芯130的宽度Wdie相比大致相同或更大的宽度Wsp。在这种几何布置中，可(例如，在机械上)通过柔性间隔块144的弹性来适应器件管芯边缘E的任何位移(例如，由部件的热失配引起的器件管芯弯折)，并且可防止管芯开裂。
在示例性实施方式中，如图1B所示，DBC衬底110和DBC衬底120 可以是镀有铜层(例如，层114、124)的瓷片(例如，氧化铝片112、 122)。器件管芯130(例如，IGBT器件)可具有一个或多个接触焊盘(例如，信号焊盘132和源极焊盘133)。
在示例性实施方式中，如图1B所示，DSC功率模块100可例如在管芯-间隔块组合150处于使器件130处于倒装芯片构型中的取向的情况下来组装。处于倒装芯片构型中的器件130可具有经由焊料层16接合到DBC 衬底120的信号焊盘132和源极焊盘133。另外，(管芯-间隔块组合150 的)混合间隔块140可经由焊料层17接合到DBC衬底110。
用于混合间隔块140中的柔性间隔块144的机械弹性或柔性间隔材料可以是不同类型的。图2B至图2F示出了可用于混合间隔块140的不同类型的柔性间隔件构型的剖视图。为了比较，图2A示出了实心金属块142的剖视图。
图2B示出了示例性柔性间隔材料200B，该柔性间隔材料包括由直鳍片(例如，直鳍片201)制成的波状结构201S。如图2B绘画地示出，直鳍片可被布置成使得波状结构201S由交替的矩形脊201r和具有竖直侧壁201sw的沟槽或凹谷201v制成并且由直鳍片201形成。脊201r和凹谷201s 可以空间周期性Wv交替。具有竖直侧壁201sw的凹谷201v可具有高度 Tv。
图2C示出了示例性柔性间隔材料200C，该柔性间隔材料包括由倾斜鳍片(例如，倾斜鳍片202)制成的波状结构202S。如图2C绘画地示出，倾斜鳍片可被布置成使得波状结构202S由交替的脊202r和具有歪斜或倾斜侧壁202sw的沟槽或凹谷202v制成并且由倾斜鳍片202形成。
图2D示出了示例性柔性间隔材料200D，该柔性间隔材料包括由弯折鳍片(例如，弯折鳍片203)制成的波状结构203S。如图2C绘画地示出，弯折鳍片可被布置成使得波状结构203S由交替的脊203r和具有弯折侧壁 203sw的沟槽或凹谷202v制成并且由弯折鳍片203形成。
图2E示出了示例性柔性间隔材料200E，该柔性间隔材料包括由弯曲鳍片(例如，弯曲鳍片204)制成的波状结构204S。如图2E绘画地示出，弯曲鳍片可被布置成使得波状结构204S由交替的矩形脊204r和具有弯曲侧壁204sw的沟槽或凹谷204v制成并且由弯曲鳍片204形成。
图2F示出了示例性柔性间隔材料200F，该柔性间隔材料包括由S形鳍片(例如，S形鳍片205)制成的波状结构205S。如图2F绘画地示出， S形鳍片可被布置成使得波状结构205S由交替的矩形脊205r和具有S形侧壁205sw的沟槽或凹谷205v制成并且由S形鳍片204形成。
具有不同类型的鳍片结构(例如，直鳍片101、倾斜鳍片202、弯折鳍片203、弯曲鳍片204和S形鳍片205等)的不同类型的柔性间隔材料可为柔性间隔块144赋予不同的机械特性和热特性。
如上所述，图1A和图1B示出了例如其中柔性间隔块144由S形鳍片式(即，S形鳍片205)的柔性间隔材料制成的实施方式。
图3示出了例如其中混合间隔块140使用用于柔性间隔块144的直鳍式(即，直鳍片201)的材料的实施方式。如图3所示，在混合间隔块140 中，柔性间隔块144可围绕实心间隔块(例如，实心间隔块142)并耦接到该实心间隔块。
图4示出了用于组装混合间隔块(例如，混合间隔块140)以在功率模块中的管芯-间隔块组合中使用的示例性方法400。
方法400包括将柔性间隔材料块成型为指定外部尺寸的混合间隔块，并且制备柔性间隔材料块的内部部分以容纳指定尺寸的实心金属块 (410)。混合间隔块的指定外部尺寸可匹配管芯-间隔块组合中的半导体管芯的尺寸。
制备柔性间隔材料块的内部部分以容纳指定尺寸的实心金属块410可包括移除柔性间隔材料块的一部分以在柔性间隔材料块中(例如，通过切出孔)形成开口。制备内部部分可包括将侧箔板(例如，铜箔)添加到开口或孔。
方法400还可包括将第一接合材料(例如，焊料)施加到底部金属片 (例如，铜箔)(420)，将成型的柔性间隔材料块和实心金属块放置在施加到底部金属片的第一接合材料上(430)。方法400还包括将第二接合材料(例如，焊料)施加到设置在底部金属片上的成型的柔性间隔材料块和实心金属块的顶部表面(440)，将顶部金属片(例如，铜箔)放置在第二接合材料上方(450)，以及使焊料回流并固化组件以形成混合间隔块 (460)。
图5A至图5I示出了以柔性间隔材料500块开始的通过方法400在不同组装阶段的混合间隔块(例如，混合间隔块140)。
图5A和图5B示出了可用于根据方法400制备混合间隔块140的柔性间隔材料500的起始块。在示例性实施方式中，柔性间隔材料500可具有直鳍片结构，即，由交替的矩形脊501和具有竖直侧壁的沟槽502制成的波状结构148。
图5A示出了具有例如矩形块尺寸D1xD2和厚度D3的柔性间隔材料 500的顶视图。在示例性实施方式中，尺寸D1和D2各自可大于约10毫米，并且厚度D3可在0.5毫米至3.0毫米的范围内。
图5B示出了柔性间隔材料500的起始块的剖视图，其描绘了具有厚度 D3的波状结构148的脊和沟槽。波状结构148可例如通过使厚度为t1的薄金属片(例如，铜片)形成波状以形成脊501和沟槽502来形成。在示例性实施方式中，厚度t1可在0.05毫米至3.0毫米的范围内。波状结构的每个单元(即，脊至脊的距离)可具有间距C。在示例性实施方式中，间距C可以在0.5毫米至2毫米的范围内。
图5C和图5D示出了可根据方法400用于混合间隔块140的实心材料块(例如，实心金属块142)。图5C示出了具有例如矩形块尺寸W1xL1 的实心金属块142的顶视图。图5D示出了具有例如厚度D4的实心金属块 142的侧视图。在示例性实施方式中，尺寸W1和L1各自可小于约50毫米，并且厚度D4可在0.5毫米至3.0毫米的范围内。
图5E示出了柔性间隔块144，该柔性间隔块已(从柔性间隔材料 500)成型为指定外部尺寸的混合间隔块(例如，在方法400的410处)。柔性间隔块144可例如具有对应于混合间隔块140的指定外部尺寸的宽度 W、长度L和厚度T。另外，切出柔性间隔块的开口内部部分145以容纳混合间隔块140的指定尺寸的实心金属块142。内部部分145可例如具有与实心金属块142(图5C)的尺寸匹配的矩形尺寸L1xW1。
图5F示出了施加到金属片146的第一接合材料(例如，焊料14)，该金属片可形成用于混合间隔块140中的柔性间隔块144和实心金属块142 的底部支撑件(例如，在方法400的420处)。
图5G示出了组装在底部金属片146上的柔性间隔块144和实心金属块 142，其中实心金属块142放置在柔性间隔块144中的孔(例如，开口内部部分145)中(例如，在方法400的430处)。
图5H示出了施加到设置在底部金属片146上的成型的柔性间隔材料块和实心金属块的顶部表面的第二接合材料(例如，焊料14)(例如，在方法400的440处)。
图5I示出了放置在图5F的组件的第二接合材料上方的顶部金属片 (例如，金属片147)(例如，在方法400的450处)。组件可被加热以用于焊料回流和固化，以将顶部金属片147和底部金属片146接合到组件部件，从而形成混合间隔块140。
在上文参考图5A至图5I所讨论的示例性实施方式中，柔性间隔材料 500具有直鳍片结构(即，由交替的矩形脊501和具有竖直侧壁的沟槽502 制成的波状结构148)。在其他实施方式中，柔性间隔材料500可具有其他类型的具有非竖直侧壁的柔性结构(例如，倾斜鳍片202、弯折鳍片203、弯曲鳍片204和S形鳍片205等，如例如图2B至图2F所示)。
图6示出了用于使用起始柔性材料组装混合间隔块(例如，混合间隔块140)的示例性方法600，该起始柔性材料具有柔性结构，该柔性结构具有非竖直壁(例如，具有S形鳍片205的结构)。在此类间隔材料中，柔性鳍片(例如，S鳍片)可预附接到底部箔片。
方法600包括将柔性间隔材料块成型为指定外部尺寸的混合间隔块 (610)，以及移除柔性间隔材料块的内部部分以形成可容纳指定尺寸的实心金属块的开口(620)，以及将竖直侧箔板耦接(例如，添加)到开口 (630)。
方法600还包括将底部箔片上的底部焊料层分配在开口中，并且将底部焊料层上的实心金属块放置在开口中(640)。方法600还包括将侧焊料层分配在位于竖直侧箔板和实心金属块之间的空间中，并且将顶部焊料层分配在组件的顶部上(650)，以及将顶部金属片(例如，铜箔)放置在组件上方(660)，以及使焊料回流并固化组件以形成混合间隔块(670)。
图7A至图7D示出了以具有S形鳍片的柔性间隔材料块开始的通过方法600在不同组装阶段的混合间隔块(例如，混合间隔块140)。
图7A示出了成型为特定外部尺寸的混合间隔块的柔性间隔材料700块的剖视图。柔性间隔材料700可具有S形鳍片结构(即，由具有非竖直侧面的交替的脊701和沟槽702制成并且由S形鳍片744形成的波状结构 748)。S形鳍片可附接到底部金属片746。
图7B示出了在移除块的内部部分以形成开口745并将竖直侧箔板747 添加到开口745之后柔性间隔材料700块的剖视图。开口745的尺寸可匹配实心金属块142的尺寸。
图7C示出了分配在底部金属片746上的焊料层14-1和在开口745中的放置在焊料层14-2上的实心金属块142。
图7D示出了开口745中的引入位于竖直侧箔板747与实心金属块142 之间的空间中的焊料层14-2，以及分配在组件顶部上的焊料层14-3。另外，将顶部金属片(例如，金属片147)放置在组件顶部上的焊料层14-3 上方。组件可被加热以用于焊料回流和焊料层14-1、14-2和14-3的固化，以将顶部金属片147和底部金属片146接合到组件部件，从而形成混合间隔块140。
在示例性实施方式中，然后本文所述的包括实心块部分和柔性块部分两者的混合间隔块可改善功率模块的可靠性。混合间隔块的柔性块部分可适应由部件之间的CTE失配引起的部件的机械位移，并且减小功率模块中的管芯应力和焊料剥离应变。实心块部分可用于满足功率模块的热性能要求和电性能要求。可通过调整实心块部分的尺寸、形状和材料来优化功率模块的机械性能、热性能和电性能。间隔件的柔性部分的设计(即波状形、鳍片形、Z形等)也可用于调节机械性能特性、热性能特性和电性能特性。
示例性功率模块可包括经由混合间隔块耦接到DSC衬底的一个或多个功率器件管芯(例如，IGBT和FRD)。混合间隔块可包括在尺寸上与单个管芯尺寸不同(即，更大或更小)的柔性间隔块。图8示出了表示单个管芯801、实心间隔块802和柔性间隔块803的块重叠以用于尺寸比较的图示。单个管芯801可具有特征尺寸A，实心间隔块802可具有特征尺寸B，并且柔性间隔块803可具有特征尺寸C。
在示例性实施方式中，管芯尺寸A可在约10毫米至14毫米的范围内，并且柔性间隔块尺寸C可在约12毫米至17毫米的范围内。另外，混合间隔块可包括在尺寸上与管芯尺寸A不同(例如，小于或等于)的实心间隔块。在示例性实施方式中，对于约10毫米至14毫米的范围内的管芯尺寸，实心间隔块尺寸B可例如在约6毫米至10毫米的范围内。
在上文参考图1至图8所讨论的混合间隔块(例如，混合间隔块140) 的示例性实施方式中，柔性间隔块围绕实心块部分。在管芯-间隔块组合 (例如，管芯-间隔块组合150)中，柔性间隔块朝向管芯边缘延伸并且可适应CTE失配应力，与管芯中心处的应力相比，该CTE失配应力可在管芯边缘处明显。多管芯功率模块中的每个管芯可耦接到相应管芯-间隔块组合。图9示出了例如可单独耦接到多管芯功率模块中的第一管芯(例如， IGBT)(未示出)和第二管芯(例如，FRD)(未示出)的混合间隔物 910和混合间隔物920。混合间隔件910可包括由耦接到第一管芯(例如， IGBT)的柔性间隔块914围绕的实心金属块912。混合间隔件920可包括由耦接到第二管芯(例如，FRD)的柔性间隔块924围绕的实心金属块 922。
在其他实施方式中，混合间隔材料(例如，直鳍片201、倾斜鳍片 202、弯折鳍片203、弯曲鳍片204和S形鳍片205)可以不同几何形状 (例如，除了在所有侧面上围绕单个实心金属块之外)结合到混合间隔块中。图10至图12示出了用于混合间隔块中的不同几何形状的混合间隔材料的示例。
图10示出了例如可单独耦接到多管芯功率模块中的第一器件管芯 1001(例如，IGBT)和第二器件管芯1002(例如，FRD)的混合间隔块 1010和1020的布置。第一器件管芯1001可包括信号焊盘区域1005，该信号焊盘区域包括与IGBT相关联的信号焊盘1001a。
混合间隔块1010可包括实心金属块1012和柔性间隔块1014。实心金属块1012在尺寸上可与器件管芯1001(例如，IGBT)相当。柔性间隔块 1014可为具有宽度WS的矩形条带。柔性间隔块1014作为条带可附接到实心金属块1012的一侧并从该侧延伸。柔性间隔块1014可从实心金属块 1012的一侧延伸以仅支撑(即，接合到)第一器件管芯1001的信号焊盘区域1005，而实心金属块1012可支撑管芯在管芯-间隔块组合中的其余部分。
在图10的示例中，间隔块1020(其与第二器件管芯1002(例如， FRD)形成管芯-间隔块组合)可仅包括实心金属块1012并且不包括柔性间隔块。
图11示出了例如可耦接到多管芯功率模块中的第一器件管芯1001 (例如，IGBT)和第二器件管芯1002(例如，FRD)两者的混合间隔块 1130。第一器件管芯1001可包括信号焊盘区域1005和源极焊盘1001b。第二器件管芯1001可包括源极焊盘1002b。混合间隔块1130可包括可与第一器件管芯1001和第二器件管芯1002形成双管芯-间隔块组合的单个实心金属块1132。与混合间隔块1010(图10)类似，混合间隔块1030还可包括从实心金属块1130的一侧延伸以仅支撑第一器件管芯1001的信号焊盘区域1005的柔性间隔块1014。
图12示出了例如可耦接到多管芯功率模块中的第一器件管芯1001 (例如，IGBT)和第二器件管芯1002(例如，FRD)两者的混合间隔块 1240。与混合间隔块1010和1020(图10)类似，混合间隔块1240可包括可分别单独耦接到第一器件管芯1001和第二器件管芯1002的第一子块 (即，实心金属块1212)和第二子块(即，实心金属块1222)。混合间隔块1240还可包括单个柔性间隔块1214，该柔性间隔块支撑第一器件管芯1001的信号焊盘区域1005并且连续远离信号焊盘区域1005延伸以围绕实心金属块1212和实心金属块1222。
图13示出了用于使用功率模块中的柔性间隔块来适应例如由于CTE 失配而可能发生的部件位移的示例性方法。功率模块可包括一个或多个器件管芯(例如，FRD、IGBT等)。
方法1300包括将半导体器件管芯的内部部分耦接到实心间隔块 (1310)，邻近实心间隔块设置柔性间隔块(1320)，以及将半导体器件管芯的边缘部分耦接到柔性间隔块(1330)。
在方法1300中，邻近实心间隔块设置柔性间隔块可包括将实心间隔块设置在柔性间隔块的开口中。另外，作为另外一种选择或除此之外，邻近实心间隔块设置柔性间隔块可包括将柔性间隔块作为附接到实心间隔块的一侧并从该侧延伸的条带设置。
在方法1300中，将半导体器件管芯的边缘部分耦接到柔性间隔块可包括在器件管芯的边缘处将柔性间隔块耦接到信号焊盘区域。
在本文所讨论的一些示例性实施方式中，导热衬底是直接接合铜 (DBC)衬底。
在本文所讨论的一些示例性实施方式中，半导体器件管芯包括快速恢复二极管(FRD)或绝缘栅双极晶体管(IGBT)中的至少一者。
在本文所讨论的一些示例性实施方式中，第一器件管芯包括绝缘栅双极晶体管(IGBT)。
应当理解，在前述描述中，当元件诸如层、区域、衬底或部件被提及为在另一个元件上，连接到另一个元件，电连接到另一个元件，耦接到另一个元件，或电耦接到另一个元件时，元件可以直接地在另一个元件上，连接到或耦接到另一个元件上，或者可以存在一个或多个中间元件。相反，当元件被提及直接在另一个元件或层上、直接连接到另一个元件或层、或直接耦接到另一个元件或层时，不存在中间元件或层。虽然在整个具体实施方式中可能不会使用术语直接在…上、直接连接到…、或直接耦接到…，但是被示为直接在元件上、直接连接或直接耦接的元件能以此类方式提及。本申请的权利要求书(如果存在的话)可被修订以叙述在说明书中描述或者在附图中示出的示例性关系。
如在本说明书和权利要求书中所使用的，除非根据上下文明确地指出特定情况，否则单数形式可包括复数形式。除了附图中所示的取向之外，空间相对术语(例如，在…上方、在…上面、在…之上、在…下方、在…下面、在…之下、在…之以下等)旨在涵盖器件在使用或操作中的不同取向。在一些实施方式中，在…上面和在…下面的相对术语可分别包括竖直地在…上面和竖直地在…下面。在一些实施方式中，术语邻近能包括横向邻近或水平邻近。
一些实施方式可使用各种半导体处理和/或封装技术来实现。一些实施方式可使用与半导体衬底相关联的各种类型的半导体处理技术来实现，该半导体衬底包含但不限于，例如硅(Si)、砷化镓(GaAs)、氮化镓 (GaN)、碳化硅(SiC)等。
虽然所描述的实施方式的某些特征已经如本文所述进行了说明，但是本领域技术人员现在将想到许多修改形式、替代形式、变化形式和等同形式。因此，应当理解，所附权利要求书旨在涵盖落入实施方式的范围内的所有此类修改形式和变化形式。应当理解，这些修改形式和变化形式仅仅以举例而非限制的方式呈现，并且可以进行形式和细节上的各种变化。除了相互排斥的组合以外，本文所述的装置和/或方法的任何部分可以任意组合进行组合。本文所述的实施方式可包括所描述的不同实施方式的功能、部件和/或特征的各种组合和/或子组合。

Claims (12)

1.一种模块，包括：
间隔块，所述间隔块包括实心间隔块和邻近柔性间隔块；
导热衬底，所述导热衬底耦接到所述间隔块的第一侧；
半导体器件管芯，所述半导体器件管芯耦接到所述间隔块的与所述第一侧相背对的第二侧；以及
所述半导体器件管芯的内部部分耦接到所述实心间隔块，并且所述半导体器件管芯的外部部分耦接到所述邻近柔性间隔块。
2.根据权利要求1所述的模块，其中所述实心间隔块为从所耦接的半导体器件管芯到所述导热衬底的热流动提供热通路，
所述邻近柔性间隔块被配置为适应由热膨胀系数(CTE)失配引起的所述模块中的所述半导体器件管芯的机械位移。
3.根据权利要求1所述的模块，其中所述邻近柔性间隔块具有波状结构，所述波状结构由直鳍片、倾斜鳍片、弯折鳍片、弯曲鳍片或S形鳍片中的至少一者制成，并且其中所述邻近柔性间隔块至少部分地围绕所述实心间隔块。
4.根据权利要求1所述的模块，其中所述邻近柔性间隔块是附接到所述实心间隔块的一侧并从所述一侧朝向所述器件管芯的边缘延伸的条带。
5.根据权利要求1所述的模块，其中所述邻近柔性间隔块在所述器件管芯的所述边缘处耦接到信号焊盘区域。
6.根据权利要求1所述的模块，其中所述实心间隔块和所述邻近柔性间隔块设置在多个金属片之间并通过焊料在所述金属片之间固定地耦接到位。
7.一种方法，包括：
将半导体器件管芯的内部部分耦接到实心间隔块；
邻近所述实心间隔块设置柔性间隔块；以及
将所述半导体器件管芯的边缘部分耦接到所述柔性间隔块。
8.根据权利要求7所述的方法，其中邻近所述实心间隔块设置所述柔性间隔块包括以下操作中的至少一者：
将所述实心间隔块设置在所述柔性间隔块中的开口中；以及
将所述柔性间隔块设置为附接到所述实心间隔块的一侧并从所述一侧延伸的条带。
9.根据权利要求8所述的方法，其中将所述半导体器件管芯的所述边缘部分耦接到所述柔性间隔块包括：在所述器件管芯的所述边缘处将所述柔性间隔块耦接到信号焊盘区域。
10.一种模块，包括：
第一器件管芯和第二器件管芯，所述第一器件管芯具有包括至少一个信号焊盘的边缘部分；和
间隔块，所述间隔块包括耦接到柔性间隔块的实心间隔块，所述实心间隔块耦接到所述第一器件管芯和所述第二器件管芯，所述柔性间隔块耦接到包括至少一个信号焊盘的所述边缘部分。
11.根据权利要求10所述的模块，其中所述实心间隔块包括耦接到所述第一器件管芯的第一子块和耦接到所述第二器件管芯的第二子块，并且所述柔性间隔件至少部分地围绕所述第一子块并且至少部分地围绕所述第二子块。
12.根据权利要求11所述的模块，其中耦接到所述第一器件管芯的所述边缘部分的所述柔性间隔块连续地延伸远离所述边缘部分，以便至少部分地围绕所述第一子块并且至少部分地围绕所述第二子块。
CN202110072148.6A 2020-02-07 2021-01-20 与使用混合间隔件的功率模块相关的结构和方法 Pending CN113257760A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/784,999 US11282764B2 (en) 2020-02-07 2020-02-07 Structure and method related to a power module using a hybrid spacer
US16/784,999 2020-02-07

Publications (1)

Publication Number Publication Date
CN113257760A true CN113257760A (zh) 2021-08-13

Family

ID=77177552

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110072148.6A Pending CN113257760A (zh) 2020-02-07 2021-01-20 与使用混合间隔件的功率模块相关的结构和方法

Country Status (2)

Country Link
US (3) US11282764B2 (zh)
CN (1) CN113257760A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11037917B1 (en) * 2019-12-11 2021-06-15 Littelfuse, Inc. Semiconductor device module and method of assembly
US11854935B2 (en) * 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443399B1 (ko) * 2001-10-25 2004-08-09 삼성전자주식회사 보이드가 형성된 열 매개 물질을 갖는 반도체 패키지
JP4016271B2 (ja) 2003-03-26 2007-12-05 株式会社デンソー 両面冷却型半導体モジュール
US9425124B2 (en) * 2012-02-02 2016-08-23 International Business Machines Corporation Compliant pin fin heat sink and methods
US8736048B2 (en) * 2012-02-16 2014-05-27 International Business Machines Corporation Flexible heat sink with lateral compliance
US9041192B2 (en) * 2012-08-29 2015-05-26 Broadcom Corporation Hybrid thermal interface material for IC packages with integrated heat spreader
KR101459857B1 (ko) * 2012-12-27 2014-11-07 현대자동차주식회사 히트싱크 일체형 양면 냉각 파워모듈
US9275926B2 (en) 2013-05-03 2016-03-01 Infineon Technologies Ag Power module with cooling structure on bonding substrate for cooling an attached semiconductor chip
KR101755769B1 (ko) * 2014-10-29 2017-07-07 현대자동차주식회사 양면 냉각 파워 모듈 및 이의 제조 방법
US10215504B2 (en) * 2015-04-06 2019-02-26 International Business Machines Corporation Flexible cold plate with enhanced flexibility
JP6862896B2 (ja) * 2017-02-17 2021-04-21 富士電機株式会社 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
US20240136247A1 (en) 2024-04-25
US11842942B2 (en) 2023-12-12
US20220208637A1 (en) 2022-06-30
US20210249329A1 (en) 2021-08-12
US11282764B2 (en) 2022-03-22

Similar Documents

Publication Publication Date Title
KR102239259B1 (ko) 고효율 열 경로 및 몰딩된 언더필을 구비한 적층형 반도체 다이 조립체
KR102490814B1 (ko) 반도체 장치
US20240136247A1 (en) Structure and method related to a power module using a hybrid spacer
US11387159B2 (en) Chip package
US20160329304A1 (en) Semiconductor device and method of manufacturing semiconductor device
JP2010251408A (ja) 半導体装置及びその製造方法並びに電子装置
US20100320584A1 (en) Semiconductor chip laminated body
US11127651B2 (en) High power module semiconductor package with multiple submodules
US11862542B2 (en) Dual side cooling power module and manufacturing method of the same
JP2016092300A (ja) 半導体装置及び半導体装置の製造方法
EP3739624A1 (en) Semiconductor arrangement with a compressible contact element encapsulated between two carriers and corresponding manufacturing method
CN114005812A (zh) 一种扇出型封装结构及其构造方法
JP6406996B2 (ja) 半導体装置
US20230253393A1 (en) Dual cool power module with stress buffer layer
US11735557B2 (en) Power module of double-faced cooling
KR101626534B1 (ko) 반도체 패키지 및 그 제조 방법
KR101561920B1 (ko) 반도체 패키지
US20210066174A1 (en) Semiconductor device package assemblies and methods of manufacture
CN112670187A (zh) 芯片封装结构及其形成方法
US20140077388A1 (en) Semiconductor device and method of manufacturing the same
WO2023068096A1 (ja) 半導体モジュール及び半導体モジュールの製造方法
KR102260662B1 (ko) 체결형 스페이서를 이용한 양면냉각모듈패키지 및 그의 제조방법
KR102487625B1 (ko) 양면 냉각 파워 모듈 패키지
US11646249B2 (en) Dual-side cooling semiconductor packages and related methods
US20240178113A1 (en) Electronic device and electronic device manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination