CN113227935B - 异步asic - Google Patents
异步asic Download PDFInfo
- Publication number
- CN113227935B CN113227935B CN201980085678.5A CN201980085678A CN113227935B CN 113227935 B CN113227935 B CN 113227935B CN 201980085678 A CN201980085678 A CN 201980085678A CN 113227935 B CN113227935 B CN 113227935B
- Authority
- CN
- China
- Prior art keywords
- clock
- data
- circuit
- phase
- candidates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411262678.7A CN119126919A (zh) | 2018-10-24 | 2019-10-23 | 异步asic |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862750180P | 2018-10-24 | 2018-10-24 | |
| US62/750,180 | 2018-10-24 | ||
| PCT/US2019/057723 WO2020086760A2 (en) | 2018-10-24 | 2019-10-23 | Asynchronous asic |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411262678.7A Division CN119126919A (zh) | 2018-10-24 | 2019-10-23 | 异步asic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113227935A CN113227935A (zh) | 2021-08-06 |
| CN113227935B true CN113227935B (zh) | 2024-09-13 |
Family
ID=70331255
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980085678.5A Active CN113227935B (zh) | 2018-10-24 | 2019-10-23 | 异步asic |
| CN202411262678.7A Pending CN119126919A (zh) | 2018-10-24 | 2019-10-23 | 异步asic |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411262678.7A Pending CN119126919A (zh) | 2018-10-24 | 2019-10-23 | 异步asic |
Country Status (5)
| Country | Link |
|---|---|
| US (5) | US11487316B2 (https=) |
| EP (2) | EP3871062B1 (https=) |
| JP (6) | JP7546559B2 (https=) |
| CN (2) | CN113227935B (https=) |
| WO (1) | WO2020086760A2 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113227935B (zh) | 2018-10-24 | 2024-09-13 | 奇跃公司 | 异步asic |
| EP4123955B1 (en) * | 2020-04-13 | 2025-08-06 | Huawei Technologies Co., Ltd. | Method for determining clock and related apparatus |
| US20240371422A1 (en) * | 2021-09-10 | 2024-11-07 | SK Hynix Inc. | Data receiving circuit for chiplet based storage architectures |
| US12578753B2 (en) * | 2023-01-27 | 2026-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Clock aligning circuit and methods for operating the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7433439B1 (en) * | 2002-12-20 | 2008-10-07 | Cypress Semiconductor Corp. | Apparatus, system, and method for synchronizing signals received by one or more system components |
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-
2019
- 2019-10-23 CN CN201980085678.5A patent/CN113227935B/zh active Active
- 2019-10-23 US US17/288,457 patent/US11487316B2/en active Active
- 2019-10-23 WO PCT/US2019/057723 patent/WO2020086760A2/en not_active Ceased
- 2019-10-23 CN CN202411262678.7A patent/CN119126919A/zh active Pending
- 2019-10-23 EP EP19874942.6A patent/EP3871062B1/en active Active
- 2019-10-23 EP EP25216745.7A patent/EP4672660A3/en active Pending
- 2019-10-23 JP JP2021522076A patent/JP7546559B2/ja active Active
-
2022
- 2022-09-22 US US17/950,808 patent/US11619965B2/en active Active
- 2022-10-13 JP JP2022164507A patent/JP7546635B2/ja active Active
-
2023
- 2023-02-27 US US18/175,466 patent/US11747856B2/en active Active
- 2023-07-25 US US18/358,623 patent/US12135580B2/en active Active
-
2024
- 2024-03-15 JP JP2024040843A patent/JP7565467B2/ja active Active
- 2024-07-15 US US18/773,471 patent/US20240370051A1/en active Pending
- 2024-09-06 JP JP2024153947A patent/JP7770497B2/ja active Active
- 2024-10-11 JP JP2024178926A patent/JP7825684B2/ja active Active
-
2026
- 2026-01-21 JP JP2026008500A patent/JP2026063316A/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7433439B1 (en) * | 2002-12-20 | 2008-10-07 | Cypress Semiconductor Corp. | Apparatus, system, and method for synchronizing signals received by one or more system components |
Also Published As
| Publication number | Publication date |
|---|---|
| US11487316B2 (en) | 2022-11-01 |
| US12135580B2 (en) | 2024-11-05 |
| JP2024071432A (ja) | 2024-05-24 |
| JP7546559B2 (ja) | 2024-09-06 |
| WO2020086760A3 (en) | 2020-07-30 |
| CN119126919A (zh) | 2024-12-13 |
| US20230018203A1 (en) | 2023-01-19 |
| JP7546635B2 (ja) | 2024-09-06 |
| EP3871062B1 (en) | 2025-11-26 |
| US20210382520A1 (en) | 2021-12-09 |
| EP4672660A2 (en) | 2025-12-31 |
| CN113227935A (zh) | 2021-08-06 |
| JP2024178214A (ja) | 2024-12-24 |
| EP4672660A3 (en) | 2026-04-08 |
| EP3871062A2 (en) | 2021-09-01 |
| EP3871062A4 (en) | 2021-12-29 |
| US11747856B2 (en) | 2023-09-05 |
| US20230205257A1 (en) | 2023-06-29 |
| US11619965B2 (en) | 2023-04-04 |
| JP7825684B2 (ja) | 2026-03-06 |
| WO2020086760A2 (en) | 2020-04-30 |
| JP2026063316A (ja) | 2026-04-10 |
| JP2022183237A (ja) | 2022-12-08 |
| US20240370051A1 (en) | 2024-11-07 |
| JP7770497B2 (ja) | 2025-11-14 |
| US20230367361A1 (en) | 2023-11-16 |
| JP7565467B2 (ja) | 2024-10-10 |
| JP2022505662A (ja) | 2022-01-14 |
| JP2025004229A (ja) | 2025-01-14 |
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| GR01 | Patent grant |