CN113205760B

CN113205760B - Silicon-based micro display and driving circuit thereof

Info

Publication number: CN113205760B
Application number: CN202110475250.0A
Authority: CN
Inventors: 冉峰
Original assignee: Wuxi Tanggu Semiconductor Co ltd
Current assignee: Wuxi Tanggu Semiconductor Co ltd
Priority date: 2021-04-29
Filing date: 2021-04-29
Publication date: 2023-12-01
Anticipated expiration: 2041-04-29
Also published as: CN113205760A

Abstract

The application discloses a silicon-based micro display and a driving circuit thereof. The driving circuit of the silicon-based micro display comprises: the device comprises a signal interface, a data separation module, a row driving circuit, a plurality of column driving circuits and a plurality of monochromatic pixel arrays, wherein the number of the monochromatic pixel arrays is the same as that of the column driving circuits; each single-color pixel array comprises a plurality of pixel circuits which are used for driving single-color sub-pixels and are arranged in an array manner; the input end of the data separation module and the input end of the row driving circuit are electrically connected with the signal interface, the output end of the data separation module is electrically connected with the plurality of column driving circuits respectively, the output end of the row driving circuit is electrically connected with the scanning lines of the plurality of monochromatic pixel arrays respectively, and the output end of each column driving circuit is electrically connected with the data line of a corresponding monochromatic pixel array. The embodiment of the application can drive different monochromatic pixel arrays through different column driving circuits, can effectively improve the driving capability of the pixel arrays, reduces the difficulty of circuit design and reduces the cost.

Description

Silicon-based micro display and driving circuit thereof

Technical Field

The application relates to the technical field of display, in particular to a silicon-based micro display and a driving circuit thereof.

Background

A silicon-based microdisplay is a special display based on silicon semiconductor technology that has a small physical size itself and forms a large field of view by optical magnification. The existing silicon-based micro-display generally comprises a driving circuit and a light-emitting device, wherein the driving circuit generally comprises a pixel array formed by pixels with various colors, a row driving circuit and a column driving circuit for driving the pixel array, the uniform row driving circuit and column driving circuit are adopted to realize the driving of the pixel array, the driving capability is poor, the circuit design is complex, and the cost is high.

Disclosure of Invention

The embodiment of the application provides a silicon-based micro display and a driving circuit thereof, which can solve the technical problem of complex circuit design in the prior art.

In a first aspect, an embodiment of the present application provides a driving circuit of a silicon-based micro display, including:

the device comprises a signal interface, a data separation module, a row driving circuit, a plurality of column driving circuits and a plurality of monochromatic pixel arrays, wherein the number of the monochromatic pixel arrays is the same as that of the column driving circuits; each single-color pixel array comprises a plurality of pixel circuits which are used for driving single-color sub-pixels and are arranged in an array manner;

the input end of the data separation module and the input end of the row driving circuit are electrically connected with the signal interface, the output end of the data separation module is electrically connected with the plurality of column driving circuits respectively, the output end of the row driving circuit is electrically connected with the scanning lines of the plurality of monochromatic pixel arrays respectively, and the output end of each column driving circuit is electrically connected with the data line of a corresponding monochromatic pixel array;

The signal interface is used for: receiving a timing control signal and first video data of a target video;

the data separation module is used for: extracting a plurality of color components in the first video data, generating column pixel data of each color component, and transmitting the plurality of column pixel data to a plurality of column driving circuits respectively;

the row driving circuit is used for: generating a row driving signal according to the time sequence control signal, and transmitting the row driving signal to a plurality of monochromatic pixel arrays through a scanning line;

the column driving circuit is used for: column pixel data is transmitted to a corresponding one of the monochrome pixel arrays through the data lines according to the timing control signal.

In a second aspect, an embodiment of the present application provides a silicon-based microdisplay, including: a light emitting device and a driving circuit of a silicon-based micro display provided in the first aspect of the embodiment of the present application;

the driving circuit comprises a plurality of monochromatic pixel arrays distributed in a plurality of monochromatic display areas, wherein each monochromatic pixel array is electrically connected with a light emitting device of one color and is used for driving the light emitting device of the color to emit light

The power module and the main board provided by the embodiment of the application have the following beneficial effects:

the silicon-based micro-display and the driving circuit thereof provided by the embodiment of the application are provided with the data separation module, a plurality of corresponding column driving circuits and a plurality of monochromatic pixel arrays.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar features, and in which the figures are not to scale.

FIG. 1 is a schematic diagram of a silicon-based micro-display according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a structural frame of another silicon-based micro-display according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a first driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 4 is a timing diagram of driving signals for different monochrome pixel arrays according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a second driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a third driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a fourth driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a scanning timing sequence for scanning pixel circuits in different monochrome pixel arrays according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a scanning timing sequence for scanning pixel circuits of different rows in the same monochrome pixel array according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a fifth driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a sixth driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a seventh driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 13 is a schematic diagram showing the structure frame and connection relationship of a shift register set, a comparator array and a digital switch array according to an embodiment of the present application;

FIG. 14 is a schematic diagram of a structural frame of an eighth driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 15 is a timing diagram of a row shutdown signal according to an embodiment of the present application;

FIG. 16 is a timing diagram of another row shutdown signal according to an embodiment of the application;

FIG. 17 is a schematic diagram of a ninth driving circuit of a silicon-based micro-display according to an embodiment of the present application;

FIG. 18 is a schematic diagram of a clock tree according to an embodiment of the present application;

FIG. 19 is a schematic diagram of a parallel shift register set according to an embodiment of the present application;

FIG. 20 is a timing diagram of the shift enable signal, the data latch signal, the column driver signal, and the row driver signal according to an embodiment of the present application.

Detailed Description

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

First, several terms related to the present application are described and explained:

ping-pong operation is a data buffering optimization design technology in FPGA development, and can be regarded as another form of pipeline technology, and when an input data stream passes through an input data stream selection unit, the input data stream is distributed into two data buffering modules in a time-division manner, and the data buffering modules can be any memory modules in FPGA (Field-Programmable Gate Array, field programmable gate array) such as dual-port RAM (Random Access Memory ), single-port RAM and FIFO (First Input First Output, first-in first-out) and the like.

Setup time (Tsu: set up time): refers to the time that the data is stable before the rising edge of the clock signal of the flip-flop arrives, if the setup time is insufficient, the data will not be driven into the flip-flop stable at this rising edge of the clock, tsu refers to this minimum settling time.

Hold time (Th: hold time): the term "hold time" refers to the time that data is stable after the rising edge of the clock signal of the flip-flop arrives, and if the hold time is insufficient, data cannot be driven into the flip-flop as well, and Th refers to the minimum hold time.

In order to solve the problems in the prior art, the embodiment of the application provides a power module and a main board. The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments.

An embodiment of the present application provides a silicon-based microdisplay, as shown in fig. 1, including: a light emitting device (not shown in fig. 1) and a driving circuit of a silicon-based micro display. The plurality of single-color pixel arrays 110 in the driving circuit of the silicon-based micro-display are distributed in a plurality of single-color display areas (such as a red display area, a green display area and a blue display area shown in fig. 1), and each single-color pixel array 110 is electrically connected to a light emitting device of one color for driving the light emitting device of the color to emit light.

In one example, the silicon-based micro display provided by the embodiment of the application may further include: at least one common electrode; when the silicon-based microdisplay includes a common electrode, the plurality of monochrome pixel arrays 110 are all electrically connected to the common electrode; when the silicon-based microdisplay includes more than two common electrodes, each single-color pixel array 110 is electrically connected to a corresponding one of the common electrodes.

In a specific example, if the number of the monochrome pixel array 110 and the common electrode is the same, the monochrome pixel array 110 and the common electrode may be connected in one-to-one correspondence; if the number of common electrodes is smaller than the number of monochrome pixel arrays 110, a part of the monochrome pixel arrays 110 are connected to the same common electrode. The provision of more than two common electrodes is advantageous for adjusting the voltage or current of each pixel array separately.

In one example, the voltage or current of the pixel array may be adjusted by: the grid voltage of the driving transistor of each pixel circuit in the pixel array is regulated, so that the output current of the driving transistor can be regulated, and the output current drives the light emitting device to emit light, thereby achieving the purpose of regulating the light emitting brightness of the light emitting device.

The light emitting device of the embodiment of the application can be an organic electroluminescent device, a semiconductor light emitting device or a liquid crystal display device.

In one example, as shown in fig. 2, the silicon-based micro display provided in the embodiment of the present application may further include: and a timing controller.

The input end of the time schedule controller is connected with first video data of the target video, and the output end of the time schedule controller is electrically connected with the signal interface 120 in the driving circuit; the timing controller is used for generating timing control signals for video data according to the first video data and outputting the first video data and the timing control signals. The first video data is video data input into the time sequence controller according to pixel points of each frame image of the target video, and the video data comprises image data of each frame image of the target video.

In one example, the timing controller is further configured to increase the amplitude of the first video data when the timing control signal includes a line-off signal and the time of the active level of the line-off signal is less than a preset value, obtain the second video data, and output the second video data.

In one example, as shown in fig. 2, the timing controller may include: the image processing module 210, the frame buffer controller 220, and the scan circuit 230 are electrically connected in this order. The image processing module 210, the frame buffer controller 220, and the scan circuit 230 may be integrated within an ASIC (Application Specific Integrated Circuit ) or an FPGA (Field-Programmable Gate Array, field programmable gate array).

The input terminal of the image processing module 210 is used as the input terminal of the timing controller, and is connected to the first video data of the target video, and the input terminal of the image processing module 210 may include any one of the following interfaces: RGB (red green blue), MIPI (Mobile Industry Processor Interface), mobile industry processor interface, HDMI (High Definition Multimedia Interface ), VGA (Video Graphics Array cable, a D-type interface), AV (composite video interface), DVI (Digital Visual Interface, digital video interface), LVDS (Low Voltage Differential Signaling, low voltage differential Signal), mini-LVDS (micro low voltage differential Signal), DP (DisplayPort, display interface)/eDP (Emedded DisplayPot, embedded display interface) interface, an output end of image processing is electrically connected with an input end of a frame buffer controller 220, a first output end of the frame buffer controller 220 is electrically connected with an input end of a scanning circuit 230, a second output end of the frame buffer controller is electrically connected with a frame buffer, and an output end of the scanning circuit 230 is electrically connected with a driving circuit of a silicon-based micro display.

The image processing module 210 may perform at least one of the following image preprocessing on each image data in the first video data: the first video data meets specific requirements by adjusting the size of the image, adjusting the brightness, adjusting the contrast, correcting the gamma, and the like.

The frame buffer controller 220 may output the image data after image preprocessing to the frame buffer through the first output terminal in a bit plane manner, and may also read the image data in the frame buffer in a bit plane manner and output the read image data to the scan circuit 230 through the second output terminal; the frame buffer may store the received image data per bit plane.

The scan circuit 230 may receive image data output from the frame buffer controller 220, and the frame buffer control sequence output and the bit plane scan circuit 230 may be ping-pong operations.

In one example, when there are a plurality of frame buffers and the frame buffer controller 220 is storing image data in one of the frame buffers, the scan circuit 230 may read another frame buffer through the frame buffer controller 220, thereby increasing the bandwidth speed.

In one example, for example, in a digital drive mode, scan circuitry 230 may include bit plane scan circuitry.

After the bit plane scanning circuit acquires the image data, three bit plane signals of which the image data are divided into different color components can be transmitted to a driving circuit of the silicon-based micro-display, each pixel data in the image data can be decomposed into three data of different color components, each data can be sequentially transmitted in a bit plane mode, and the transmission mode can be a TTL (Transistor Transistor Logic, transistor-transistor logic) level mode or a low-voltage differential pair mode. The three bit plane signals output by the bit plane scanning circuit can be respectively transmitted to the driving circuit of the silicon-based micro-display through three transmission lines, and can also be transmitted to the driving circuit of the silicon-based micro-display through one transmission line shown in fig. 2 in the form of mixed bit plane signals so as to improve the transmission efficiency.

The different color components in embodiments of the present application may be determined according to at least one of the following color modes: RGB (red green blue, respectively), CMYK (cyan magenta yellow black, respectively), YUV (Y brightness, UV chromaticity). Hereinafter, RGB will be mainly exemplified.

In one example, the bit plane scanning circuit may further generate a timing control signal according to the acquired image data and transmit the timing control signal to a driving circuit of the silicon-based micro display, where the timing control signal may be transmitted in a bit plane manner, and the transmission manner may be a TTL level manner or a low voltage differential pair manner.

In another example, the scan circuit 230 may include a digital-to-analog scan controller, such as in an analog drive mode or in a digital-to-analog hybrid drive mode.

After the image data output by the frame buffer controller 220 is processed by the digital-to-analog scan controller, a high-frequency analog driving signal can be output to the driving circuit of the silicon-based micro-display to increase the scanning rate of the pixels.

In one example, the timing controller may not include the image processing module 210, i.e., no image preprocessing is required.

In one example, the scan circuitry 230 may include a state machine that may employ the same timing operations on R, B, G data in the bit plane to synchronize the timing of these data. The timing operation includes reading data from the frame buffer one by the frame buffer controller 220, and the reading order may be row by column or random. In another example, the R, G, B data for the same pixel is configured to be read out at the same time when the R, G, B data is read out row by row or randomly.

The frame buffer in the embodiment of the present application may be any one of SRAM (Static Random-Access Memory), SDRAM (Synchronous Dynamic Random-Access Memory), DDR SDRAM (Double Data Rate Memory SDRAM, double rate synchronous dynamic Random Access Memory). In one example, if the frame buffer is SRAM, the SRAM may be integrated within the FPGA or ASIC, and if the frame buffer is SDRAM or DDR, the SDRAM or DDR may be provided in a separate chip.

An embodiment of the present application provides a driving circuit of a silicon-based micro-display, as shown in fig. 3, the driving circuit includes: a signal interface 120, a data separation module 130, a row driving circuit 140, a plurality of column driving circuits 150, and a plurality of monochrome pixel arrays 110 equal in number to the plurality of column driving circuits 150; each of the monochrome pixel arrays 110 includes a plurality of pixel circuits for driving one type of monochrome sub-pixels and arranged in an array.

The input end of the data separation module 130 and the input end of the row driving circuit 140 are electrically connected to the signal interface 120, the output end of the data separation module 130 is electrically connected to the plurality of column driving circuits 150, the output end of the row driving circuit 140 is electrically connected to the scanning lines of the plurality of monochrome pixel arrays 110, and the output end of each column driving circuit 150 is electrically connected to the data line of a corresponding one of the monochrome pixel arrays 110.

The signal interface 120 is used for: receiving a timing control signal and first video data of a target video; the data separation module 130 is configured to: extracting a plurality of color components in the first video data, generating column pixel data of each color component, and transmitting the plurality of column pixel data to the plurality of column driving circuits 150, respectively; the row driving circuit 140 is configured to: generating a row driving signal according to the timing control signal, and transmitting the row driving signal to the plurality of monochrome pixel arrays 110 through the scan lines; the column driving circuit 150 is configured to: column pixel data is transmitted to a corresponding one of the monochrome pixel arrays 110 through the data lines according to the timing control signal.

In one example, the first video data received by the data separation module 130 may be a bit plane signal output by a bit plane scan circuit or an analog driving signal output by a digital-to-analog scan controller.

In one example, the signal interface 120, the row driver circuit 140, the column driver circuit 150, and the monochrome pixel array 110 are integrated on the same single crystal silicon substrate; each single-color pixel array 110 is tiled on a single-crystal silicon substrate, and a gap is reserved between two adjacent single-color pixel arrays 110. The monocrystalline silicon substrate can enable the integration level of the driving circuit of the silicon-based micro-display to be higher, and a gap is reserved between two adjacent monochromatic pixel arrays 110, so that the light-emitting device can be conveniently manufactured.

In one example, the top electrode of each single-color pixel array 110, each metal layer, and the semiconductor device layer, etc., may be fabricated on a single-crystal silicon substrate at a time using the same semiconductor process.

In one example, a gap of not less than 1 pixel is left between two adjacent monochrome pixel arrays 110 to leave sufficient space for fabricating a light emitting device, such as in the case of an LED. In another example, a gap of not less than 10 pixels is left between two adjacent single color pixel arrays 110 to leave enough space for fabricating a light emitting device, such as in the case of an OLED.

In one example, the signal interface 120 in an embodiment of the present application may include a video signal interface 120 and a timing signal interface 120, the video signal interface 120 may be used to receive first video data of a target video, and the timing interface may be used to receive a timing control signal. The first video data received by the video signal interface 120 may be original video data of the target video, or may be video data of the target video, which is subjected to image preprocessing by the timing controller and transmitted in a bit plane.

In one example, the video signal interface 120 in an embodiment of the present application may be an analog circuit compatible with video signals, such as any of the following interfaces: RGB, MIPI, HDMI, VGA, AV, DVI, LVDS, mini-LVDS, DP/eDP.

In one example, the timing of the pixel data of the plurality of columns output by the data separation module 130 is the same, and the timing of the driving signals output by the pixel circuits at the same array position in each single-color pixel array 110 is the same, so that the light emitting devices of different colors of the same pixel point can be driven at the same time, and the light emitting devices of different colors of the same pixel point can emit light synchronously.

Taking the driving circuit shown in fig. 3 as an example, if each sub-pixel in the red pixel array, the green pixel array and the blue pixel array is a sub-pixel of each of the pixels P0 to Pn and L0 to Lm, for the red sub-pixel, the green sub-pixel and the blue sub-pixel included in the same pixel in the respective pixel arrays (for example, the i-th row and the j-th column), the timings of the driving signals for the red pixel array, the green pixel array and the blue pixel array are the same, and are all turned on or turned off simultaneously from P0 to Pn and from L0 to Lm, as shown in fig. 4.

In one example, delay times of the transmission of the plurality of column pixel data to the plurality of column driving circuits 150 by the data separation module 130 are equal, and an attenuation amplitude of the signal when each column pixel data is transmitted to a corresponding one of the column driving circuits 150 by the data separation module 130 is less than or equal to a preset attenuation amplitude threshold.

In one example, the attenuation amplitude threshold may be preset according to actual requirements or empirical values, for example, a value that does not affect the normal function of the circuit is set as the attenuation amplitude threshold, and in one specific example, the attenuation amplitude threshold may be set to 30% so that the amplitude of the attenuated signal (the highest voltage of the signal) is not lower than 70% of the amplitude of the attenuated signal.

In one example, at least one of the following effects may be achieved between the data separation module 130 and the plurality of column driving circuits 150 by adjusting at least one of routing, device type, and circuit parasitic parameters between the data separation module 130 and the plurality of column driving circuits 150: the routing lengths are equal, the device types are the same, and the parasitic parameters of the circuits are equal, so that the delay time of the pixel data of the plurality of columns transmitted to the plurality of column driving circuits 150 by the data separation module 130 is equal; the signal attenuation between each column of pixel data from the data separation module 130 to a corresponding column driver circuit 150 can be reduced by reducing the interference between the data separation module 130 and each column driver circuit 150, so as to achieve the purpose of no signal attenuation.

In one example, the data separation module 130 includes: a decoding unit and a signal processing unit.

The decoding unit is used for decoding the first video DATA, and separating column pixel DATA of different color components (RED column pixel DATA red_data, GREEN column pixel DATA green_data and BLUE column pixel DATA blue_data as shown in fig. 3).

When the first video data is a bit-plane signal (digital signal) outputted from the bit-plane scanning circuit, the second signal processing unit is configured to perform at least one signal process of waveform shaping, data grouping, and parallel-to-serial conversion (i.e., parallel data is converted into serial data) on column pixel data (digital signal at this time) separated based on the bit-plane signal.

When the first video data is an analog driving signal output by the digital-analog scanning controller, the signal processing unit is configured to perform gains on column pixel data (analog signal at this time) separated based on the analog driving signal, for example, perform different gains on column pixel data of different colors;

the data bit width of the column pixel data of each color component separated by the data separation module 130 may be 1/3 of the data bit width of the first video data before separation.

In another example, the first video data may also be a digital signal, in which case the data separation module may include a decoding unit and a second signal processing unit; the decoding unit is used for decoding the first video data and separating column pixel data (digital signals at the moment) of different color components; and a second signal processing unit for performing at least one signal process of waveform shaping, data grouping, parallel-to-serial conversion (i.e., parallel data conversion into serial data) on the column pixel data output from the decoding unit.

In one example, the decoding unit is specifically configured to: acquiring first video data through the signal interface 120; determining luminance values of light emitting devices of a plurality of color components for each pixel location in each first video data; for the light emitting device of a color component corresponding to each pixel position, determining a data parameter (such as at least one of duty cycle, current intensity, voltage intensity) of the light emitting device of the color according to the brightness value of the color component of each pixel position; column pixel data for a column pixel is generated based on data parameters of light emitting devices of the same color component of the column pixel.

In one example, the separated column pixel data may be gained by: the weighting weight of each color component is determined according to the sensitivity degree of human eyes to the colors of each channel, and then the column pixel data of each color component is gained according to the determined weighting weight, so that the compensation of the column pixel data of different color components is realized, and the image quality is improved. In one example, for the pixel data of R, G, B three color components, when compensating to rgb=2:1:4, the image quality can be better guaranteed, and the pixel data of other types of color components are the same.

In the above example, the quality of the transmitted signal can be maintained by waveform shaping, and attenuation during transmission is reduced so that the signal is correctly transmitted to the target node.

In the above example, the data grouping may be performed by: column pixel data of a bit width (e.g., any of 16 bits, 32 bits, 64 bits) is taken as a set.

In one example, the number of row drive circuits 140 is at least one; when the number of the row driving circuits 140 is one, the plurality of monochrome pixel arrays 110 are electrically connected to the row driving circuits 140, as shown in fig. 3; when the number of the row driving circuits 140 is two or more, each of the single color pixel arrays 110 is electrically connected to a corresponding one of the row driving circuits 140, as shown in fig. 5.

In a specific example, as shown in fig. 5, if the number of the monochrome pixel array 110 and the row driving circuit 140 is the same, the monochrome pixel array 110 and the row driving circuit 140 may be connected in one-to-one correspondence; if the number of the row driving circuits 140 is smaller than the number of the monochrome pixel arrays 110, a part of the monochrome pixel arrays 110 are connected to the same row driving circuit 140. The arrangement of more than two row driving circuits 140 can generate row driving signals to drive different monochrome pixel arrays 110, respectively, so that the driving capability of each row of pixel circuits can be increased.

In one example, the distribution of the pixel circuits in each monochrome pixel array 110 may be an array of 3 rows and 3 columns of pixel circuits as shown in fig. 6 or fig. 7, each pixel circuit is connected to a light emitting diode (as a light emitting device), and the negative electrode of the light emitting diode is electrically connected to a common electrode, which may be one common electrode as shown in fig. 6 or three common electrodes as shown in fig. 7. Fig. 6 and 7 show only the case of 3 rows and 3 columns as an example, and the actual monochrome pixel array 110 may include more pixel circuits, and correspondingly, may include more common electrodes.

Referring to an example shown in fig. 6 or fig. 7, the driving circuit of the silicon-based micro display provided in the embodiment of the application has the following working principle:

the signal interface 120 divides an input video signal into S monochrome pixel data (S is 3 in fig. 6 and 7), and is connected to S column driving circuits 150, respectively, each column driving circuit 150 includes a function of converting monochrome pixel data into a column driving signal, and the row driving circuit 140 is used for generating a row driving signal, and different monochrome display areas can share the row driving signal. The row drive signal is used to select a particular row, and when the row is open (active level), the pixel circuits of the row latch the data on the column drive signal into the circuit, and in one particular example, the data can be stored on a capacitor (which can be in the form of a single capacitor or multiple capacitors) in the pixel circuit or in a latch (which can be in the form of an SRAM structure) in the pixel circuit, and the signal output by the pixel circuit can drive the light emitting diode to emit light.

Referring to the example shown in fig. 6 or 7, for each pixel circuit in different monochrome pixel arrays 110, scanning may be performed according to the scanning timing shown in fig. 8, that is, the scanning timing of each monochrome pixel array 110 is the same, the high level corresponds to the light emitting time of the light emitting diode, and the low level corresponds to the blanking time of the light emitting diode; for each row of pixel circuits in the same monochrome pixel array 110, the scanning may be performed at a scanning timing as shown in fig. 9, that is, each row may be scanned at a different scanning timing, for example, a voltage or current duty cycle gray scale modulation manner may be used for the first row of pixel circuits, a voltage or current amplitude modulation manner may be used for the second row of pixel circuits, and a hybrid modulation (including both duty cycle gray scale modulation and amplitude modulation) manner may be used for the third and fourth rows.

Regarding the hybrid modulation scheme, in one example, if the RGB pixels are required to emit light of 256 levels in total, 32 different voltage values can be used in combination with 8 different duty cycles.

In an alternative embodiment, as shown in fig. 10, each column driving circuit 150 includes: a shift register, a sample hold circuit and a digital-to-analog conversion circuit.

The input end of the shift register is electrically connected with the signal interface 120, and the output end of the shift register is electrically connected with the first input end of the sample hold circuit; the shift register is used for generating a shift signal according to the time sequence control signal and outputting the shift signal.

The input end of the digital-to-analog conversion circuit is electrically connected with the output end of the data separation module 130, and the output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the sample hold circuit; the digital-to-analog conversion circuit is used for carrying out digital-to-analog conversion on the column pixel data and outputting the column pixel data.

The output end of the sample hold circuit is electrically connected with the data line of a corresponding monochromatic pixel array 110; the sampling hold circuit is used for sampling and holding the data output by the digital-to-analog conversion circuit when the shift signal output by the shift register is effective, and outputting column pixel data to the pixel circuits when the corresponding row of pixel circuits are opened.

In another alternative embodiment, as shown in FIG. 11, each column driver circuit 150 includes: the device comprises a shift register, a level conversion circuit, a sample hold circuit and a digital-to-analog conversion circuit.

The input end of the shift register is electrically connected with the signal interface 120, and the output end of the shift register is electrically connected with the output end of the level conversion circuit; the shift register is used for generating a shift signal according to the time sequence control signal and outputting the shift signal.

The output end of the level conversion circuit is electrically connected with the first input end of the sample hold circuit; the level conversion circuit is used for converting the shift signal output by the shift register into a level which can be received by the sample hold circuit and outputting the level.

The output end of the sample-hold circuit is electrically connected with the data line of a corresponding monochrome pixel array 110, and the sample-hold circuit is used for sampling and holding the column pixel data output by the digital-to-analog conversion circuit when the shift signal output by the level conversion circuit is valid, and outputting the column pixel data to the pixel circuit when the corresponding row of pixel circuits is opened.

The present embodiment adds a level shift circuit to the embodiment shown in fig. 10 to realize level shift, thereby satisfying the operation requirement of the sample-and-hold circuit.

In one example, as shown in fig. 10 and 11, when the signal interface 120 includes the timing signal interface 120 and the video signal interface 120, an input terminal of the shift register is electrically connected to the timing signal interface 120, and an input terminal of the data separation module 130 is electrically connected to the video signal interface 120.

In one example, in the embodiment shown in fig. 10 and 11, the shift signals output from the shift registers in each column driving circuit 150 correspond to the same pixel position;

the sample-and-hold circuits in the column driving circuits 150 sample and hold pixel data of the columns at the same pixel position at the same time.

In one example, the shift registers in each column driving circuit 150 shown in fig. 10 and 11 may operate simultaneously, and generate the same shift signal according to the timing control signal, that is, the shift signals output by each shift register are all at the same position, and each shift register may move from left to right or from right to left simultaneously, so that the sample and hold circuits in each column driving circuit 150 may also operate simultaneously.

In one example, the sample-and-hold circuit may include a plurality of sample-and-hold modules having the same number of columns as the monochrome pixel array 110, and the shift register in each column driver circuit 150 may only output one data valid signal at a time as a valid shift signal, which may enable one of the sample-and-hold modules to start operating, i.e., to sample and hold, the data output by the digital-to-analog conversion circuit.

In one example, the shift register may output shift signals in a serial shift order, so that each sample-and-hold module sequentially starts to operate, and pixel data of each pixel column in the corresponding monochrome pixel array 110 is sequentially sampled and held.

In one example, the sample-and-hold circuit may further include a column driver, where the sample-and-hold module may sample and hold the monochrome pixel data converted and output by the digital-to-analog conversion circuit, and when the row driving circuit 140 starts a certain pixel row of each monochrome pixel array 110, the column driver may output the corresponding monochrome pixel data to the pixel row; the column driver in each column driver circuit 150 can simultaneously output corresponding monochrome pixel data for the pixel row of the connected monochrome pixel array 110, thereby reducing chromatic dispersion formed by color combination of external optics; the pixel data sampled by the different sample and hold modules may be sequentially output by the column driver.

The embodiment of the application can repeatedly execute the scanning mode to realize progressive scanning and finish scanning of one frame of data, thereby keeping the scanning line frame and the frame frequency of each monochromatic display area the same.

In an alternative embodiment, as shown in fig. 12, each column driving circuit 150 includes: a shift register set, a comparator array, a digital switch array, a cycle counter and a digital-to-analog conversion circuit;

The input end of the shift register group is electrically connected with the data separation module 130, and the output end of the shift register group is electrically connected with the input end of the comparator array; the shift register set is configured to receive the column pixel data output by the data separation module 130, and sequentially output column pixel data corresponding to each column pixel repair to the comparator array based on the shift signal.

The input end of the circulation counter is electrically connected with the signal interface 120, and the output end of the circulation counter is electrically connected with the input end of the digital-to-analog conversion circuit and the input end of the comparator array respectively; the cycle counter is used for counting according to the time sequence control signal output by the signal interface 120 and outputting a count value.

The output end of the comparator array is electrically connected with the first input end of the digital switch array; the comparator array is used for receiving the column pixel data output by the shift register group, comparing the column pixel data with the count value output by the cycle counter, outputting a switch control signal according to the comparison result, and outputting the column pixel data; the switch control signal is used for controlling the on and off of the digital switch array.

The output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the digital switch array; the digital-to-analog conversion circuit is used for carrying out digital-to-analog conversion on the count value and outputting the converted analog voltage.

The output end of the digital switch array is electrically connected with the data line of a corresponding single-color pixel array 110; the digital switch array is used for outputting the analog voltage output by the digital-to-analog conversion circuit to the pixel circuits when the corresponding row of pixel circuits are turned on.

Referring to fig. 13, in the shift register group of the embodiment of the present application, the comparator array includes a plurality of comparators, the digital switch array includes a plurality of digital switches, the number of shift registers, comparators and digital switches is the same as the number of data lines output to the pixel circuit, the output ends of the shift registers in the shift register group are connected in one-to-one correspondence with the input ends of the comparators in the comparator array, the output ends of the comparators in the comparator array are connected in one-to-one correspondence with the first input ends of the digital switches in the digital switch array, and the output end of each digital switch is connected with one data line.

In one example, when the comparison result of the comparator is true (1), the comparator may output a switch control signal for controlling the digital switch to be turned on, so that one digital switch connected to the comparator is turned on; when the comparison result of the comparator is false (0), the comparator can output a switch control signal for controlling the digital switch to be turned off, so that one digital switch connected with the comparator is turned off.

In another alternative embodiment, as shown in fig. 14, each column driving circuit 150 further includes: shift register set, latch array, comparator array, level conversion circuit, digital switch array, cyclic counter and digital-to-analog conversion circuit.

The input end of the shift register group is electrically connected with the output end of the data separation module 130, and the output end of the shift register group is electrically connected with the input end of the latch array; the shift register group is configured to receive the column pixel data output from the data separation module 130, and sequentially output column pixel data corresponding to each column pixel to the latch array based on the shift signal.

The output end of the latch array is electrically connected with the input end of the comparator array; the latch array is used for receiving and storing data of the shift register set before shifting when the shift register set shifts.

The output end of the comparator array is electrically connected with the input end of the level conversion array; the comparator array is used for acquiring the column pixel data stored in the latch, comparing the column pixel data with the count value, outputting a switch control signal according to the comparison result, and outputting the column pixel data; the switch control signal is used for controlling the on and off of the digital switch array.

The output end of the level conversion array is electrically connected with the first input end of the digital switch array; the level conversion array is used for converting the switch control signals and the column pixel data output by the comparator array into the level which can be received by the digital switch array and outputting the level.

The output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the digital switch array, and the digital-to-analog conversion circuit is used for carrying out digital-to-analog conversion on the count value and outputting the converted analog voltage.

In this embodiment, compared with the embodiment shown in fig. 12, the latch array is added, so that the pixel data line of the M-th row can be saved when the shift register in the shift register group shifts the pixel data of the m+1th row, thereby realizing pipeline operation and improving performance.

In one example, as shown in fig. 12 and 13, when the signal interface 120 includes the timing signal interface 120 and the video signal interface 120, an input terminal of the shift register is electrically connected to the timing signal interface 120, and an input terminal of the data separation module 130 is electrically connected to the video signal interface 120.

In one example, the cycle counter in the embodiment of the present application may count from 0 to a maximum value and then count from the maximum value to 0, where the maximum value may be set according to actual requirements.

In one example, each cycle counter may store a count step of a corresponding monochrome pixel, and the step of each cycle counter may be adjusted according to actual requirements, where the adjustment manner may be any one of the following three manners:

in one mode, the adjustment is performed based on a memory in the cycle counter.

In the second mode, the counting step output by the timing controller is obtained, and the counting step output by the timing controller can be obtained through the timing signal interface 120. The time sequence controller comprises a gamma correction module, wherein the input of the gamma correction module is a linear array, and the output of the gamma correction module is the step length of gamma correction data, so that the time sequence controller can give out a counting step length when counting each time.

And in a third mode, a relation between the counting step length and the input is fitted in advance through a fitting algorithm, and then the counting step length is determined through a logic algorithm circuit according to the relation.

The specific structure and connection of the shift register set, the comparator array and the digital switch array can be referred to the previous description and the structure frame shown in fig. 13. The latch array in the embodiment of the application comprises a plurality of latches, the level conversion array comprises a plurality of level conversion circuits, the number of the latches is the same as that of the shift registers, the output ends of the shift registers in the shift register group are connected with the input ends of the latches in the latch array in a one-to-one correspondence manner, the output ends of the latches in the latch array are connected with the input ends of the comparators in the comparator array in a one-to-one correspondence manner, the output ends of the comparators in the comparator array are connected with the input ends of the level conversion circuits in the level conversion array in a one-to-one correspondence manner, and the output ends of the level conversion circuits in the level conversion array are connected with the first input ends of the digital switches in the digital switch array in a one-to-one correspondence manner.

In one example, as shown in fig. 12 and 14, the shift register groups in each column driving circuit 150 may output shift signals for the same pixel position at the same time, each cycle counter may count for the same pixel position at the same time, and then the comparator arrays in each column driving circuit 150 may compare for the same pixel position at the same time, and each digital-to-analog conversion circuit may perform digital-to-analog conversion for the same pixel position at the same time, and then each digital switch array may output monochrome pixel data for the same pixel position at the same time, so that the light emitting devices of different colors at the same pixel position are turned on at the same time, and thus the chromatic dispersion formed by the combination of external optical devices is reduced.

In the example of fig. 12 or 14, the digital-to-analog conversion circuit includes a digital-to-analog converter and a driver, an input of the digital-to-analog converter is electrically connected to an output of the cycle counter, an output of the digital-to-analog converter is electrically connected to an input of the driver, an output of the driver is electrically connected to each switch in the digital switch array, and the driver is operable to drive the switches in the digital switch array according to the output of the digital-to-analog converter.

In one example, since the light emitting characteristics of the light emitting devices of different colors are generally different, different (e.g., different bit widths or different counting rules) cycle counters and different (e.g., different bit widths) digital-to-analog converters may be employed for the different light emitting devices to implement gamma correction for the different color components, thereby improving color saturation and color rendering index, and the specific implementation of the gamma correction may be determined according to actual requirements.

In one example, the data separation module includes interpolation circuitry for interpolating the input video data to increase the number of bits of the video data, for example from 8 bits to 10-12 bits, which may be equal to the number of bits of the cycle counter and the number of bits of the input digital to analog converter, so that the gamma correction may be extended to 10-12 bits. When the step size of the cycle counter is 1, the interpolation circuit starts to operate, and the specific value to be inserted is determined according to the light emitting characteristics of the light emitting devices of different colors. Taking red, green and blue as examples, according to the corresponding relation of gamma curves of the red, green and blue light emitting devices, the input 8-bit value is converted into an output value of 10-12 bits, and the corresponding relation can be written into a memory in an interpolation circuit through a configuration interface before the display works, and the memory of the interpolation circuit can be any one of an SRAM, a register and a nonvolatile memory.

In one example, the timing control signal may include a row shutdown signal having a duty cycle of a preset duty cycle; the signal interface 120 is further configured to receive second video data, the second video data having a magnitude greater than the first video data.

The timing of the row off signal may refer to the timing diagram shown in fig. 15 or 16, the active level is the high level in fig. 15 or 16, and the inactive level is the low level in fig. 15 or 16. The time of the effective level corresponds to the on time of a certain row of pixels, namely, in the time range, the driving transistor of a certain row of pixel circuits is in a conducting state, the light emitting device is driven to emit light, and the corresponding light emitting device is also in a lighting state; the time of the invalid level corresponds to the turn-off time of a certain row of pixels, namely, in the time range, the driving transistor of a certain row of pixel circuits is in an off state, the light emitting device is not driven to emit light any more, and the corresponding light emitting device is also in an off state.

Referring to the example shown in fig. 15, control of the on-off state of the driving transistors of a certain row of pixel circuits can be achieved by shortening the time of the active level, for example, the 1-row on time in fig. 15, which can cause the corresponding driving transistors to be turned off in advance. Referring to the example shown in fig. 16, control of the on-off state of the driving transistors of a certain row of pixel circuits can be achieved by turning off a ratio of time for adjusting the active level to time for the inactive level, for example, by increasing the time for the inactive level within 1 row on time as shown in fig. 16, and by turning off a plurality of times within 1 row on time.

Referring to the example shown in fig. 15 or 16, the active levels of the row-off signals of two adjacent rows have time intervals to ensure that the on-off states of the driving transistors are controlled in row units, the off time of each row of driving transistors is inconsistent, and each row of driving transistors is not turned off at the same time, so that rolling turn-off is realized.

By increasing the amplitude of the video data on the basis of scrolling-off (e.g. by adding video data to the video dataThe pixel voltage is doubled) to effectively adjust the brightness of the low gray scale pixels. The voltage amplitude for the low gray scale pixel to light is very low, possibly reaching nA (nanoampere, 10) ^-9 And the brightness of the low-gray-scale pixels is inconsistent due to larger errors, the pixel lighting time can be shortened by rolling off and increasing the amplitude of the pixel voltage, the brightness of the low-gray-scale pixels can be controlled, the refreshing frequency is improved, and the flickering feeling of human eyes is reduced.

In yet another alternative embodiment, as shown in fig. 17, each column driving circuit 150 includes: clock tree, parallel shift register set, data latches and column driver.

The input end of the clock tree is electrically connected with the signal interface 120, the first output end of the clock tree is electrically connected with the parallel shift register group, and the second output end of the clock tree is electrically connected with the data latch respectively; the clock tree is used to output a first clock signal to the parallel shift register set and a second clock signal to the data latches according to the clock source of the signal interface 120.

The input end of the parallel shift register group is electrically connected with the data separation module 130, and the output end of the parallel shift register group is electrically connected with the input end of the data latch; the parallel shift register set is configured to receive the column pixel data output from the data separation module 130 and the first clock signal output from the clock tree, and shift the column pixel data according to the second clock signal.

The output end of the data latch is electrically connected with the input end of the column driver; the data latch is used for latching column pixel data and latching and outputting the result of the parallel shift register group when the second clock signal is valid.

The output of the column driver is electrically connected to a corresponding one of the monochrome pixel arrays 110; the column driver is used for outputting the data output by the data latch to the connected pixel circuit.

In one example, as shown in fig. 17, when the signal interface 120 includes the timing signal interface 120 and the video signal interface 120, an input terminal of the clock tree is electrically connected to the timing signal interface 120, and an input terminal of the data separation module 130 is electrically connected to the video signal interface 120.

Referring to the example of fig. 17, the pixel circuit in the embodiment of the present application employs a digital driving technology including a memory cell (e.g., an SRAM of a 1bit bistable structure) and a pixel driving circuit (e.g., a driving transistor), and the memory cell and the driving transistor in the pixel circuit are electrically connected.

In one example, the operation timing of the parallel shift register groups in each column driver circuit 150 is the same, and the operation timing of the data latches in each column driver circuit 150 is the same.

In one example, as shown in fig. 18, the clock trees in each column driving circuit 150 are homologous clock trees, the clock source may be a timing controller, the timings of the clock signals (first clock signal or second clock signal) generated by each clock tree are the same, the signal delays of the clock signals generated by each clock tree transmitted to all the target nodes are the same, for example, the signal delays of the first clock signal transmitted to each clock node in the connected parallel shift register group (hereinafter referred to as first delay) are the same, the signal delays of the second clock signal transmitted to each clock node in the connected data latches (second delay) are the same, and the first delay and the second delay may be the same or different. The clock trees 1 to 3 in fig. 17 represent clock trees in the column driving circuit 150 to which the red pixel array, the green pixel array, and the blue pixel array are connected, respectively, as shown in fig. 16.

In one example, each clock tree may have the same structure, for example, the same delay circuit is used and the interconnection lines are set to be equal in length, so that the signal delay of the first clock signal generated by each clock tree transmitted to each clock node in the connected parallel shift register group may be the same, so that the working time sequence of each parallel register group is the same, and the signal delay of the second clock signal generated by each clock tree transmitted to each clock node in the connected data latch may be the same, so that the working time sequence of each data latch is the same.

In one example, as shown in fig. 19, the parallel shift register group of the embodiment of the present application includes t parallel shift register rows, each including a plurality of parallel shift registers connected in series (each block in fig. 19 represents one parallel shift register). Each parallel shift register row may output shift data for one row, m columns (m being a positive integer, the same as the number of columns of monochrome pixel array 110).

In one example, the shift register at the same position in each parallel shift register row is taken as one parallel shift register unit, and the unit has t shift registers in total, that is, the output bit width of the unit is t (representing the transmission bit width of data and may be 8 bits or an integer multiple of 8 bits), if m parallel shift registers are included in the parallel shift register group, m/t parallel shift register units may be formed. The delay of the clock signal generated by the clock tree and transmitted to each parallel shift register is the same, for example, the delay is within 1ns (nanosecond), so that the data signal of each parallel shift register is ensured to be stable in a tiny time before and after the clock edge, and the requirements of the set-up time and the hold time are met.

In one example, each shift register in the parallel shift register unit may be a bidirectional parallel shift register, and after each shift of one row of parallel data is completed, each data latch may latch column pixel data in the connected bidirectional parallel shift register at the same time under the control of a clock signal output by a clock tree.

The following describes the operation principle of the parallel shift register group, the data latch and the column driver with reference to the timing diagram shown in fig. 20 and the driving circuit shown in fig. 17:

under the control of the time sequence control signals, the three clock trees respectively output three first clock signals with the same time sequence as shift enabling signals of the three parallel shift register groups, and the three clock trees also respectively output three second clock signals with the same time sequence as data latch signals; the row driving circuit 140 outputs a row driving signal.

Referring to fig. 20, when the shift enable signal is at a high level, the parallel shift register group performs shifting of the x-th row (x is a positive integer) data, when the shift enable signal transitions to a low level, the shifting of the x-th row data ends, at this time, the data latch signal transitions from a low level to a high level, the data latch latches the x-th row data in the parallel shift register group, the column driver signal updates to the x-th row data, and when the data latch signal is at a low level, the column driver signal remains stable, i.e., is stable when the x-th row data is valid, the row driver signal remains stable for a while when the column driver signal is stable, and the data of the column driver is written into one of the connected monochrome pixel arrays 110. In one example, the active time of the row drive signal hold may be such that three sets of column driver signals are written to three monochrome pixel arrays 110 simultaneously, e.g., 1-50ns.

In the example shown in fig. 17, the driving circuit of the silicon-based micro-display provided by the embodiment of the application may further include a zero clearing circuit (not shown in fig. 17), an input end of the zero clearing circuit is electrically connected to the timing control interface, a zero clearing signal transmitted by the timing control interface is received (may occur by the timing controller), an output end of the zero clearing circuit is electrically connected to the data latch, and data in the data latch may be quickly cleared according to the zero clearing signal, so as to blank each row.

In one example, the plurality of column driving circuits of the embodiment of the present application may include at least one circuit structure as shown in fig. 10 to 11, 12 to 14, and 17, so that any one of a digital driving manner, an analog driving manner, and a digital-analog hybrid driving manner may be implemented.

It should be noted that, in the embodiment of the present application, the case of three monochrome pixel arrays and three column driving circuits are mainly described as examples, but the present application is not limited thereto, and those skilled in the art can understand that the number of monochrome pixel arrays and column driving circuits in the embodiment of the present application may be set according to actual requirements.

The technical scheme provided by the embodiment of the application has at least the following beneficial effects:

1) The silicon-based micro-display and the driving circuit thereof provided by the embodiment of the application are provided with the data separation module, a plurality of corresponding column driving circuits and a plurality of monochromatic pixel arrays.

2) The signal interface, the row driving circuit, the column driving circuit and the monochromatic pixel array in the embodiment of the application are integrated on the same monocrystalline silicon substrate, and can be integrated on the same monocrystalline silicon substrate, so as to improve the integration level of the silicon-based micro-display.

3) The data separation module in the embodiment of the application outputs the same time sequence of the pixel data of a plurality of columns, and the same time sequence of the driving signals output by the pixel circuits at the same array position in each monochromatic pixel array, so that the light emitting devices with different colors at the same pixel position can be driven at the same time, and the light emitting devices with different colors at the same pixel position can emit light synchronously, thereby improving the display effect.

4) The column driving circuit in the embodiment of the application can be driven by multiple driving modes, such as a driving mode based on a sample-and-hold circuit shown in fig. 10 and 11, a driving mode based on a digital-to-analog conversion circuit and a comparator shown in fig. 12 and 13, and a driving mode based on digital scanning shown in fig. 16, the driving modes are flexible, and the corresponding driving modes can be selected according to actual requirements (such as requirements of resolution) so as to improve the driving capability of a specific scene; meanwhile, the application range of different driving modes is wider, and the driving method is applicable to driving of display areas with certain special forms, such as circular or elliptic display areas.

It should be understood that the application is not limited to the particular arrangements and instrumentality described above and shown in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after appreciating the spirit of the present application.

It should also be noted that the exemplary embodiments mentioned in this disclosure describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, or may be performed in a different order from the order in the embodiments, or several steps may be performed simultaneously.

In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the present application, and they should be included in the scope of the present application.

Claims

1. A drive circuit for a silicon-based microdisplay, comprising: the device comprises a signal interface, a data separation module, a row driving circuit, a plurality of column driving circuits and a plurality of monochromatic pixel arrays, wherein the number of the monochromatic pixel arrays is the same as that of the column driving circuits; each single-color pixel array comprises a plurality of pixel circuits which are used for driving single-color sub-pixels and are arranged in an array manner;

The input end of the data separation module and the input end of the row driving circuit are electrically connected with the signal interface, the output end of the data separation module is electrically connected with a plurality of column driving circuits respectively, the output end of the row driving circuit is electrically connected with scanning lines of a plurality of monochromatic pixel arrays respectively, and the output end of each column driving circuit is electrically connected with a corresponding data line of one monochromatic pixel array;

the data separation module is used for: extracting a plurality of color components in the first video data, generating column pixel data of each color component, and respectively transmitting a plurality of column pixel data to a plurality of column driving circuits;

the row driving circuit is configured to: generating a row driving signal according to the time sequence control signal, and transmitting the row driving signal to a plurality of the monochromatic pixel arrays through the scanning line;

the column driving circuit is configured to: and transmitting the column pixel data to a corresponding one of the single-color pixel arrays through the data line according to the time sequence control signal.

2. The drive circuit of a silicon-based microdisplay of claim 1, wherein the signal interface, the row drive circuit, the column drive circuit, and the array of monochrome pixels are integrated in the same single-crystal silicon substrate;

Each single-color pixel array is tiled on the monocrystalline silicon substrate, and a gap is reserved between every two adjacent single-color pixel arrays.

3. The driving circuit of a silicon-based micro-display according to claim 1, wherein timings of a plurality of the column pixel data are the same;

the timing of the driving signals output by the pixel circuits at the same array position in each single-color pixel array is the same.

4. A driving circuit of a silicon-based micro display as claimed in claim 3, wherein delay times of the plurality of column pixel data transmitted from the data separation module to the plurality of column driving circuits are equal, and an attenuation amplitude of a signal when each of the column pixel data is transmitted from the data separation module to a corresponding one of the column driving circuits is less than or equal to a preset attenuation amplitude threshold.

5. The driving circuit of a silicon-based micro display according to claim 1, wherein the data separation module comprises: a decoding unit and a signal processing unit;

the decoding unit is used for decoding the first video data and separating column pixel data of different color components;

when the first video data is a bit-plane signal, the signal processing unit is configured to perform at least one signal process of waveform shaping, data grouping, and parallel-to-serial conversion on the column pixel data separated based on the bit-plane signal;

When the first video data is an analog driving signal, the signal processing unit is configured to gain the column pixel data separated based on the analog driving signal.

6. The driving circuit of a silicon-based micro display according to claim 1, wherein the number of the row driving circuits is at least one;

when the number of the row driving circuits is one, a plurality of the single-color pixel arrays are electrically connected with the row driving circuits;

when the number of the row driving circuits is more than two, each of the single-color pixel arrays is electrically connected with a corresponding one of the row driving circuits.

7. The drive circuit of a silicon-based microdisplay of claim 1, wherein each of the column drive circuits comprises: a shift register, a sample hold circuit and a digital-to-analog conversion circuit;

the input end of the shift register is electrically connected with the signal interface, and the output end of the shift register is electrically connected with the first input end of the sample hold circuit; the shift register is used for generating a shift signal according to the time sequence control signal and outputting the shift signal;

the input end of the digital-to-analog conversion circuit is electrically connected with the output end of the data separation module, and the output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the sample hold circuit; the digital-to-analog conversion circuit is used for carrying out digital-to-analog conversion on the column pixel data and outputting the column pixel data;

The output end of the sampling hold circuit is electrically connected with the data line of a corresponding monochromatic pixel array; the sampling hold circuit is used for sampling and holding the data output by the digital-to-analog conversion circuit when the shift signal output by the shift register is valid, and outputting the column pixel data to the pixel circuit when the corresponding row of the pixel circuit is opened.

8. The drive circuit of a silicon-based microdisplay of claim 1, wherein each of the column drive circuits comprises: the device comprises a shift register, a level conversion circuit, a sample hold circuit and a digital-to-analog conversion circuit;

the input end of the shift register is electrically connected with the signal interface, and the output end of the shift register is electrically connected with the output end of the level conversion circuit; the shift register is used for generating a shift signal according to the time sequence control signal and outputting the shift signal;

the output end of the level conversion circuit is electrically connected with the first input end of the sample hold circuit; the level conversion circuit is used for converting the shift signal output by the shift register into a level receivable by the sample hold circuit and outputting the level;

the output end of the sampling hold circuit is electrically connected with the data line of a corresponding single-color pixel array, and the sampling hold circuit is used for sampling and holding the column pixel data output by the digital-to-analog conversion circuit when the shift signal output by the level conversion circuit is valid, and outputting the column pixel data to the pixel circuit when a corresponding row of the pixel circuits is opened.

9. The driving circuit of a silicon-based micro-display according to claim 7 or 8, wherein the shift signals output from the shift registers in each of the column driving circuits correspond to the same pixel position;

the sample-and-hold circuit in each of the column driving circuits simultaneously samples and holds each of the column pixel data at the same pixel position.

10. The drive circuit of a silicon-based microdisplay of claim 1, wherein each of the column drive circuits comprises: a shift register set, a comparator array, a digital switch array, a cycle counter and a digital-to-analog conversion circuit;

The input end of the shift register set is electrically connected with the data separation module, and the output end of the shift register set is electrically connected with the input end of the comparator array; the shift register group is used for receiving the column pixel data output by the data separation module and sequentially outputting column pixel data corresponding to each column of pixels to the comparator array based on a shift signal;

the input end of the cycle counter is electrically connected with the signal interface, and the output end of the cycle counter is electrically connected with the input end of the digital-to-analog conversion circuit and the input end of the comparator array respectively; the cycle counter is used for counting according to the time sequence control signal output by the signal interface and outputting a count value;

the output end of the comparator array is electrically connected with the first input end of the digital switch array; the comparator array is used for receiving the column pixel data output by the shift register set, comparing the column pixel data with the count value, outputting a switch control signal according to a comparison result, and outputting the column pixel data; the switch control signal is used for controlling the on and off of the digital switch array;

The output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the digital switch array; the digital-to-analog conversion circuit is used for carrying out digital-to-analog conversion on the count value and outputting converted analog voltage;

the output end of the digital switch array is electrically connected with the data line of a corresponding single-color pixel array; the digital switch array is used for outputting the analog voltage to the pixel circuits when the pixel circuits of the corresponding row are turned on.

11. The drive circuit of a silicon-based microdisplay of claim 1, wherein each of the column drive circuits further comprises: a shift register set, a latch array, a comparator array, a level conversion circuit, a digital switch array, a cycle counter and a digital-to-analog conversion circuit;

the input end of the shift register group is electrically connected with the output end of the data separation module, and the output end of the shift register group is electrically connected with the input end of the latch array; the shift register group is used for receiving the column pixel data output by the data separation module and sequentially outputting column pixel data corresponding to each column of pixels to the latch array based on a shift signal;

The output end of the latch array is electrically connected with the input end of the comparator array; the latch array is used for receiving and storing data of the shift register set before shifting when the shift register set shifts;

the output end of the comparator array is electrically connected with the input end of the level conversion array; the comparator array is used for acquiring the column pixel data stored by the latch, comparing the column pixel data with the count value, outputting a switch control signal according to a comparison result, and outputting the column pixel data; the switch control signal is used for controlling the on and off of the digital switch array;

the output end of the level conversion array is electrically connected with the first input end of the digital switch array; the level conversion array is used for converting the switch control signals and the column pixel data output by the comparator array into the level receivable by the digital switch array and outputting the level;

The output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the digital switch array, and the digital-to-analog conversion circuit is used for carrying out digital-to-analog conversion on the count value and outputting converted analog voltage;

12. The driving circuit of a silicon-based micro-display according to any one of claims 7, 8, 10, 11, wherein the timing control signal comprises a row-off signal, the duty cycle of the row-off signal being a preset duty cycle;

the signal interface is also configured to receive second video data, the second video data having a magnitude greater than the first video data.

13. The drive circuit of a silicon-based microdisplay of claim 1, wherein each of the column drive circuits comprises: a clock tree, a parallel shift register set, a data latch, and a column driver;

the input end of the clock tree is electrically connected with the signal interface, the first output end of the clock tree is electrically connected with the parallel shift register group, and the second output end of the clock tree is electrically connected with the data latch respectively; the clock tree is used for outputting a first clock signal to the parallel shift register set and outputting a second clock signal to the data latch according to a clock source of the signal interface;

The input end of the parallel shift register group is electrically connected with the data separation module, and the output end of the parallel shift register group is electrically connected with the input end of the data latch; the parallel shift register group is used for receiving the column pixel data output by the data separation module and a first clock signal output by the clock tree, and shifting according to the second clock signal;

the output end of the data latch is electrically connected with the input end of the column driver; the data latch is used for latching the column pixel data and latching and outputting the result of the parallel shift register group when the second clock signal is valid;

the output end of the column driver is electrically connected with a corresponding single-color pixel array; the column driver is configured to output data output from the data latch to the connected pixel circuit.

14. The driving circuit of a silicon-based microdisplay of claim 13, wherein the parallel shift register sets in each of the column driving circuits have the same operation timing and the data latches in each of the column driving circuits have the same operation timing.

15. A silicon-based microdisplay comprising: a light emitting device and a driving circuit of a silicon-based micro display as claimed in any one of claims 1 to 14;

the driving circuit comprises a driving circuit, a plurality of monochromatic pixel arrays and a display unit, wherein the monochromatic pixel arrays in the driving circuit are distributed in a plurality of monochromatic display areas, and each monochromatic pixel array is electrically connected with the light emitting device of one color and is used for driving the light emitting device of the color to emit light.

16. The silicon-based microdisplay of claim 15, further comprising: at least one common electrode;

when the silicon-based micro-display comprises a common electrode, a plurality of the single-color pixel arrays are electrically connected with the common electrode;

when the silicon-based micro-display includes more than two common electrodes, each of the single-color pixel arrays is electrically connected to a corresponding one of the common electrodes.

17. The silicon-based microdisplay of claim 15 or 16, further comprising: a timing controller;

the input end of the time schedule controller is connected with first video data of a target video, and the output end of the time schedule controller is electrically connected with a signal interface in the driving circuit;

the timing controller is configured to generate a timing control signal for the video data from the first video data, and output the first video data and the timing control signal.

18. The silicon-based microdisplay of claim 17, wherein the timing controller is further configured to increase the amplitude of the first video data to obtain and output the second video data when the timing control signal includes a row-off signal and the time of the active level of the row-off signal is less than a preset value.