CN113205760A

CN113205760A - Silicon-based micro-display and driving circuit thereof

Info

Publication number: CN113205760A
Application number: CN202110475250.0A
Authority: CN
Inventors: 冉峰
Original assignee: Suzhou Tanggu Photoelectric Technology Co Ltd
Current assignee: Wuxi Tanggu Semiconductor Co ltd
Priority date: 2021-04-29
Filing date: 2021-04-29
Publication date: 2021-08-03
Anticipated expiration: 2041-04-29
Also published as: CN113205760B

Abstract

The application discloses a silicon-based micro-display and a driving circuit thereof. The drive circuit of a silicon-based microdisplay comprises: the device comprises a signal interface, a data separation module, a row driving circuit, a plurality of column driving circuits and a plurality of monochrome pixel arrays, wherein the number of the monochrome pixel arrays is the same as that of the column driving circuits; each monochromatic pixel array comprises a plurality of pixel circuits which are used for driving a monochromatic sub-pixel and are arranged in an array; the input end of the data separation module and the input end of the row driving circuit are electrically connected with the signal interface, the output end of the data separation module is electrically connected with the plurality of column driving circuits respectively, the output end of the row driving circuit is electrically connected with the scanning lines of the plurality of monochrome pixel arrays respectively, and the output end of each column driving circuit is electrically connected with the data line of the corresponding monochrome pixel array. The embodiment of the application can drive different monochrome pixel arrays through different row driving circuits, can effectively improve the driving capability of the pixel arrays, and reduces the difficulty of circuit design and the cost.

Description

Silicon-based micro-display and driving circuit thereof

Technical Field

The application relates to the technical field of display, in particular to a silicon-based micro-display and a driving circuit thereof.

Background

The silicon-based micro-display is a special display based on silicon semiconductor technology, has small physical size and forms a large field of view through optical amplification. The existing silicon-based micro display usually comprises a driving circuit and a light emitting device, wherein the driving circuit usually comprises a pixel array consisting of pixels with various colors, and a row driving circuit and a column driving circuit which are used for driving the pixel array, the pixel array is driven by adopting the uniform row driving circuit and the uniform column driving circuit, the driving capability is poor, the circuit design is complex, and the cost is high.

Disclosure of Invention

The embodiment of the application provides a silicon-based micro-display and a driving circuit thereof, which can solve the technical problem of complex circuit design in the prior art.

In a first aspect, an embodiment of the present application provides a driving circuit for a silicon-based microdisplay, including:

the device comprises a signal interface, a data separation module, a row driving circuit, a plurality of column driving circuits and a plurality of monochrome pixel arrays, wherein the number of the monochrome pixel arrays is the same as that of the column driving circuits; each monochromatic pixel array comprises a plurality of pixel circuits which are used for driving a monochromatic sub-pixel and are arranged in an array;

the input end of the data separation module and the input end of the row driving circuit are electrically connected with the signal interface, the output end of the data separation module is electrically connected with the plurality of column driving circuits respectively, the output end of the row driving circuit is electrically connected with the scanning lines of the plurality of monochrome pixel arrays respectively, and the output end of each column driving circuit is electrically connected with the data line of the corresponding monochrome pixel array;

the signal interface is used for: receiving a timing control signal and first video data of a target video;

the data separation module is used for: extracting a plurality of color components in the first video data, generating column pixel data of each color component, and transmitting the plurality of column pixel data to a plurality of column driving circuits, respectively;

the row drive circuit is used for: generating a row driving signal according to the timing control signal and transmitting the row driving signal to the plurality of monochrome pixel arrays through the scan line;

the column driver circuit is configured to: and transmitting column pixel data to a corresponding one of the monochrome pixel arrays through the data line according to the timing control signal.

In a second aspect, an embodiment of the present application provides a silicon-based microdisplay, including: the drive circuit of the light emitting device and the silicon-based micro-display provided by the first aspect of the embodiment of the application;

the driving circuit has multiple monochrome pixel arrays distributed in multiple monochrome display regions, each monochrome pixel array electrically connected with one color light emitting device for driving the color light emitting device to emit light

The power module and the mainboard that this application embodiment provided can realize following beneficial effect at least:

the embodiment of the application provides a silicon-based micro-display and a driving circuit thereof, which are provided with a data separation module, a plurality of corresponding column driving circuits and a plurality of monochrome pixel arrays.

Drawings

Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

Fig. 1 is a schematic structural framework diagram of a silicon-based microdisplay according to an embodiment of the present disclosure;

fig. 2 is a schematic structural framework diagram of another silicon-based microdisplay according to an embodiment of the present disclosure;

fig. 3 is a schematic structural framework diagram of a first driving circuit of a silicon-based microdisplay according to an embodiment of the present invention;

FIG. 4 is a timing diagram of driving signals for different monochrome pixel arrays according to an embodiment of the present disclosure;

fig. 5 is a schematic structural framework diagram of a second driving circuit of a silicon-based microdisplay according to an embodiment of the present invention;

FIG. 6 is a block diagram of a third driving circuit of a silicon-based microdisplay according to an embodiment of the present invention;

FIG. 7 is a block diagram of a fourth driving circuit of a silicon-based microdisplay according to an embodiment of the present invention;

FIG. 8 is a timing diagram illustrating scanning of pixel circuits in different monochrome pixel arrays according to an embodiment of the present disclosure;

FIG. 9 is a timing diagram illustrating scanning for different rows of pixel circuits in the same monochrome pixel array according to an embodiment of the present disclosure;

fig. 10 is a schematic structural framework diagram of a fifth driving circuit of a silicon-based microdisplay according to an embodiment of the present application;

fig. 11 is a schematic structural framework diagram of a sixth driving circuit of a silicon-based microdisplay according to an embodiment of the present invention;

fig. 12 is a schematic structural framework diagram of a seventh driving circuit of a silicon-based microdisplay according to an embodiment of the present application;

FIG. 13 is a schematic diagram of the structural frameworks and connections of the shift register set, the comparator array and the digital switch array in the embodiment of the present application;

FIG. 14 is a block diagram of an eighth driving circuit of a silicon-based microdisplay according to an embodiment of the present invention;

FIG. 15 is a timing diagram of a row shutdown signal in an embodiment of the present application;

FIG. 16 is a timing diagram of another row shutdown signal in the embodiment of the present application;

fig. 17 is a schematic structural framework diagram of a ninth driving circuit of a silicon-based microdisplay according to an embodiment of the present application;

FIG. 18 is a block diagram of a clock tree according to an embodiment of the present application;

FIG. 19 is a block diagram of a parallel shift register set according to an embodiment of the present invention;

FIG. 20 is a timing diagram of a shift enable signal, a data latch signal, a column driver signal, and a row driver signal according to an embodiment of the present invention.

Detailed Description

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. In the description of the present application, "a plurality" means two or more unless otherwise specified.

The terms referred to in this application will first be introduced and explained:

ping-pong operation is a data buffering optimization design technique in FPGA development, and can be regarded as another form of pipeline technique, when an Input data stream passes through an "Input data stream selection unit", the data stream is distributed into two data buffering modules at equal time intervals, and a data buffering module can be any storage module in an FPGA (Field-Programmable Gate Array), such as a dual-port RAM (Random Access Memory), a single-port RAM, and a FIFO (First Input First Output, First in First out).

Set up time (Tsu: set up time): it is the time before the rising edge of the clock signal of the flip-flop, the data is stable and unchanged, if the setup time is not enough, the data cannot be stably driven into the flip-flop at the rising edge of the clock, Tsu is the minimum stable time.

Hold time (Th): the data is stable and unchangeable time after the rising edge of the clock signal of the trigger arrives, if the holding time is not enough, the data can not be stably driven into the trigger, and Th is the minimum holding time.

In order to solve the problem of the prior art, the embodiment of the application provides a power module and a main board. The following describes the technical solutions of the present application and how to solve the above technical problems in detail with specific embodiments.

An embodiment of the present application provides a silicon-based microdisplay, as shown in fig. 1, including: a light emitting device (not shown in fig. 1) and a driver circuit for a silicon-based microdisplay. A plurality of monochrome pixel arrays 110 in the driving circuit of the silicon-based microdisplay are distributed in a plurality of monochrome display regions (such as a red display region, a green display region and a blue display region shown in fig. 1), and each monochrome pixel array 110 is electrically connected to a light emitting device of one color for driving the light emitting device of the color to emit light.

In an example, a silicon-based microdisplay provided by an embodiment of the present application may further include: at least one common electrode; when the silicon-based microdisplay includes a common electrode, the monochrome pixel arrays 110 are all electrically connected to the common electrode; when the silicon-based microdisplay includes more than two common electrodes, each monochrome pixel array 110 is electrically connected to a corresponding one of the common electrodes.

In a specific example, if the number of the monochrome pixel array 110 and the common electrode is the same, the monochrome pixel array 110 and the common electrode may be connected in a one-to-one correspondence; if the number of the common electrodes is smaller than that of the monochrome pixel arrays 110, some of the monochrome pixel arrays 110 are connected to the same common electrode. The arrangement of more than two common electrodes is beneficial to respectively adjusting the voltage or the current of each pixel array.

In one example, the voltage or current of the pixel array can be adjusted by: the grid voltage of the driving transistor of each pixel circuit in the pixel array is adjusted, so that the output current of the driving transistor can be adjusted, the output current drives the light-emitting device to emit light, and the purpose of adjusting the light-emitting brightness of the light-emitting device is achieved.

The light emitting device of the embodiment of the present application may be an organic electroluminescent device, a semiconductor light emitting device, or a liquid crystal display device.

In an example, as shown in fig. 2, a silicon-based microdisplay provided in an embodiment of the present application may further include: a time schedule controller.

The input end of the time schedule controller is connected with the first video data of the target video, and the output end of the time schedule controller is electrically connected with the signal interface 120 in the driving circuit; the timing controller is used for generating a timing control signal aiming at the video data according to the first video data and outputting the first video data and the timing control signal. The first video data is the video data which is input into the time sequence controller according to the pixel points of each frame of image of the target video, and the video data comprises the image data of each frame of image of the target video.

In one example, the timing controller is further configured to increase an amplitude of the first video data to obtain and output the second video data when the timing control signal includes the row shutdown signal and a time of an active level of the row shutdown signal is less than a preset value.

In one example, as shown in fig. 2, the timing controller may include: an image processing module 210, a frame buffer controller 220 and a scanning circuit 230 electrically connected in sequence. The image processing module 210, the frame buffer controller 220 and the scan Circuit 230 may be Integrated into an ASIC (Application Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array).

The input terminal of the image processing module 210 is used as the input terminal of the timing controller, and is connected to the first video data of the target video, and the input terminal of the image processing module 210 may include any one of the following interfaces: RGB (red, green, blue), MIPI (Mobile Industry Processor Interface), VGA (Video Graphics Array, a D-type Interface), AV (composite Video Interface), DVI (Digital Visual Interface), LVDS (Low Voltage Differential Signaling), mini-LVDS (micro Low Voltage Differential Signaling), DP (display Interface)/eDP (Embedded display Interface), wherein the output end of the image processing is electrically connected with the input end of the frame buffer controller 220, the first output end of the frame buffer controller 220 is electrically connected with the input end of the scanning circuit 230, the second output end is electrically connected with the frame, and the output end of the scanning circuit 230 is electrically connected with the drive circuit of the silicon-based buffer.

The image processing module 210 may perform at least one of the following image preprocessing on each image data in the first video data: the image size adjustment, brightness adjustment, contrast adjustment, gamma correction, etc. make the first video data meet specific requirements.

The frame buffer controller 220 may output the image data after the image preprocessing to the frame buffer via a first output terminal in a bit plane manner, and may also read the image data in the frame buffer in a bit plane manner and output the read image data to the scanning circuit 230 via a second output terminal; the frame buffer may store the received image data in bitplanes.

The scan circuit 230 may receive image data output by the frame buffer controller 220, and the output of the frame buffer control and the reception by the bit plane scan circuit 230 may be ping-pong operations.

In one example, when there are multiple frame buffers and the frame buffer controller 220 is storing image data in one of the frame buffers, the scan circuit 230 may read another frame buffer by the frame buffer controller 220, thereby increasing the bandwidth speed.

In one example, the scan circuitry 230 may include bit plane scan circuitry, such as in a digital drive mode.

After acquiring the image data, the bit plane scanning circuit may transmit three bit plane signals, which divide the image data into different color components, to a driving circuit of the silicon-based microdisplay, each pixel data in the image data may be decomposed into three data with different color components, each data may be sequentially transmitted in a bit plane manner, and the transmission manner may be a TTL (Transistor-Transistor Logic) level manner or a low voltage differential pair manner. The three bit plane signals output by the bit plane scanning circuit can be transmitted to the driving circuit of the silicon-based microdisplay through three transmission lines respectively, or can be transmitted to the driving circuit of the silicon-based microdisplay through one transmission line as shown in fig. 2 in the form of a mixed bit plane signal, so as to improve the transmission efficiency.

The different color components in the embodiments of the present application may be determined according to at least one of the following color modes: RGB (red green blue, respectively), CMYK (cyan magenta yellow black, respectively), YUV (Y brightness, UV chromaticity). Hereinafter, mainly RGB will be described as an example.

In one example, the bit plane scanning circuit may further generate a timing control signal according to the acquired image data and transmit the timing control signal to a driving circuit of the silicon-based microdisplay, and the timing control signal may be transmitted in a bit plane manner, which may be a TTL level manner or a low voltage differential pair manner.

In another example, the scan circuit 230 may include a digital-to-analog scan controller, such as in an analog driving mode or a digital-to-analog hybrid driving mode.

The image data output by the frame buffer controller 220 is processed by the digital-analog scan controller, and then the high-frequency analog driving signal is output to the driving circuit of the silicon-based microdisplay, so as to increase the scanning rate of the pixels.

In one example, the timing controller may not include the image processing module 210, i.e., without image pre-processing.

In one example, scan circuitry 230 may include a state machine that may employ the same timing operations for R, B, G data in the bit plane to synchronize the timing of the data. The timing operation includes reading out data from the frame buffer one by the frame buffer controller 220, and the reading out sequence may be row by row and column by column or may be random reading out. In another example, the state machine when reading R, G, B the data row-by-row, column-by-column, or random readout, R, G, B data for the same pixel is configured to be read out at the same time.

The frame buffer in the embodiment of the present application may be any one of an SRAM (Static Random-Access Memory), an SDRAM (Synchronous Dynamic Random-Access Memory), and a DDR SDRAM (Double Data Rate SDRAM). In one example, if the frame buffer is SRAM, the SRAM may be integrated within the FPGA or ASIC, and if the frame buffer is SDRAM or DDR, the SDRAM or DDR may be provided in a separate chip.

An embodiment of the present application provides a driving circuit of a silicon-based microdisplay, as shown in fig. 3, the driving circuit includes: a signal interface 120, a data separation module 130, a row driving circuit 140, a plurality of column driving circuits 150, and a plurality of monochrome pixel arrays 110 having the same number as the plurality of column driving circuits 150; each monochrome pixel array 110 includes a plurality of pixel circuits arranged in an array for driving a monochrome sub-pixel.

The input end of the data separation module 130 and the input end of the row driving circuit 140 are electrically connected to the signal interface 120, the output end of the data separation module 130 is electrically connected to the plurality of column driving circuits 150, the output end of the row driving circuit 140 is electrically connected to the scan lines of the plurality of monochrome pixel arrays 110, and the output end of each column driving circuit 150 is electrically connected to the data line of a corresponding monochrome pixel array 110.

The signal interface 120 is used for: receiving a timing control signal and first video data of a target video; the data separation module 130 is configured to: extracting a plurality of color components in the first video data, generating column pixel data of each color component, and transmitting the plurality of column pixel data to the plurality of column driving circuits 150, respectively; the row driver circuit 140 is configured to: generating row driving signals according to the timing control signals and transmitting the row driving signals to the plurality of monochrome pixel arrays 110 through the scan lines; the column driver circuit 150 is configured to: the column pixel data is transmitted to a corresponding one of the monochrome pixel arrays 110 through the data line according to the timing control signal.

In one example, the first video data received by the data separation module 130 may be a bit plane signal output by a bit plane scanning circuit or an analog driving signal output by a digital-to-analog scanning controller.

In one example, signal interface 120, row driver circuit 140, column driver circuit 150, and monochrome pixel array 110 are integrated on the same single-crystal silicon substrate; each monochrome pixel array 110 is tiled on a single crystal silicon substrate with a gap between two adjacent monochrome pixel arrays 110. The monocrystalline silicon substrate can enable the integration level of a driving circuit of the silicon-based micro-display to be higher, and a gap is reserved between every two adjacent monochromatic pixel arrays 110, so that a light-emitting device can be manufactured conveniently.

In one example, the top electrode, the metal layers, the semiconductor device layer, and the like of each monochrome pixel array 110 can be fabricated on the single crystal silicon substrate at one time by using the same semiconductor process.

In one example, a gap of not less than 1 pixel is left between two adjacent monochrome pixel arrays 110 to leave enough space for fabricating a light emitting device, for example, in the case where the light emitting device is an LED. In another example, a gap of not less than 10 pixels is left between two adjacent monochrome pixel arrays 110 to leave enough space for fabricating a light emitting device, for example, in the case where the light emitting device is an OLED.

In one example, the signal interface 120 in the embodiment of the present application may include a video signal interface 120 and a timing signal interface 120, the video signal interface 120 may be configured to receive first video data of a target video, and the timing interface may be configured to receive a timing control signal. The first video data received by the video signal interface 120 may be original video data of the target video, or may be video data that is image-preprocessed by the timing controller and transmitted in a bit plane.

In one example, the video signal interface 120 in the embodiment of the present application may be an analog circuit compatible with a video signal, such as any one of the following: RGB, MIPI, HDMI, VGA, AV, DVI, LVDS, mini-LVDS, DP/eDP.

In one example, the timings of the plurality of rows of pixel data output by the data separation module 130 are the same, and the timings of the driving signals output by the pixel circuits at the same array position in each monochrome pixel array 110 are the same, so that the driving of the light emitting devices of different colors of the same pixel point at the same time can be realized, and the light emitting devices of different colors of the same pixel point can emit light synchronously.

Taking the driving circuit shown in fig. 3 as an example, if each sub-pixel in the red pixel array, the green pixel array, and the blue pixel array is a sub-pixel of pixels P0 to Pn, and L0 to Lm, and the positions of the red sub-pixel, the green sub-pixel, and the blue sub-pixel included in the same pixel in the respective pixel arrays are the same (for example, they are all in the ith row and jth column), the time sequences of the driving signals for the red pixel array, the green pixel array, and the blue pixel array are the same, and are all from P0 to Pn, and from L0 to Lm, and the sub-pixels at the corresponding positions in the three pixel arrays are simultaneously turned on or off, as shown in fig. 4.

In one example, the delay time of the plurality of column pixel data transmitted to the plurality of column driving circuits 150 by the data separation module 130 is equal, and the attenuation amplitude of the signal when each column pixel data is transmitted to the corresponding one of the column driving circuits 150 by the data separation module 130 is less than or equal to the preset attenuation amplitude threshold.

In one example, the attenuation threshold may be preset according to actual requirements or empirical values, for example, a value that does not affect the normal function of the circuit is set as the attenuation threshold, and in a specific example, the attenuation threshold may be set to 30% so that the amplitude of the attenuated signal (the highest voltage of the signal) is not lower than 70% of the amplitude of the attenuated signal.

In one example, at least one of the following effects between the data separation module 130 and the column driving circuits 150 may be achieved by adjusting at least one of a routing manner, a device type, and a circuit parasitic parameter between the data separation module 130 and the column driving circuits 150: the same routing length, the same device type, and the same circuit parasitic parameters are used to achieve the same delay time for transmitting the pixel data of a plurality of columns from the data separation module 130 to the plurality of column driving circuits 150; the signal attenuation between each column pixel data from the data separation module 130 to a corresponding one of the column driving circuits 150 can be reduced by reducing the interference between the data separation module 130 and each column driving circuit 150, so as to achieve the purpose of no signal attenuation.

In one example, the data separation module 130 includes: a decoding unit and a signal processing unit.

The decoding unit is configured to decode the first video DATA and separate column pixel DATA of different color components (e.g., RED column pixel DATA RED _ DATA, GREEN column pixel DATA GREEN _ DATA, and BLUE column pixel DATA BLUE _ DATA shown in fig. 3).

When the first video data is a bit-plane signal (digital signal) output from the bit-plane scanning circuit, the second signal processing unit is configured to perform at least one of waveform shaping, data grouping, and parallel-to-serial conversion (i.e., parallel-to-serial conversion of data into serial data) on column pixel data (in this case, a digital signal) separated based on the bit-plane signal.

When the first video data is an analog driving signal output by the digital-analog scanning controller, the signal processing unit is configured to perform a gain on column pixel data (in this case, an analog signal) separated based on the analog driving signal, for example, perform different gains on column pixel data of different colors;

the data bit width of the column pixel data of each color component separated by the data separation module 130 may be 1/3 of the data bit width of the first video data before separation.

In another example, the first video data may also be a digital signal, and in this case, the data separation module may include a decoding unit and a second signal processing unit; the decoding unit is used for decoding the first video data and separating out column pixel data (digital signals at this time) of different color components; and the second signal processing unit is used for performing at least one of waveform shaping, data grouping and parallel-serial conversion (namely parallel data is converted into serial data) on the column pixel data output by the decoding unit.

In one example, the decoding unit is specifically configured to: acquiring the first video data through the signal interface 120; determining luminance values of light emitting devices of a plurality of color components for each pixel position in each first video data; for the light-emitting device of one color component corresponding to each pixel position, determining the data parameter (such as at least one of duty ratio, current intensity and voltage intensity) of the light-emitting device of the color corresponding to each pixel position according to the brightness value of the color component of each pixel position; column pixel data for the column of pixels is generated based on data parameters for light emitting devices of the same color component for the same column of pixels.

In one example, the separated column pixel data may be gained by: and determining the weighting weight of each color component according to the sensitivity of human eyes to the color of each channel, and further performing gain on the column pixel data of each color component according to the determined weighting weight so as to realize compensation on the column pixel data of different color components and improve the image quality. In one example, for R, G, B pixel data of three color components, when compensating to R: G: B ═ 2:1:4, image quality can be better guaranteed, and the same applies for pixel data of other types of color components.

In the above example, the quality of the transmitted signal may be maintained by waveform shaping, reducing attenuation during transmission, so that the signal is correctly transmitted to the target node.

In the above example, the data grouping may be performed by: column pixel data of a certain bit width (e.g., any one of 16 bits, 32 bits, and 64 bits) is set as a group.

In one example, the number of row driving circuits 140 is at least one; when the number of the row driving circuits 140 is one, the plurality of monochrome pixel arrays 110 are all electrically connected to the row driving circuits 140, as shown in fig. 3; when the number of the row driving circuits 140 is two or more, each monochrome pixel array 110 is electrically connected to a corresponding one of the row driving circuits 140, as shown in fig. 5.

In a specific example, as shown in fig. 5, if the number of the monochrome pixel arrays 110 and the row driving circuits 140 is the same, the monochrome pixel arrays 110 and the row driving circuits 140 may be connected in a one-to-one correspondence; if the number of the row driving circuits 140 is less than the number of the monochrome pixel arrays 110, some of the monochrome pixel arrays 110 are connected to the same row driving circuit 140. The arrangement of more than two row driving circuits 140 can generate row driving signals to drive different monochrome pixel arrays 110, respectively, thereby increasing the driving capability for each row of pixel circuits.

In one example, the distribution of the pixel circuits in each monochrome pixel array 110 may be an array of 3 rows and 3 columns of pixel circuits as shown in fig. 6 or fig. 7, each pixel circuit is connected with a light emitting diode (as a light emitting device), the cathode of the light emitting diode is electrically connected with a common electrode, and the common electrode may be a common electrode as shown in fig. 6 or three common electrodes as shown in fig. 7. Fig. 6 and 7 only show 3 rows and 3 columns as an example, and an actual monochrome pixel array 110 may include more pixel circuits and correspondingly, may include more common electrodes.

Referring to the example shown in fig. 6 or fig. 7, the operation principle of the driving circuit of the silicon-based microdisplay provided by the embodiment of the present application is as follows:

the signal interface 120 divides the input video signal into S monochrome pixel data (S is 3 in fig. 6 and 7), and is respectively connected to S column driving circuits 150, each column driving circuit 150 includes a function of converting monochrome pixel data into column driving signals, the row driving circuit 140 is used for generating row driving signals, and different monochrome display regions can share the row driving signals. The row drive signal is used to select a particular row, and when the row is open (level active), the pixel circuits of that row latch the data on the column drive signal into the circuit, which in one particular example may be stored on a capacitor (which may be in the form of a single capacitor or multiple capacitors) in the pixel circuit or in a latch (which may be a latch of SRAM configuration) in the pixel circuit, and the signal output by the pixel circuit may drive the light emitting diode to emit light.

Referring to the example shown in fig. 6 or fig. 7, for each pixel circuit in different monochrome pixel arrays 110, scanning may be performed according to the scanning timing shown in fig. 8, that is, the scanning timing of each monochrome pixel array 110 is the same, and a high level corresponds to the light emitting time of the light emitting diode, and a low level corresponds to the blanking time of the light emitting diode; for each row of pixel circuits in the same monochrome pixel array 110, scanning may be performed according to the scanning timing shown in fig. 9, that is, each row may be scanned with different scanning timing, for example, a first row of pixel circuits may be scanned by duty ratio gray-scale modulation of voltage or current, a second row of pixel circuits may be scanned by amplitude modulation of voltage or current, and a third row and a fourth row may be scanned by hybrid modulation (including both duty ratio gray-scale modulation and amplitude modulation).

Regarding the hybrid modulation scheme, in one example, if the RGB pixels are required to emit 256 levels of light from 0-255, 32 different voltage values in combination with 8 different duty cycles may be used.

In an alternative embodiment, as shown in fig. 10, each column driving circuit 150 includes: the circuit comprises a shift register, a sampling hold circuit and a digital-to-analog conversion circuit.

The input end of the shift register is electrically connected with the signal interface 120, and the output end of the shift register is electrically connected with the first input end of the sample-and-hold circuit; the shift register is used for generating and outputting a shift signal according to the time sequence control signal.

The input end of the digital-to-analog conversion circuit is electrically connected with the output end of the data separation module 130, and the output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the sample hold circuit; the digital-to-analog conversion circuit is used for performing digital-to-analog conversion on the column pixel data and outputting the column pixel data.

The output end of the sample-and-hold circuit is electrically connected with the data line of a corresponding one of the monochrome pixel arrays 110; the sampling and holding circuit is used for sampling and holding data output by the digital-to-analog conversion circuit when a shifting signal output by the shifting register is effective, and outputting column pixel data to the pixel circuit when the corresponding row of pixel circuits is opened.

In another alternative embodiment, as shown in fig. 11, each column driving circuit 150 includes: the circuit comprises a shift register, a level conversion circuit, a sampling hold circuit and a digital-to-analog conversion circuit.

The input end of the shift register is electrically connected with the signal interface 120, and the output end of the shift register is electrically connected with the output end of the level conversion circuit; the shift register is used for generating and outputting a shift signal according to the time sequence control signal.

The output end of the level conversion circuit is electrically connected with the first input end of the sampling and holding circuit; the level conversion circuit is used for converting the shift signal output by the shift register into a level which can be received by the sampling holding circuit and outputting the level.

The output end of the sample-and-hold circuit is electrically connected to the data line of a corresponding one of the monochrome pixel arrays 110, and the sample-and-hold circuit is configured to sample and hold the column pixel data output by the digital-to-analog conversion circuit when the shift signal output by the level conversion circuit is valid, and output the column pixel data to the pixel circuit when the corresponding one row of pixel circuits is turned on.

Compared with the embodiment shown in fig. 10, the present embodiment adds a level shift circuit to implement level shift, so as to meet the operation requirement of the sample-and-hold circuit.

In one example, as shown in fig. 10 and 11, when the signal interface 120 includes the timing signal interface 120 and the video signal interface 120, an input terminal of the shift register is electrically connected to the timing signal interface 120, and an input terminal of the data separation module 130 is electrically connected to the video signal interface 120.

In one example, in the embodiment shown in fig. 10 and 11, the shift signals output by the shift registers in each column driving circuit 150 correspond to the same pixel position;

the sample-and-hold circuits in each column drive circuit 150 sample and hold pixel data for each column of the same pixel location at the same time.

In one example, the shift registers in the column driving circuits 150 shown in fig. 10 and 11 may operate simultaneously, and generate the same shift signal according to the timing control signal, that is, the shift signals output by the shift registers are all at the same position, and the shift registers may move from left to right or from right to left simultaneously, and further, the sample-and-hold circuits in the column driving circuits 150 may also operate simultaneously.

In one example, the sample-and-hold circuit may include a plurality of sample-and-hold modules with the same number of columns as the monochrome pixel array 110, and the shift register in each column driving circuit 150 outputs only one data valid signal at a time as a valid shift signal, which enables one of the sample-and-hold modules in the sample-and-hold circuit to start to operate, i.e., start to sample and hold data output from the digital-to-analog conversion circuit.

In one example, the shift register may output the shift signals in a serial shift order, so that each sample-and-hold module starts to operate in sequence, and the pixel data of each pixel column in the corresponding monochrome pixel array 110 is sampled and held in sequence.

In one example, the sample-and-hold circuit may further include a column driver, and the sample-and-hold module may sample and hold the monochrome pixel data converted and output by the digital-to-analog conversion circuit in the column driver, and when the row driving circuit 140 starts a certain pixel row of each monochrome pixel array 110, the column driver may output the corresponding monochrome pixel data to the pixel row; the column driver in each column driving circuit 150 can simultaneously output corresponding monochrome pixel data to the pixel row of the connected monochrome pixel array 110, thereby reducing chromatic dispersion caused by color combination of external optical devices; the pixel data sampled by the different sample and hold modules may be sequentially output by the column driver.

The embodiment of the application can repeatedly execute the scanning mode to realize progressive scanning and complete scanning of one frame of data, so that the scanning line frame and the frame frequency of each single-color display area are kept the same.

In an alternative embodiment, as shown in fig. 12, each column driving circuit 150 includes: the shift register group, the comparator array, the digital switch array, the cycle counter and the digital-to-analog conversion circuit;

the input end of the shift register group is electrically connected with the data separation module 130, and the output end of the shift register group is electrically connected with the input end of the comparator array; the shift register group is configured to receive the column pixel data output by the data separation module 130, and sequentially output the column pixel data corresponding to each column of pixels to the comparator array based on the shift signal.

The input end of the cycle counter is electrically connected with the signal interface 120, and the output end of the cycle counter is electrically connected with the input end of the digital-to-analog conversion circuit and the input end of the comparator array respectively; the cycle counter is configured to count according to the timing control signal output by the signal interface 120 and output a count value.

The output end of the comparator array is electrically connected with the first input end of the digital switch array; the comparator array is used for receiving the column pixel data output by the shift register group, comparing the column pixel data with the count value output by the cycle counter, outputting a switch control signal according to the comparison result and outputting the column pixel data; the switch control signal is used for controlling the on and off of the digital switch array.

The output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the digital switch array; the digital-to-analog conversion circuit is used for performing digital-to-analog conversion on the count value and outputting the converted analog voltage.

The output end of the digital switch array is electrically connected with the data line of the corresponding one of the monochrome pixel arrays 110; the digital switch array is used for outputting the analog voltage output by the digital-to-analog conversion circuit to the pixel circuit when the digital switch array is conducted and the corresponding row of pixel circuits is opened.

Referring to fig. 13, in the shift register group in the embodiment of the present application, the comparator array includes a plurality of comparators, the digital switch array includes a plurality of digital switches, the number of the shift registers, the number of the comparators and the number of the digital switches are the same, and is also the same as the number of the data lines output to the pixel circuit, the output end of the shift register in the shift register group is connected to the input end of each comparator in the comparator array in a one-to-one correspondence, the output end of each comparator in the comparator array is connected to the first input end of each digital switch in the digital switch array in a one-to-one correspondence, and the output end of each digital switch is connected to one data line.

In one example, when the comparison result of the comparator is true (1), the comparator can output a switch control signal for controlling the conduction of the digital switch, so that one digital switch connected with the comparator is conducted; when the comparison result of the comparator is false (0), the comparator can output a switch control signal for controlling the digital switch to be switched off, so that one digital switch connected with the comparator is switched off.

In another alternative embodiment, as shown in fig. 14, each column driving circuit 150 further includes: the circuit comprises a shift register group, a latch array, a comparator array, a level conversion circuit, a digital switch array, a cycle counter and a digital-to-analog conversion circuit.

The input end of the shift register group is electrically connected with the output end of the data separation module 130, and the output end of the shift register group is electrically connected with the input end of the latch array; the shift register group is configured to receive the column pixel data output by the data separation module 130, and sequentially output the column pixel data corresponding to each column of pixels to the latch array based on the shift signal.

The output end of the latch array is electrically connected with the input end of the comparator array; the latch array is used for receiving and storing the data of the shift front shift register group when the shift register group shifts.

The output end of the comparator array is electrically connected with the input end of the level conversion array; the comparator array is used for acquiring the column pixel data stored by the latch, comparing the column pixel data with the count value, outputting a switch control signal according to the comparison result and outputting the column pixel data; the switch control signal is used for controlling the on and off of the digital switch array.

The output end of the level conversion array is electrically connected with the first input end of the digital switch array; the level conversion array is used for converting the switch control signals and the column pixel data output by the comparator array into levels which can be received by the digital switch array and outputting the levels.

The output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the digital switch array, and the digital-to-analog conversion circuit is used for performing digital-to-analog conversion on the count value and outputting the converted analog voltage.

Compared with the embodiment shown in fig. 12, the embodiment adds the latch array, and can save the pixel data line of the mth line when the shift register in the shift register group shifts the pixel data of the M +1 th line, so as to implement pipeline operation and improve performance.

In one example, as shown in fig. 12 and 13, when the signal interface 120 includes the timing signal interface 120 and the video signal interface 120, an input terminal of the shift register is electrically connected to the timing signal interface 120, and an input terminal of the data separation module 130 is electrically connected to the video signal interface 120.

In one example, the loop counter in the embodiment of the present application may count from 0 to a maximum value, and then count from the maximum value to 0, where the maximum value may be set according to actual requirements.

In one example, each loop counter may store a counting step of a corresponding monochrome pixel, and the step of each loop counter may be adjusted according to actual needs, where the adjustment manner may be any one of the following three manners:

in the first mode, the adjustment is performed according to the memory in the cycle counter.

In the second mode, the counting step output by the timing controller is obtained, and the counting step output by the timing controller can be obtained through the timing signal interface 120. The time sequence controller comprises a gamma correction module, the input of the gamma correction module is a linear array, and the output of the gamma correction module is the step length of gamma correction data, so that the time sequence controller can give out counting step length when counting every time.

And thirdly, fitting the relation between the counting step length and the input in advance through a fitting algorithm, and then determining the counting step length according to the relation through a logic algorithm circuit.

The specific structure and connection of the shift register set, the comparator array and the digital switch array can refer to the foregoing description and the structural framework shown in fig. 13. The latch array in the embodiment of the application comprises a plurality of latches, the level shift array comprises a plurality of level shift circuits, the number of the latches is the same as that of the shift registers, the output ends of the shift registers in the shift register group are connected with the input ends of the latches in the latch array in a one-to-one correspondence mode, the output ends of the latches in the latch array are connected with the input ends of comparators in the comparator array in a one-to-one correspondence mode, the output ends of the comparators in the comparator array are connected with the input ends of the level shift circuits in the level shift array in a one-to-one correspondence mode, the output ends of the level shift circuits in the level shift array are connected with the first input ends of the digital switches in the digital switch array in a one-to-one correspondence mode, and each digital switch is connected with one data line.

In one example, as shown in fig. 12 and 14, the shift register groups in the column driving circuits 150 may output shift signals for the same pixel position at the same time, the cyclic counters may count for the same pixel position at the same time, the comparator arrays in the column driving circuits 150 may compare for the same pixel position at the same time, the digital-to-analog conversion circuits may perform digital-to-analog conversion for the same pixel position at the same time, and the digital switch arrays may output monochrome pixel data for the same pixel position at the same time, so that the light emitting devices of different colors at the same pixel position are simultaneously turned on, thereby reducing chromatic dispersion caused by color combination of external optical devices.

In the example of fig. 12 or 14, the digital-to-analog conversion circuit includes a digital-to-analog converter and a driver, an input of the digital-to-analog converter is electrically connected to an output of the cycle counter, an output of the digital-to-analog converter is electrically connected to an input of the driver, an output of the driver is electrically connected to each switch in the array of digital switches, and the driver is operable to drive the switches in the array of digital switches according to an output of the digital-to-analog converter.

In one example, since the light emitting characteristics of the light emitting devices of different colors are generally different, different (e.g., different bit widths or different counting rules) cyclic counters and different (e.g., different bit widths) digital-to-analog converters may be used for different light emitting devices to implement gamma correction on different color components, so as to improve color saturation and color rendering index, and the specific implementation manner of gamma correction may be determined according to actual requirements.

In one example, the data separation module includes an interpolation circuit for performing interpolation processing on the input video data to increase the number of bits of the video data, for example, from 8 bits of the input to 10-12 bits, which may be equal to the number of bits of the repetition counter and the number of input bits of the digital-to-analog converter, so that the gamma correction may be extended to 10-12 bits. When the step size of the repetition counter is 1, the interpolation circuit starts to operate, and the specific value of interpolation is determined according to the light emitting characteristics of the light emitting devices of different colors. Taking red, green and blue as an example, an input 8-bit value is converted into an output value of 10-12 bits according to the corresponding relationship of the gamma curves of the red, green and blue light emitting devices, the corresponding relationship can be written into a memory in an interpolation circuit through a configuration interface before the display works, and the memory of the interpolation circuit can be any one of an SRAM, a register and a non-volatile memory.

In one example, the timing control signal may include a row off signal, a duty ratio of the row off signal being a preset duty ratio; the signal interface 120 is further configured to receive second video data, the second video data having a larger amplitude than the first video data.

The timing sequence of the row shutdown signal can refer to the timing diagram shown in fig. 15 or fig. 16, the active level is the high level in fig. 15 or fig. 16, and the inactive level is the low level in fig. 15 or fig. 16. The time of the effective level corresponds to the starting time of a certain row of pixels, namely in the time range, the driving transistor of a certain row of pixel circuits is in a conducting state, the light-emitting device is driven to emit light, and the corresponding light-emitting device is also in a lighting state; the time of the invalid level corresponds to the turn-off time of a certain row of pixels, namely in the time range, the driving transistor of a certain row of pixel circuits is in a turn-off state, the light-emitting device is not driven to emit light any more, and the corresponding light-emitting device is also in a turn-off state.

Referring to the example shown in fig. 15, the on/off state of the driving transistors of a certain row of pixel circuits can be controlled by shortening the time of the active level, for example, the on time of 1 row in fig. 15, which can turn off the corresponding driving transistors in advance. Referring to the example shown in fig. 16, the on/off state of the driving transistor of a certain row of pixel circuits can be controlled by adjusting the ratio of the time of the active level to the time of the inactive level, for example, by increasing the time of the inactive level within the on time of 1 row as shown in fig. 16, and by turning off the driving transistor a plurality of times within the on time of 1 row.

Referring to the example shown in fig. 15 or 16, the active levels of the row turn-off signals of two adjacent rows have time intervals to ensure that the on-off state of the driving transistors is controlled in a row unit, the turn-off time of the driving transistors in each row is inconsistent, the driving transistors in each row are not turned off at the same time, and rolling turn-off is realized.

By increasing the video data amplitude (e.g., doubling the pixel voltage in the video data) on a rolling off basis, the brightness of the low gray scale pixels can be effectively adjusted. The voltage amplitude for lighting the low gray-scale pixel is very low, and can reach nA (nanoampere, 10)^-9Ampere), larger errors can be generated, the brightness of the low gray-scale pixels is inconsistent, the pixel lighting time can be shortened by rolling off and increasing the amplitude of the pixel voltage, and further the brightness of the low gray-scale pixels can be controlled, thereby being beneficial to improving the refreshing frequency and reducing the flicker feeling of human eyes.

In yet another alternative embodiment, as shown in fig. 17, each column driving circuit 150 includes: a clock tree, a parallel shift register bank, data latches, and column drivers.

The input end of the clock tree is electrically connected with the signal interface 120, the first output end of the clock tree is electrically connected with the parallel shift register group, and the second output end of the clock tree is electrically connected with the data latch respectively; the clock tree is used to output a first clock signal to the parallel shift register set and a second clock signal to the data latch according to the clock source of the signal interface 120.

The input end of the parallel shift register group is electrically connected with the data separation module 130, and the output end of the parallel shift register group is electrically connected with the input end of the data latch; the parallel shift register set is configured to receive the column pixel data output by the data separation module 130 and the first clock signal output by the clock tree, and perform shifting according to the second clock signal.

The output end of the data latch is electrically connected with the input end of the column driver; the data latch is used for latching column pixel data and latching and outputting the result of the parallel shift register group when the second clock signal is effective.

The output terminal of the column driver is electrically connected to a corresponding one of the monochrome pixel arrays 110; the column driver is used for outputting the data output by the data latch to the connected pixel circuit.

In one example, as shown in fig. 17, when the signal interface 120 includes the timing signal interface 120 and the video signal interface 120, an input terminal of the clock tree is electrically connected to the timing signal interface 120, and an input terminal of the data separation module 130 is electrically connected to the video signal interface 120.

Referring to the example of fig. 17, the pixel circuit in the embodiment of the present application adopts a digital driving technology, and includes a memory cell (e.g., SRAM with 1-bit bistable structure) and a pixel driving circuit (e.g., driving transistor), and the memory cell is electrically connected to the driving transistor in the pixel circuit.

In one example, the operation timings of the parallel shift register groups in the respective column driving circuits 150 are the same, and the operation timings of the data latches in the respective column driving circuits 150 are the same.

In one example, as shown in fig. 18, the clock trees in each column driving circuit 150 are homologous clock trees, the clock source may be a timing controller, the timing of the clock signal (first clock signal or second clock signal) generated by each clock tree is the same, the signal delay of the clock signal generated by each clock tree transmitted to all target nodes is the same, for example, the signal delay (hereinafter referred to as first delay) of the first clock signal transmitted to each clock node in the connected parallel shift register group is the same, the signal delay (second delay) of the second clock signal transmitted to each clock node in the connected data latches is the same, and the first delay and the second delay may be the same or different. Clock trees 1 to 3 in fig. 17 represent clock trees in the column driving circuit 150 to which the red pixel array, the green pixel array, and the blue pixel array shown in fig. 16 are connected, respectively.

In one example, each clock tree may have the same structure, for example, the same delay circuit may be used, and the interconnection lines are set to have the same length, so that the signal delay for transmitting the first clock signal generated by each clock tree to each clock node in the connected parallel shift register set may be the same, and thus the operation timing of each parallel register set may be the same, and the signal delay for transmitting the second clock signal generated by each clock tree to each clock node in the connected data latch may be the same, and thus the operation timing of each data latch may be the same.

In one example, as shown in fig. 19, the parallel shift register group of the embodiment of the present application includes t parallel shift register lines, each of which includes a plurality of parallel shift registers connected in series (each block in fig. 19 represents one parallel shift register). Each parallel shift register row may output shift data for one row and m columns (m is a positive integer, the same number of columns as monochrome pixel array 110).

In one example, the shift register at the same position in each parallel shift register row is used as a parallel shift register unit, which has t shift registers in total, that is, the output bit width of the unit is t (which represents the transmission bit width of data and may be 8 bits or an integer multiple of 8 bits), and if m parallel shift registers are included in the parallel shift register group, m/t parallel shift register units can be formed. The signal delay of the clock signal generated by the clock tree transmitted to each parallel shift register is the same, for example, within 1ns (nanosecond), so that the data signal of each parallel shift register is ensured to be stable in a small time before and after the clock edge, and the requirements of setup time and hold time are met.

In one example, each shift register in the parallel shift register unit may be a bidirectional parallel shift register, and each data latch may latch the column pixel data in the connected bidirectional parallel shift register at the same time under the control of a clock signal output by the clock tree after each shift of one row of parallel data is completed.

The operation of the parallel shift register set, the data latches, and the column drivers is described below with reference to the timing diagram of fig. 20 and the driving circuit of fig. 17:

under the control of the time sequence control signal, the three clock trees respectively output three first clock signals with the same time sequence as shift enable signals of the three parallel shift register groups, and also respectively output three second clock signals with the same time sequence as data latch signals; the row driving circuit 140 outputs a row driving signal.

Referring to fig. 20, when the shift enable signal is at a high level, the parallel shift register group performs shifting of data of an x-th row (x is a positive integer), when the shift enable signal jumps to a low level, shifting of the x-th row of data is completed, at this time, the data latch signal jumps from a low level to a high level, the data latch latches the x-th row of data in the parallel shift register group, the column driver signal is updated to data of the x-th row, when the data latch signal is at a low level, the column driver signal is kept stable, that is, when the x-th row of data is active, the row driving signal keeps stable for a while the column driver signal is stable, and data of the column driver is written into one monochrome pixel array 110 connected thereto. In one example, the active time for the row drive signals to remain on may cause three sets of column driver signals to be written to three monochrome pixel arrays 110 simultaneously, e.g., 1-50 ns.

In the example shown in fig. 17, the driving circuit of a silicon-based microdisplay according to the embodiment of the present application may further include a clear circuit (not shown in fig. 17), an input end of the clear circuit is electrically connected to the timing control interface, and receives a clear signal (which may be generated by the timing controller) transmitted by the timing control interface, and an output end of the clear circuit is electrically connected to the data latch, and the data in the data latch may be cleared quickly according to the clear signal, so as to blank each row.

In one example, the plurality of column driving circuits according to the embodiment of the present application may include at least one circuit structure as shown in fig. 10 to 11, fig. 12 to 14, and fig. 17, so that any one of a digital driving method, an analog driving method, and a digital-analog hybrid driving method may be implemented.

It should be noted that, in the embodiment of the present application, a case of three monochrome pixel arrays and three column driving circuits is mostly taken as an example for description, but the present application is not limited thereto, and those skilled in the art can understand that the numbers of the monochrome pixel arrays and the column driving circuits in the embodiment of the present application can be set according to actual requirements.

The technical scheme provided by the embodiment of the application at least has the following beneficial effects:

1) the embodiment of the application provides a silicon-based micro-display and a driving circuit thereof, which are provided with a data separation module, a plurality of corresponding column driving circuits and a plurality of monochrome pixel arrays.

2) The signal interface, the row driving circuit, the column driving circuit and the monochrome pixel array in the embodiment of the application can be integrated on the same monocrystalline silicon substrate, so that the integration level of the silicon-based micro-display is improved.

3) The time sequences of a plurality of rows of pixel data output by the data separation module in the embodiment of the application are the same, and the time sequences of driving signals output by pixel circuits at the same array position in each monochrome pixel array are the same, so that the light-emitting devices with different colors at the same pixel position can be driven at the same time, the light-emitting devices with different colors at the same pixel position can synchronously emit light, and the display effect is improved.

4) The column driving circuit in the embodiment of the present application may be driven by a plurality of driving manners, such as the driving manner based on the sample-and-hold circuit shown in fig. 10 and 11, the driving manner based on the digital-to-analog conversion circuit and the comparator shown in fig. 12 and 13, and the driving manner based on the digital scanning shown in fig. 16, which is flexible, and the corresponding driving manner may be selected according to actual requirements (e.g., requirements of resolution) to improve the driving capability of a specific scene; meanwhile, the different driving methods are widely applicable, for example, the driving method can be applied to the driving of some special display areas, such as circular or elliptical display areas.

It is to be understood that the present application is not limited to the particular arrangements and instrumentality described above and shown in the attached drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions or change the order between the steps after comprehending the spirit of the present application.

It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.

As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.

Claims

1. A driver circuit for a silicon-based microdisplay, comprising: the device comprises a signal interface, a data separation module, a row driving circuit, a plurality of column driving circuits and a plurality of monochrome pixel arrays, wherein the number of the monochrome pixel arrays is the same as that of the column driving circuits; each monochromatic pixel array comprises a plurality of pixel circuits which are used for driving a monochromatic sub-pixel and are arranged in an array;

the data separation module is configured to: extracting a plurality of color components in the first video data, generating column pixel data of each color component, and transmitting the plurality of column pixel data to a plurality of column driving circuits, respectively;

the row driver circuit is to: generating a row driving signal according to the timing control signal and transmitting the row driving signal to the plurality of monochrome pixel arrays through the scan line;

the column driver circuit is to: and transmitting the column pixel data to a corresponding one of the monochrome pixel arrays through the data line according to the timing control signal.

2. The driver circuit for a silicon-based microdisplay of claim 1 in which the signal interface, the row driver circuitry, the column driver circuitry and the monochrome pixel array are integrated on the same single crystal silicon substrate;

each monochromatic pixel array is laid on the monocrystalline silicon substrate, and a gap is reserved between every two adjacent monochromatic pixel arrays.

3. A drive circuit for a silicon-based microdisplay according to claim 1 in which the timing of a plurality of the column pixel data is the same;

the time sequence of the driving signals output by the pixel circuits at the same array position in each monochromatic pixel array is the same.

4. The driving circuit of a silicon-based microdisplay of claim 3 in which the delay time for a plurality of column pixel data transmitted by the data separation module to a plurality of column driving circuits is equal, and the attenuation magnitude of the signal when each column pixel data is transmitted by the data separation module to a corresponding one of the column driving circuits is less than or equal to a preset attenuation magnitude threshold.

5. The drive circuit of a silicon-based microdisplay of claim 1 in which the data separation module comprises: a decoding unit and a signal processing unit;

the decoding unit is used for decoding the first video data and separating out column pixel data of different color components;

when the first video data is a bit-plane signal, the signal processing unit is configured to perform at least one of waveform shaping, data grouping, and parallel-to-serial conversion on the column of pixel data separated based on the bit-plane signal;

when the first video data is an analog driving signal, the signal processing unit is configured to perform a gain on the column of pixel data separated based on the analog driving signal.

6. A drive circuit for a silicon-based microdisplay according to claim 1 in which the number of row drive circuits is at least one;

when the number of the row driving circuits is one, the plurality of the monochrome pixel arrays are electrically connected with the row driving circuits;

when the number of the row driving circuits is more than two, each of the monochrome pixel arrays is electrically connected with a corresponding one of the row driving circuits.

7. A drive circuit for a silicon-based micro-display according to claim 1, wherein each column drive circuit comprises: the circuit comprises a shift register, a sampling hold circuit and a digital-to-analog conversion circuit;

the input end of the shift register is electrically connected with the signal interface, and the output end of the shift register is electrically connected with the first input end of the sample-and-hold circuit; the shift register is used for generating a shift signal according to the time sequence control signal and outputting the shift signal;

the input end of the digital-to-analog conversion circuit is electrically connected with the output end of the data separation module, and the output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the sample hold circuit; the digital-to-analog conversion circuit is used for performing digital-to-analog conversion on the column pixel data and outputting the column pixel data;

the output end of the sampling and holding circuit is electrically connected with the data line of the corresponding single-color pixel array; the sampling and holding circuit is used for sampling and holding data output by the digital-to-analog conversion circuit when the shift signal output by the shift register is effective, and outputting the pixel data of the column to the pixel circuit when the corresponding row of the pixel circuits is opened.

8. A drive circuit for a silicon-based micro-display according to claim 1, wherein each column drive circuit comprises: the circuit comprises a shift register, a level conversion circuit, a sampling hold circuit and a digital-to-analog conversion circuit;

the input end of the shift register is electrically connected with the signal interface, and the output end of the shift register is electrically connected with the output end of the level conversion circuit; the shift register is used for generating a shift signal according to the time sequence control signal and outputting the shift signal;

the output end of the level conversion circuit is electrically connected with the first input end of the sampling and holding circuit; the level conversion circuit is used for converting the shift signal output by the shift register into a level which can be received by the sampling holding circuit and outputting the level;

the output end of the sampling and holding circuit is electrically connected with the data line of the corresponding one of the monochrome pixel arrays, and the sampling and holding circuit is used for sampling and holding the column pixel data output by the digital-to-analog conversion circuit when the shift signal output by the level conversion circuit is effective, and outputting the column pixel data to the pixel circuit when the pixel circuit of the corresponding row is opened.

9. A drive circuit for a silicon-based microdisplay according to claim 7 or 8 in which the shift signals output by the shift registers in each column drive circuit correspond to the same pixel location;

the sample-and-hold circuit in each of the column drive circuits samples and holds each of the column pixel data of the same pixel position at the same time.

10. A drive circuit for a silicon-based micro-display according to claim 1, wherein each column drive circuit comprises: the shift register group, the comparator array, the digital switch array, the cycle counter and the digital-to-analog conversion circuit;

the input end of the shift register group is electrically connected with the data separation module, and the output end of the shift register group is electrically connected with the input end of the comparator array; the shift register group is used for receiving the row pixel data output by the data separation module and sequentially outputting the row pixel data corresponding to each row of pixels to the comparator array based on a shift signal;

the input end of the cycle counter is electrically connected with the signal interface, and the output end of the cycle counter is electrically connected with the input end of the digital-to-analog conversion circuit and the input end of the comparator array respectively; the cycle counter is used for counting according to the time sequence control signal output by the signal interface and outputting a count value;

the output end of the comparator array is electrically connected with the first input end of the digital switch array; the comparator array is used for receiving the column pixel data output by the shift register group, comparing the column pixel data with the count value, outputting a switch control signal according to a comparison result, and outputting the column pixel data; the switch control signal is used for controlling the on and off of the digital switch array;

the output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the digital switch array; the digital-to-analog conversion circuit is used for performing digital-to-analog conversion on the counting value and outputting converted analog voltage;

the output end of the digital switch array is electrically connected with the data line of the corresponding monochromatic pixel array; the digital switch array is used for outputting the analog voltage to the pixel circuits when the digital switch array is conducted and the corresponding row of the pixel circuits is opened.

11. The drive circuit of a silicon-based microdisplay of claim 1 in which each column drive circuit further comprises: the circuit comprises a shift register group, a latch array, a comparator array, a level conversion circuit, a digital switch array, a cycle counter and a digital-to-analog conversion circuit;

the input end of the shift register group is electrically connected with the output end of the data separation module, and the output end of the shift register group is electrically connected with the input end of the latch array; the shift register group is used for receiving the column pixel data output by the data separation module and sequentially outputting the column pixel data corresponding to each column of pixels to the latch array based on a shift signal;

the output end of the latch array is electrically connected with the input end of the comparator array; the latch array is used for receiving and storing the data of the shift register group before shifting when the shift register group shifts;

the output end of the comparator array is electrically connected with the input end of the level conversion array; the comparator array is used for acquiring the column pixel data stored by the latch, comparing the column pixel data with the count value, outputting a switch control signal according to a comparison result, and outputting the column pixel data; the switch control signal is used for controlling the on and off of the digital switch array;

the output end of the level conversion array is electrically connected with the first input end of the digital switch array; the level conversion array is used for converting the switch control signals and the column pixel data output by the comparator array into levels which can be received by the digital switch array and outputting the levels;

the output end of the digital-to-analog conversion circuit is electrically connected with the second input end of the digital switch array, and the digital-to-analog conversion circuit is used for performing digital-to-analog conversion on the counting value and outputting the converted analog voltage;

12. A drive circuit for a silicon-based micro-display according to any of claims 7, 8, 10, 11, wherein the timing control signal comprises a row off signal, the duty cycle of the row off signal being a preset duty cycle;

the signal interface is further configured to receive second video data, wherein the second video data has a larger amplitude than the first video data.

13. A drive circuit for a silicon-based micro-display according to claim 1, wherein each column drive circuit comprises: a clock tree, a parallel shift register set, a data latch, and a column driver;

the input end of the clock tree is electrically connected with the signal interface, the first output end of the clock tree is electrically connected with the parallel shift register group, and the second output end of the clock tree is electrically connected with the data latch respectively; the clock tree is used for outputting a first clock signal to the parallel shift register group and outputting a second clock signal to the data latch according to a clock source of a signal interface;

the input end of the parallel shift register group is electrically connected with the data separation module, and the output end of the parallel shift register group is electrically connected with the input end of the data latch; the parallel shift register group is used for receiving the column pixel data output by the data separation module and a first clock signal output by the clock tree and shifting according to the second clock signal;

the output end of the data latch is electrically connected with the input end of the column driver; the data latch is used for latching the column pixel data and latching and outputting the result of the parallel shift register group when the second clock signal is effective;

the output end of the column driver is electrically connected with one corresponding monochromatic pixel array; the column driver is used for outputting the data output by the data latch to the connected pixel circuit.

14. A driver circuit according to claim 13 in which the parallel shift register banks in each column driver circuit operate at the same timing and the data latches in each column driver circuit operate at the same timing.

15. A silicon-based microdisplay, comprising: a light emitting device and a drive circuit for a silicon-based micro-display according to any of claims 1 to 14;

the driving circuit comprises a plurality of monochrome pixel arrays, wherein the monochrome pixel arrays are distributed in a plurality of monochrome display areas, and each monochrome pixel array is electrically connected with the light-emitting device of one color and used for driving the light-emitting device of the color to emit light.

16. The silicon-based microdisplay of claim 15 further comprising: at least one common electrode;

when the silicon-based microdisplay comprises a common electrode, a plurality of monochrome pixel arrays are electrically connected to the common electrode;

when the silicon-based microdisplay includes more than two common electrodes, each monochrome pixel array is electrically connected to a corresponding one of the common electrodes.

17. A silicon-based micro-display according to claim 15 or 16, further comprising: a time schedule controller;

the input end of the time schedule controller is connected with first video data of a target video, and the output end of the time schedule controller is electrically connected with a signal interface in the driving circuit;

the time sequence controller is used for generating a time sequence control signal aiming at the video data according to the first video data and outputting the first video data and the time sequence control signal.

18. The silicon-based microdisplay of claim 17 in which the timing controller is further configured to increase the amplitude of the first video data to obtain and output second video data when the timing control signal comprises a row off signal and the time for the active level of the row off signal is less than the preset value.