JP2005134645A - Liquid crystal display element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of source drivers to be used when driving TFT liquid crystal display elements specially for monochrome display without color filters by standard source drivers for color display driving. <P>SOLUTION: A display driving system is so arranged as to sequentially output a monochrome display data to each pixel from a timing controller 210 in synchronism with a clock signal, and between the timing controller 210 and the source driver 220, the system comprises a data delaying means 230 which, among the monochrome display data, holds two clock signals of monochrome display data for the nth pixel, also holding one clock signal of monochrome display data for the (n + 1)th pixel, and which, when the monochrome display data of the (n + 2)th pixel arrives or after the predetermined time, outputs each monochrome display data for the nth pixel, (n + 1)th pixel, and (n + 2)th pixel simultaneously to the source driver 220 (however, n = 1 + 3N (N is a positive integer including 0)), and a data output control means 240 which controls sampling timing of the data delaying means 230 with one third of the clock signal frequency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an active matrix type liquid crystal display element, and more particularly to a liquid crystal display element that performs only monochrome display with a source driver for color display driving.

  FIG. 3A schematically shows the array substrate 10 and its display drive system 20 included in an active matrix liquid crystal display element. In general, the array substrate 10 is provided with a color filter in which R (red), G (green), and B (blue) color elements are arranged in a stripe pattern. As shown in FIG. The pixel MP includes three sub-pixels SP of R, G, and B.

  A semiconductor switch element (not shown) such as a TFT (Thin Film Transistor), a TFD (Thin Film Diode), or an MIM (Metal Insulated Metal) is provided for each sub-pixel SP. Note that a combination of cyan, magenta, and yellow may be used instead of R, G, and B.

  The display drive system 20 includes a timing controller 21 and a source driver 22 for color display drive. The timing controller 21 outputs display data for each subpixel SP together with a clock signal. The source driver 22 has a large number of output terminals S1, S2, S3,... Corresponding to each column of the color filter, and a predetermined gradation voltage is subtracted via the semiconductor switch element based on display data from the timing controller 21. Applied to the pixel electrode.

  Here, operations of the timing controller 21 and the source driver 22 will be described with reference to the timing chart of FIG. It is assumed that display data for each sub-pixel SP output from the timing controller 21 is 6 bits (64 gradations). Further, for the convenience of explanation, each display data is provided with reference numerals S1, S2, S3,.

  The timing controller 21 outputs display data in units of one pixel MP for each clock signal CLK. That is, with the first clock signal CLK, R display data S1 including 6 bits of R00 to R05 for the output terminal S1 of the first column, and 6 bits of G00 to G05 for the output terminal S2 of the second column. The B display data S3 including 6 bits B00 to B05 is simultaneously sampled for the G display data S2 and the output terminal S3 in the third column.

  In the next second clock signal CLK, R display data S4 including 6 bits R00 to R05 for the output terminal S4 in the fourth column, and 6 bits G00 to G05 for the output terminal S5 in the fifth column are used. The G display data S5 including and the B display data S6 including 6 bits B00 to B05 are sampled simultaneously for the output terminal S6 in the sixth column. This is sequentially repeated in units of 1 pixel MP.

  The source driver 22 operates based on the clock signal CLK sent from the timing controller 21, latches display data for three pixels (in this case, three subpixels) for each clock signal CLK, and array substrate Ten adjacent three pixels (in this case, three adjacent sub-pixels) are given.

  That is, the R display data S1, the G display data S2, and the B display data S3 (18 bits in total) are latched by the first clock signal CLK, and correspond to each display data from the output terminals S1, S2, S3. The gradation voltage to be output is output by the output enable signal. In the next clock signal CLK, the R display data S4, the G display data S5, and the B display data S6 are latched, and the gradation voltages corresponding to the display data are similarly output by the output enable signal. . This is repeated below.

  In this way, the color display driving source driver 22 operates so as to latch three display data for each of the R, G, and B sub-pixels for each clock signal CLK. This type of operation is generally widely used as a standard source driver for color display driving.

  The active matrix type liquid crystal display element (hereinafter sometimes referred to as a TFT liquid crystal display element) is generally a color display, and the display data for the three sub-pixels SP included in one pixel MP is the same. By doing so, monochrome display can be achieved. However, for example, in order to reduce costs, there is the following problem when a TFT liquid crystal display element is used exclusively for monochrome display without providing a color filter.

  That is, most of the standard source drivers for TFT liquid crystal display devices are currently used for color display driving. Therefore, even when dedicated to monochrome display, color source drivers can be used from the standpoint of availability and price. A standard source driver for display drive will be used.

  However, since the standard source driver outputs in R, G, and B units as described above, the number of use is the same as in the case of color display even though it is monochrome display. Cannot be achieved.

  If a source driver dedicated to monochrome display is used as a custom specification, the number of use can be reduced. However, since the price of the custom specification is higher than that of the standard specification, the overall cost is not reduced.

  Accordingly, an object of the present invention is to reduce the number of use even when a standard source driver for color display driving is used when a TFT liquid crystal display element is used exclusively for monochrome display without providing a color filter. There is.

  In order to solve the above problems, an invention according to claim 1 of the present application includes an array substrate based on an active matrix system having a semiconductor switch element for each pixel, a timing controller that outputs display data for each pixel together with a clock signal, A color display driving source driver that latches display data for three pixels for each clock signal output from the timing controller and supplies the data to three adjacent pixels on the array substrate. In the liquid crystal display element that performs only monochrome display using the source driver, monochrome display data for each pixel is sequentially output from the timing controller together with the clock signal. Among the monochrome display data sequentially output from the timing controller, the n-th pixel monochrome display data is held for two clock signals of the clock signal, and the n + 1 pixel monochrome display data is Holds one clock signal of the clock signal, and outputs the monochrome display data of the nth pixel, the n + 1th pixel, and the n + 2 pixel to the source driver at the time when the n + 2th pixel monochrome display data arrives or after a predetermined time. Data delay means (where n is 1 + 3N (N is a positive integer including 0)) and data output control for controlling the sampling timing of the data delay means for the source driver at a frequency of 1/3 of the clock signal. And a means.

  In the invention according to claim 2 of the present application, the size of each pixel includes R, G, B as sub-pixels or a color trio corresponding thereto, and a black mask is formed between the pixels. It is characterized by being.

  According to the first aspect of the present invention, since the monochrome display data for three pixels are aligned and simultaneously output by the data delay means, the source driver for color display driving has three pixels for each clock signal. It is possible to match the function of latching display data for minutes. Therefore, when the TFT liquid crystal display element is exclusively used for monochrome display without providing a color filter, the number of source drivers used for color display driving can be reduced to 1/3.

  According to the invention according to claim 2 of the present application, a black mask is provided only between each pixel (between main pixels), and unlike a color display having sub-pixels, there is no black mask in each pixel. Accordingly, a bright display can be obtained. Further, since the driving frequency of the source driver is reduced to 1/3 compared to the case of color display, it is easy to take measures against unnecessary radiation.

  Next, an embodiment of the present invention will be described with reference to FIGS. 1 and 2, but the present invention is not limited to this. FIG. 1 is a schematic view showing only a main part of a liquid crystal display element according to the present invention, and FIG. 2 is a timing chart for explaining the operation of the present invention.

  The liquid crystal display element according to the present invention is of an active matrix type, and FIG. 1 shows its array substrate 100 and its display drive system 200. A large number of pixels MP are arranged in a matrix on the array substrate 100, and each pixel MP is provided with a semiconductor switch element (not shown) such as a TFT. Although not shown, a common electrode substrate is disposed to face the array substrate 100.

  Although the liquid crystal display element of the present invention is a TFT liquid crystal display element, a color filter is not formed on the array substrate 100 because it is exclusively for monochrome display. The size per pixel MP is preferably about 180 × 180 μm or 240 × 240 μm including the three sub-pixels SP of R, G, and B as shown in FIG.

  As described above, preferably, one pixel MP is formed in the same size as that in the case of color display. However, since the sub-pixel SP is not included, the black mask (light-shielding film) BM is provided only between the pixels MP. High brightness can be obtained compared to monochrome display.

  The display driving system 200 includes a timing controller 210 and a source driver 220. The timing controller 210 may have the same function as that of the timing controller 21 provided in the above-described conventional example. However, in the present invention, the timing controller 210 uses each pixel column of the array substrate 100 for each clock signal. The monochrome display data for L1, L2, L3.

  As for the source driver 220, the source driver 22 used in the above-described conventional example, that is, a color display driving standard that latches and outputs display data for three pixels (columns) for each clock signal. The source driver is used as it is.

  The source driver 220 is a driver for driving the source electrode of each TFT via a data signal line (not shown), and the data signal line is wired along the column direction (vertical direction in FIG. 1) of the array substrate 100. Yes.

  Further, on the array substrate 100, gate electrode lines (not shown) connected to the gate electrodes of the TFTs are wired along the row direction (left and right direction in FIG. 1), and the gate electrode lines are not shown. It is connected to the. Note that the gate driver is a driver that sequentially scans each gate electrode line at a predetermined duty ratio, and the operation thereof may be a known one. Therefore, the description thereof is omitted here.

  The output terminals S1, S2, S3... Of the source driver 220 are connected to the respective pixel columns L1, L2, L3. Since it is monochrome display data for one pixel column per clock signal, it cannot operate normally as it is.

  Therefore, in the present invention, the data delay unit 230 and the data output control unit 240 for controlling the data sampling timing of the data delay unit 230 are provided between the timing controller 210 and the source driver 220.

  In this example, the data delay unit 230 includes a first latch circuit 231, a second latch circuit 232, and a buffer circuit 233 connected in series to the data line D extending from the timing controller 210 to the source driver 220.

  The data output control means 240 includes a reference clock generation circuit 241 and a 1/3 clock generation circuit 242 connected in series to a clock line C from the timing controller 210 to the source driver 220.

  The reference clock generation circuit 241 generates a reference clock signal Cb (= Ca) having the same frequency as that based on the clock signal Ca from the timing controller 210, and provides it to the second latch circuit 232 and the 1/3 clock generation circuit 242. The 1/3 clock generation circuit 242 generates a clock signal Cc having a frequency that is 1/3 of the frequency of the reference clock signal Cb, and supplies it to the second latch circuit 232 and the source driver 220.

  Here, the reason why the reference clock generation circuit 241 is provided will be described. The clock signal Ca is an internal clock of the timing controller 210, and its waveform is generally unstable. Therefore, if the 1/3 clock is generated directly from the clock signal Ca, the waveform becomes unstable. Therefore, the reference clock generation circuit 241 uses the reference clock signal having the same frequency waveform from the clock signal Ca. Cb is obtained.

  The first latch circuit 231 outputs the monochrome display data sent from the timing controller 210 to the second latch circuit 232 for each cycle of the clock signal Ca. In this example, the second latch circuit 232 is composed of a shift register, latches monochrome display data from the first latch circuit 231 at, for example, the rising edge of the reference clock signal Cb, and completes one cycle of the clock signal Cc. Is output.

  Next, operations of the data delay unit 230 and the data output control unit 240 will be described with reference to the timing chart of FIG. It is assumed that the monochrome display data sent from the timing controller 210 is 6 bits (64 gradations).

  First, the timing controller 210 outputs monochrome display data (6 bits including D0 to D5) for one pixel column for each clock signal Ca. That is, the monochrome display data LS1 for the first pixel column L1 by the first first clock signal Ca, the monochrome display data LS2 for the second pixel column L2 by the second clock signal Ca, and the third clock signal. Monochrome display data is sequentially output with Ca as monochrome display data LS3 for the third pixel row L3.

  Then, as shown in FIG. 2A, the first latch circuit 231 samples the monochrome display data LS1, LS2, LS3... In the second latch circuit 232 for each cycle in accordance with the clock signal Ca from the timing controller 210. To do. That is, in this example, the first latch circuit 231 is used as a phase matching latch circuit.

  The second latch circuit 232 latches the monochrome display data from the first latch circuit 231 at, for example, the rising edge of the reference clock signal Cb (not shown), but the data is shifted to the next stage after one cycle of the clock signal Cc. Sampling is performed in the buffer circuit 233.

  This will be described for the monochrome display data LS1 to LS3 of the first pixel column L1 to the third pixel column L3. As shown in FIG. 2B, the second latch circuit 232 is the first pixel column latched first. The monochrome display data (D0 to D5) LS1 of L1 is held for two clocks of the reference clock signal Cb. The monochrome display data (D10 to D15) LS2 of the second pixel row L2 latched second is held for one clock of the reference clock signal Cb.

  Then, after latching the monochrome display data (D20 to D25) LS3 of the third third pixel row L3, the monochrome display data LS1 to LS3 are simultaneously transferred to the buffer circuit 233 in the next stage at the first rise of the clock signal Cc. To sample. Thereafter, this is repeated to sample monochrome display data LS4 to LS6, LS7 to LS9,.

  As a result, the source driver 220 can simultaneously latch monochrome display data of a total of 18 bits for three pixel columns using the clock signal Cc as a trigger, and operates normally as in the case of color display. That is, the monochrome display data LS1 to LS3 are output from the corresponding output terminals S1 to S3.

  Therefore, since the output terminals S1 to S3 assigned to the three sub-pixels SP included in one pixel MP in the case of color display can be assigned to each pixel MP in the monochrome display of the present invention, the source driver 220 is set to 1 / 3. Further, since the driving frequency of the source driver 220 is reduced to 1/3 compared to the case of color display, measures against unnecessary radiation can be facilitated.

The schematic diagram which shows only the principal part of the liquid crystal display element by this invention. The timing chart for operation | movement explanation of the data delay means and data output control means in this invention. The schematic diagram which shows the array substrate with which the liquid crystal display element by the conventional active matrix system is provided, and its display drive system. The timing chart for operation | movement description of the display drive system in the said conventional liquid crystal display element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Array substrate 200 Display drive system 210 Timing controller 220 Source driver bar 230 Data delay means 231 1st latch circuit 232 2nd latch circuit 233 Buffer circuit 240 Data output control means 241 Reference clock generation circuit 242 1/3 lock generation circuit MP pixel BM black mask

Claims (2)

An active matrix array substrate having a semiconductor switch element for each pixel, a timing controller for outputting display data for each pixel together with a clock signal, and a display for three pixels for each clock signal output from the timing controller A color display driving source driver that latches data and supplies it to three adjacent pixels on the array substrate, and removes the color filter from the array substrate and performs only monochrome display using the source driver. In the element
Monochrome display data for each pixel is sequentially output together with the clock signal from the timing controller, and n of monochrome display data sequentially output from the timing controller between the timing controller and the source driver. The monochrome display data of the pixel is held for two clock signals of the clock signal, and the monochrome display data of the n + 1 pixel is held for one clock signal of the clock signal, and the monochrome display data of the (n + 2) pixel has arrived. Data delay means for simultaneously outputting the monochrome display data of the nth pixel, the n + 1th pixel and the n + 2th pixel to the source driver at the time or after a predetermined time (where n is 1 + 3N (N is a positive integer including 0)) And the above clock The liquid crystal display element characterized by comprising a data output control means for controlling the sampling timing at 1/3 of the frequency of that item to the source driver of the data delay unit.   2. The size of each pixel is a size including R, G, B as sub-pixels or a color trio corresponding thereto, and a black mask is formed between the pixels. The liquid crystal display element as described.

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