JPH07152348A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To provide a signal processing circuit capable of realizing two inputs of an RGB input and a highly fine monochromatic input only by changing a timing signal with the same circuit constitution. CONSTITUTION:In the case of a color display, color signals of RGB are inputted to an R-input 3, a G-input 4 and a B-input 5 and subjected to serial-parallel conversions by three sample-and-hold circuits 30, 40, 50, respectively. Three data inverting circuits 60, 70, 80 having jointly a function for amplifying a converted signal to a video signal level required for a liquid crystal module 10 and a polarity inverting/non-inverting function with respect to a reference voltage to prevent the flicker of the liquid crystal are connected to sample-and- hold circuits 30, 40, 50, respectively. In the case of a monochromatic display, signal processions are performed by changing only the timing signal by inputting monochromatic signals of the same signals to the R-input 3, the G-input 4 and the B-input 5 with the same circuit constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit of an active matrix liquid crystal display device, and in particular, it utilizes a RGB separate video signal and a horizontal synchronizing signal HD and a vertical synchronizing signal VD which are used in a personal computer or the like. The present invention relates to a signal processing circuit capable of inputting display data and timing signals necessary for operating an active matrix liquid crystal display device and sharing both color display and high-definition monochrome display as a liquid crystal display method.

[0002]

2. Description of the Related Art Conventionally, this kind of signal processing circuit has been used for the purpose of reducing the development cost of a drive circuit dedicated to color by sharing color / monochrome display in an interface section. For example, as shown in Japanese Patent Laid-Open No. 63-74099, color display data equivalent to an interface signal to an R, G, B CRT display device is converted into parallel, and the converted parallel signal has regularity. A color display data processing circuit section configured by a circuit group that switches the parallel signals in a time division manner by applying a color mixture color arrangement means for the case of monochrome display,
The monochrome display data processing circuit has a switching circuit group for performing parallel conversion of at least one display data of R, G, and B and performing time-division switching.

FIG. 9 shows the relationship between the liquid crystal panel and the X-direction driver for monochrome display. FIG. 10 shows the relationship between the liquid crystal panel and the X-direction driver in the case of color display. 9,
From FIG. 10, the configuration of the peripheral circuit of the liquid crystal panel is different between monochrome display and color display. Note that, here, a structure in which an X driver, a Y driver, and a liquid crystal panel are connected is referred to as a liquid crystal module.

[0004]

The interface circuit of the conventional liquid crystal display device has a signal processing system which can be used for both color display and monochrome display.
Since the signal processing unit rearranges the video signals by using the switching circuit, a large number of switching circuits are required, which causes a problem that the circuit configuration becomes complicated.

Further, in terms of cost, there is a problem in that the liquid crystal module cannot be used for both color display and monochrome display.

[0006]

According to the present invention, input means for inputting an analog video signal, and serial-parallel conversion of the analog video signal respectively connected to the input means and sending out a parallel output signal. First, second, and third sample-hold circuits are connected to the first, second, and third sample-hold circuits, respectively, and the parallel output signals are amplified and inverted / reversed at every horizontal time. A first, a second, and a third data inversion circuit having an inversion function of non-inversion, and a liquid crystal module connected to the first, second, and third data inversion circuits and provided with a liquid crystal display device. , The first, second, and third sample and hold circuits, the first, second, and third data inversion circuits, and the sample and hold circuits and the data units connected to the liquid crystal module. An inversion circuit and a timing control unit that generates a timing necessary for the liquid crystal module, and includes the first, second, and third sample-hold circuits and the first, second, and third data inversion circuits. By changing the timing signal from the timing control section without changing the circuit configuration of the circuit, a signal processing circuit can be obtained which performs monochrome display and color display on the liquid crystal display device.

Further, according to the present invention, in the case of signal processing for color display, the input means comprises first, second and third input sections, and the first, second and third input sections are provided. Input sections are respectively connected to the first, second and third sample and hold circuits, RGB signals are respectively input to the first, second and third input sections, and the first and second , And the third sample and hold circuit respectively include a plurality of first
Timing signals out of phase from the timing control section, each of which has a front stage sample hold and a rear stage sample hold, a plurality of second front stage sample hold and a rear stage sample hold, and a plurality of third front stage sample hold and a rear stage sample hold. Are sequentially input to the plurality of first, second, and third pre-stage sample / holds, and the plurality of first, second, and third pre-stage sample / hold switches are sequentially switched. The RGB signals are captured as data into the plurality of first, second, and third pre-stage sample-holds, respectively, and the timing control unit outputs timing signals in phase with each other. The plurality of first, second, and third input signals are input to the second and third latter-stage sample and hold units. By simultaneously switching a plurality of switches of each of the third and third post-stage sample and hold, phase-aligned serial-to-parallel conversion is performed, and a plurality of the first, second, and third post-stage sample and hold are respectively performed. A signal processing circuit is obtained which is characterized in that parallel output signals are sent out.

Further, according to the present invention, in the case of signal processing for monochrome display, the first, second and third sample and hold circuits are connected to each other and a monochromatic video signal is inputted to the input means. The first, second, and third sample and hold circuits respectively include a plurality of first pre-stage sample and hold and a second stage sample and hold, and a plurality of second sample and hold circuits.
Of the first, second, and third sample-holds, and the plurality of third sample-holds and third-stage sample-holds. 3 are sequentially input to the previous sample-hold, and the plurality of first, second, and third sample-hold switches are sequentially switched,
The monochromatic video signal is captured as data in each of the plurality of first, second, and third pre-stage sample and hold, and the timing signals in phase from the timing control unit are respectively provided in the plurality of first, The serial-parallel conversion is input to the second and third latter-stage sample and hold, and by simultaneously switching all the plurality of switches of the plurality of first, second, and third latter-stage sample and hold, phase-aligned serial-parallel conversion is performed. A plurality of parallel output signals are transmitted from each of the plurality of first, second, and third post-stage sample and hold circuits, and a signal processing circuit is obtained.

Further, according to the present invention, when a monochrome video signal is input, a monochrome display is made on the liquid crystal display device, and when an RGB signal is input, a color coloring filter is provided on the liquid crystal display device. By mounting, a signal processing circuit characterized by color display is obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The RGB input signal processing circuit 1 has one system for inputting each RGB signal. The first input means
Has an input unit 3, a second input unit 4, and a third input unit 5. The input unit 3 (hereinafter referred to as R input 3) is for inputting an R signal, and the input unit 4 (hereinafter referred to as G input 4) is for G
Input unit 5 (hereinafter referred to as B input 5) for signal input
Is used for B signal input. The first sample and hold circuit (hereinafter referred to as S / H circuit) 30 has an R input 3
And the first data inversion circuit 60 and the timing control 9 are connected, and the second S / H circuit 40 is connected to the G input 4, the second data inversion circuit 70, and the timing control 9. , The third S / H circuit 50 is connected to the B input 5, the third data inverting circuit 80, and the timing control 9.

A sampling clock CK generated by the timing control 9 is used to convert an analog input signal (analog video signal) from serial to parallel (hereinafter referred to as S / S).
(P conversion). Data inverting circuits 60, 70, 80 for inverting the S / P converted parallel output signals
Are connected to the liquid crystal module 10 and the timing control 9, respectively, and generate video signals necessary for driving the liquid crystal.

Next, the operation of the color signal processing circuit shown in FIG. 1 will be described with reference to FIGS. Figure 3 shows S /
FIG. 4 is an internal configuration diagram of an H circuit, and FIG. 4 is a diagram showing a time chart of the S / H circuit.

An analog input signal (analog video signal) is input to a plurality of channels (8 in this embodiment) by using a plurality of S / H circuits.
S / P conversion to an analog signal of ch). As shown in FIG. 3, the sample-hold circuit is composed of eight first-stage S / Hs as front-stage S / Hs and eight second-stage S / Hs as rear-stage S / Hs. . That is, the S / H circuit 30
The S / H circuit 40 includes a first front stage S / H and a rear stage S / H, and the S / H circuit 40 includes a second front stage S / H and a rear stage S / H.
The / H circuit 50 includes a third front stage S / H and a rear stage S / H. Here, in this embodiment, the first front stage S / H
Eight S / Hs are provided in each of the rear S / H, the second front S / H and the rear S / H, and the third front S / H and the rear S / H. Note that in FIG. 3, only the internal configuration of one of the three sample-hold circuits is shown, and the remaining two sample-hold circuits are omitted.

Timing control 9 A → B → C →
Timing signals are input to the eight first-stage S / Hs in the order of D → E → F → G → H. By inputting the phase-shifted timing signals to the eight S / Hs, the analog input signal data (a to h in FIG. 4) is temporarily taken into the first S / H. The video data when a timing signal is input with eight S / Hs has a phase shift at each input timing.

The analog input signals input by switching all the video data at the second stage S / H switch P at the same time are parallel output 11, parallel output 12, parallel output 13, parallel output 14, parallel output 15,
Parallel output 16, parallel output 17, parallel output 1
Therefore, S / P conversion in which the phases are uniform can be performed.

Next, the data inversion circuit will be described.
FIG. 5 is a diagram showing the internal configuration of the data inverting circuit and the input waveform. The data inversion circuits 60, 70, 80 are connected to the S / H circuits 30, 40, 50, respectively, and have a function of amplifying to a video signal level required by the liquid crystal module 10, and preventing flicker of the liquid crystal and extending the life of the liquid crystal. Therefore, it also has the function of inverting / non-inverting the polarity of analog data with respect to the reference voltage.

The input video signal is inverted and non-inverted signal is generated in this circuit by using two operational amplifiers having an amplification factor of 1. The operational amplifier 7 generates non-inverted data, the operational amplifier 8 generates inverted video data, and the inversion pulse input switches the switch to invert / non-invert the video signal. The data inversion circuits 60, 70, 80 are connected to the liquid crystal module 10 and send necessary video signals to the liquid crystal module 10.

In the case of RGB input method, R input 3
The S / H circuit 30 and the data inverting circuit 60 are configured as one system. Similarly, G input 4 and S / H circuit 4
0 and the data inverting circuit 70 constitute one system, and the B input 5, the S / H circuit 50 and the data inverting circuit 80 constitute one system. It can be considered that there are three systems of the same circuit in each system, and the circuits of the three systems operate with the same timing signal. The RGB input processing circuit 1 has S
/ H circuits 30, 40, 50 and data inversion circuits 60, 7
0, 80, a liquid crystal module 10, and a timing control 9 for generating a necessary timing signal.

FIG. 2 is a block diagram showing one embodiment for performing monochrome display according to the present invention. This configuration shares the circuit configuration for performing color display in FIG. That is, the present invention is
The timing control 9 is divided into one for color display and the other for monochrome display, and by adopting a configuration for switching timing signals, respective signal processing can be performed. In the case of the signal processing circuit for monochrome display, the monochrome signal input 6 is connected to the S / H circuits 30, 40 and 50,
S / P conversion is performed in each S / H circuit. Furthermore, S
The / H circuits 30, 40 and 50 are connected to each other and to the data inverting circuits 60, 70 and 80 and the timing control 9. The sample-and-hold video signal is level-converted into a video signal required for the liquid crystal module 10 by a data inverting circuit.

Next, the operation of the monochrome signal processing circuit shown in FIG. 2 will be described. In the case of monochrome signal processing, the width of one pixel on the screen is shifted at a frequency of 1/3 of the clock used for RGB input, that is, the phase of the dot clock (dot CK) that determines the sampling interval is shifted by one clock. The sample hold is performed using the clock.

FIG. 6A is a diagram showing the configuration of the sample hold circuit of the monochrome display signal processing circuit.
FIG. 6B is a diagram showing a monochrome display clock wave, and FIG. 6C is a diagram showing a parallel-converted video output from the sample hold circuit of FIG. 6A. By inputting the sampling clock in the order of repeating the S / H circuit 30 → S / H circuit 40 → S / H circuit 50, the video input signal as the monochrome signal is S / P converted. Clock 1 (CK1) is a sampling clock for the S / H circuit 30. Clock 2 (CK2) is a sampling clock for the S / H circuit 40. Similarly, clock 3 (CK
3) is a sampling clock of the S / H circuit 50.

In the case of analog data having levels such as A, B, C, D, E, F, G ...
Sample and hold every other data. S / H circuit 3
The outputs 0, 40, and 50 output video outputs 1, 2, and 3, respectively. From the chart, S in 8 layers of A, D, G ... V
/ P-converted video signal is obtained. Similarly, in the S / H circuit 40, a video signal is S / P-converted into eight layers of B, E, H ... W, and in the S / H circuit 50, S / P is converted into eight layers of C, F, I ... X.
A P-converted video signal can be obtained.

That is, the three S / H circuits 3 are used for the clock phase with the above-mentioned timing by using the three S / H circuits.
By inputting 0, 40 and 50, it is possible to obtain a signal obtained by expanding the monochrome input signal into 24 layers. The signal inversion circuit 60, 70, 80 performs signal processing on the video signal expanded in 24 layers to perform polarity inversion / non-inversion of the video signal as in the case of color display, and the necessary video signal is input to the liquid crystal module 10. taking it. The arrangement of the video data when actually displayed on the liquid crystal panel is shown in FIG. 7, and the arrangement of the data on the liquid crystal panel is the same for both color display and monochrome display. In the case of color display, color display can be easily realized by mounting the color coloring filter shown in FIG. 8 on the liquid crystal panel.

[0025]

According to the present invention, the signal processing circuit of the active matrix liquid crystal display is provided on the same substrate,
Since the signal processing circuit for color display and the signal processing circuit for high-definition monochrome display can be realized, the development cost of the board can be reduced and the parts can be shared.

Further, in the liquid crystal module part, in the case of color display even with the same liquid crystal panel, it can be realized by mounting a color coloring filter on the liquid crystal panel in the manufacturing process.

In the case of monochrome display, monochrome display is possible without mounting a color coloring filter. Therefore, the liquid crystal panel can be shared, and the development cost of the liquid crystal panel, which is an expensive part in the liquid crystal display device, can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal processing circuit for performing color display according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a signal processing circuit for performing monochrome display according to the present invention.

FIG. 3 is an explanatory diagram showing an internal configuration of a sample hold circuit.

FIG. 4 is an explanatory diagram showing a time chart of a sample hold circuit.

FIG. 5 is an explanatory diagram showing an internal configuration of a data inverting circuit and an input waveform.

6A is a diagram showing a configuration of a sample hold circuit of a monochrome display signal processing circuit, and FIG.
6B is a diagram showing a monochrome display clock wave input to the sample hold circuit of FIG. 6A.
FIG. 6C is a diagram showing a parallel-converted video output from the sample hold circuit of FIG. 6A.

FIG. 7 is an explanatory diagram showing a data arrangement in a liquid crystal panel.

FIG. 8 is an explanatory diagram showing a configuration of a color filter.

FIG. 9 is an explanatory diagram showing a conventional monochrome display liquid crystal module.

FIG. 10 is an explanatory view showing a conventional color display liquid crystal module.

[Explanation of symbols]

1 RGB input signal processing circuit 2 Monochrome input signal processing circuit 3 R input 4 G input 5 B input 7, 8 operational amplifier 9 Timing control 10 Liquid crystal module 30, 40, 50 S / H circuit 60, 70, 80 Data inversion circuit 101, 102, 103, 111, 112, 113, 1
17, 118, 119 X driver 104, 105, 106, 114, 115, 116
Y driver

Claims (4)

[Claims] 1. Input means for inputting an analog video signal, and first, second, and third means connected to the input means for serial-parallel converting the analog video signal and sending a parallel output signal. A sample-hold circuit and the first, second, and third sample-hold circuits, respectively, for amplifying the parallel output signals,
A first, second, and third data inversion circuit having an inversion function of inversion / non-inversion every horizontal time, and a liquid crystal display connected to the first, second, and third data inversion circuits. A liquid crystal module including a device, the first, second, and third sample hold circuits, the first, second, and third data inversion circuits, and the liquid crystal module connected to each of the samples. A hold circuit, each of the data inversion circuits, and a timing control unit that generates a timing necessary for the liquid crystal module, and the first, second, and third sample and hold circuits and the first,
A signal characterized by performing monochrome display and color display on the liquid crystal display device by changing the timing signal from the timing control section without changing the circuit configurations of the second and third data inversion circuits. Processing circuit. 2. The signal processing circuit according to claim 1,
In the case of signal processing for color display, the input means includes first, second and third input sections, and the first, second and third input sections are provided.
And a third input section are respectively connected to the first, second and third sample and hold circuits, and the first, second and third sample and hold circuits are respectively connected.
RGB signals are input to the third and third input sections, respectively, and the first, second, and third sample-and-hold circuits respectively include a plurality of first pre-stage sample-holds and post-stage sample-holds, and a plurality of second pre-stages. A sample hold and a rear sample hold, and a plurality of third front sample hold and a rear sample hold are provided, and the timing signals whose phases are deviated from the timing control unit are output to the plurality of first, second and third samples. The plurality of first, second, and third pre-stage sample and hold switches are sequentially input to the pre-stage sample and hold, and the plurality of first, second, and third pre-stage sample and hold switches are sequentially switched.
The RGB signals are captured as data in the front-end sample and hold, and the timing signals whose phases are aligned are input from the timing control section to the plurality of first, second, and third rear-end sample and hold, respectively. Serial-parallel conversion in which the phases are aligned is performed by simultaneously switching all of the plurality of switches of each of the plurality of first, second, and third latter-stage sample and hold, and the plurality of first, second, and 3. A signal processing circuit, wherein a plurality of parallel output signals are sent out from each of the third stage sample and hold stages. 3. The signal processing circuit according to claim 1,
In the case of signal processing for monochrome display, the first, second,
And a third sample and hold circuit are connected to each other, a monochromatic video signal is inputted to the input means, and the first, second and third sample and hold circuits are respectively provided with a plurality of first pre-stage sample and hold circuits. A second-stage sample hold, a plurality of second front-stage sample hold and a second-stage sample hold, and a plurality of third front-stage sample hold and a second-stage sample hold. The plurality of first, second, and third pre-stage sample and hold switches are sequentially input to the first, second, and third pre-stage sample and hold switches, so that the plurality of switches are sequentially switched. The monochromatic video signal is captured as data in each of the first, second, and third pre-stage sample and hold, In addition, the timing signals having the same phase are input from the timing control unit to the plurality of first, second, and third rear sample-holds, respectively, and the plurality of first, second, and third rear stages are input. Serial-parallel conversion in which the phases are aligned is performed by simultaneously switching all of the plurality of switches of the sample and hold, and a plurality of parallel output signals are sent from each of the plurality of first, second, and third post-stage sample and hold. A signal processing circuit characterized by being performed. 4. The signal processing circuit according to claim 1,
When a monochrome video signal is input, monochrome display is performed on the liquid crystal display device, and when an RGB signal is input, color display is performed by mounting a color coloring filter on the liquid crystal display device. Characteristic signal processing circuit.