JPH0535201A - Driving circuit for display device - Google Patents

Abstract

PURPOSE:To obtain the same effect as high-speed sampling without increasing the sampling speed of a driver by providing a video dividing means and a means which generates clock signals synchronized with the timing of divided video signals respectively. CONSTITUTION:The driving circuit is equipped with the signal dividing circuit A which divides the video signal and generates a sampling clock and a source driver B which samples the divided video signals. A digital video signal D and a clock signal CK are inputted to the signal dividing circuit A. The signal dividing circuit A generates the divided digital video signals DA, DB, and DC by subjecting the digital video signal to tripartition and three kind of clock signals CKA, CKB, and CKC corresponding to those divided video signals. In another way, the signal dividing circuit A matches the timing of the divided video signals DA, DB and DC and sends out a signal clock signal corresponding to them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a display device, and more particularly to a drive circuit for a display device in which a video signal is given digitally and the digital data of which is required to be sampled. It is preferably used. In particular, it is useful as a drive circuit of a device that requires a very high sampling speed, for example, a large-sized and high-definition liquid crystal display device.

[0002]

2. Description of the Related Art The present invention can be suitably applied to drive circuits of all display devices that require sampling of digital data. Here, a drive circuit of a TFT liquid crystal display device will be described as an example. .

When a video signal is given digitally, a circuit as shown in FIG. 23 is used as a source driver. Here, for simplification, it is assumed that the video signal data D is composed of 2 bits. That is, the video signal data D has four values of _{0 to 3} , and the signal voltage applied to each picture element is one of the four levels of V _{0 to} V ₃ . The 2-bit video signal data D is input to each of the unit circuits CELL1 to CELLn corresponding to each source line. The shift clock from the shift clock generator SHCK is also input to each of the unit circuits CELL1 to CELLn. Signal voltage output from the unit circuit CELL1~CELLn are given to the corresponding source lines O ₁ ~ O _n.

FIG. 24 shows a unit circuit CELLn for the _nth source line O _n . The circuit shown in FIG. 24 includes a first-stage D flip-flop (sampling flip-flop) MSMP and a second-stage flip-flop (hold flip-flop) provided for each bit (D ₀ , D ₁ ) of the video signal data D. ) MH, one decoder DE
C, and four external voltage sources V _{0 to} V ₃ and source line O
Analog switches ASW _{0 to} A respectively provided between _n and
It is composed of SW ₃ . Note that various kinds of digital video signal data can be sampled other than the D flip-flop.

This digital source driver operates as follows. The video signal data D ₀ and D ₁ are taken into the sampling flip-flop MSMP at the rising edge of the sampling pulse SHCK _n corresponding to the nth picture element and held there. When the sampling for one horizontal period is completed, the output pulse OE is given to the hold flip-flop MH and the sampling flip-flop MS
The video signal data D ₀ and D ₁ held in MP are taken into the hold flip-flop MH and output to the decoder DEC. The decoder DEC decodes the 2-bit video signal data D ₀ and D ₁ and outputs the value (0 to 0).
Output as conduct any one of the analog switches ASW ₀ ~ASW _3, one of the four external voltages V ₀ ~V ₃ to the source line O _n according to 3).

FIG. 25 shows an overall configuration diagram of a source driver corresponding to the case where red (R), blue (B), and green (G) signals are independently sent from a computer.

Although the output pulse OE and the gradation power supplies V _{0 to} V ₄ are omitted in FIGS. 23 and 25, they are commonly input to all the unit circuits. This also applies to the source driver diagrams described below.

[0008]

The digital driver described above is capable of sampling at a very high speed (about 25 MHz) as compared with the conventional analog driver. However, with the increase in size and definition of liquid crystal panels,
The required sampling speed has become higher and higher, and it is becoming difficult for the above driver to handle it. For example, as a driver for a display device compatible with a workstation or the like, high-speed sampling that is about twice as fast as the conventional sampling is required. LSI that constitutes a driver
It is difficult for itself to support such high-speed sampling.

The present invention has been made from this point of view, and an object of the present invention is to provide a drive circuit capable of obtaining the same effect as high-speed sampling without increasing the sampling speed of the driver. It is in.

[0010]

A drive circuit according to the present invention is a drive circuit for a display device to which a digital video signal is input, and a video output by dividing the digital video signal into a plurality of divided video signals. The signal dividing means and the clock signal generating means for sending out a plurality of clock signals synchronized with the timings of the plurality of divided video signals are provided, thereby achieving the above object.

Further, another driving circuit of the present invention is a driving circuit of a display device to which a digital video signal is input, and the video signal division for dividing the digital video signal into a plurality of divided video signals and outputting the divided video signals. And a divided video signal timing matching means for matching the timings of the plurality of divided video signals.

The other drive circuit of the present invention may further comprise a clock signal generating means for transmitting a single clock signal synchronized with the timing of the plurality of aligned divided video signals.

[0013]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows the basic construction of an embodiment of the present invention. This embodiment includes a signal dividing circuit A for dividing a video signal and generating a sampling clock, and a source driver B adapted to sample the divided video signal. The signal dividing circuit A is preferably formed on a chip different from the LSI forming the source driver B. The digital video signal D and the clock signal CK are input to the signal division circuit A. From these inputs, the signal division circuit A divides the digital video signal D into three, and outputs divided digital video signals DA, DB, and DC, and three types of clock signals CKA, CKB, and CKC corresponding to these divided digital video signals, respectively. To occur.

Clock signal CK, digital video signal D,
The timings of the divided digital video signals DA to DC and the clock signals CKA to CKC are shown in FIG.

FIG. 2 shows the configuration of the signal division circuit A. The signal division circuit A changes from the clock signal CK to the clock signal CK.
A clock generation circuit G for generating A to CKC and three flip-flops FF1, FF2 and FF3 are provided. The flip-flops FF1 to FF3 have the same number of inputs and outputs as the number of bits of the digital video signal D.
In other figures, only one input and output is shown for each flip-flop, but those flip-flops also have a number of inputs and outputs suitable for the number of bits of the input video signal. It is assumed that

Details of the clock generation circuit G are shown in FIG.
The clock generation circuit G includes three flip-flops FF4 to FF6 and a flip-flop FF connected in a ring shape.
4 is input to the flip-flop FF7, the outputs of the flip-flops FF4 and FF7 are input to the OR circuit 12, the output of the OR circuit 12 is input to the flip-flop FF8, and the output of the flip-flop FF8 is input to the flip-flop FF8. FF9 is provided. The clock signal CK is applied to the clock terminal of the flip-flop FF7.
Is input, but flip-flops FF4 to FF
An inverter 1 is provided at the clock terminals of 6, FF8 and FF9.
The clock signal CK via 1 is input. In the clock generation circuit G having such a configuration, the OR circuit 1
The output of 2 becomes the clock signal CKA, the output of the flip-flop FF8 becomes the clock signal CKB, and the output of the flip-flop FF9 becomes the clock signal CKC. The frequency of the clock signals CKA to CKC is one third of the frequency of the original clock signal CK. Clock generation circuit G
FIG. 4 shows the signal waveform of each part of.

The video signal D is flip-flops FF1 to F.
It is input to each of F3. The clock signals CKA to CKC are flip-flops FF1 to F, respectively.
It is input to the clock terminal of F3. Therefore, as shown in FIG. 5, the output of the flip-flop FF1 becomes the divided video signal DA which continuously outputs the (3N + 1) th (N is an integer of 0 or more) data of the original video signal D. Also,
The period of the divided video signal DA is three times that of the original video signal D. Similarly, the output of the flip-flop FF2 becomes a divided video signal DB that continuously outputs the (3N + 2) th data of the video signal D, and the output of the flip-flop FF3 outputs the (3N + 3) th data of the video signal D. The divided video signal DC is output continuously.

Clock signals CKA to CKC output from the signal division circuit A and divided digital video signals DA to
DC is input to the source driver B. FIG. 6 shows the configuration of the source driver B. Source driver B is 3
Number of shift clock generator SHCK1～SHCK3, and each source line O _1, O _2, corresponding unit circuits respectively ... in CELL1, CELL2, and a .... Clock signals CKA to CKC are input to the shift clock generators SHCK1 to SHCK3, respectively. (3
The divided video signal DA and the output of the shift clock generator SHCK1 are input to the (N + 1) th unit circuit CELL (3N + 1). Similarly, the divided video signal DB and the output of the shift clock generator SHCK2 are input to the (3N + 2) th unit circuit CELL (3N + 2),
The (3N + 3) th unit circuit CELL (3N + 3) has a divided video signal DC and a shift clock generator SHC.
The output of K3 is input.

When the video signal is divided into three as in this embodiment, the speeds of the divided video signal and the sampling clock signal are both reduced to one third of the original signal. Therefore, the speed of the original video signal and the clock signal can be increased up to 3 times the limit speed of the source driver B.

FIG. 7 shows the configuration of the signal dividing circuit A in the embodiment in which the video signal is divided into two. A timing chart of each clock signal and video signal in this embodiment is shown in FIG.
9 shows the configuration of the source driver B. In the case of this embodiment, the speeds of the divided video signal and the sampling clock signal are both reduced to one half of the original signal.

FIG. 10 shows a basic configuration of an embodiment applied to a configuration in which RGB signals are independently and simultaneously input. In this embodiment, the input video signal is divided into two. FIG. 11 shows the signal division circuit A of this embodiment, and FIG.
2 shows.

The basic structure of another embodiment of the present invention is shown in FIG. In this embodiment, the signal dividing circuit A outputs a single clock signal CLK, and the source driver B performs sampling based on the clock signal CLK. A timing chart of each clock signal and video signal in this embodiment is shown in FIG.

The signal division circuit A of this embodiment has the configuration shown in FIG. The signal dividing circuit A has a clock signal C.
A clock generation circuit G for generating clock signals CKA to CKC from K, and five flip-flops FF1 to F
It is provided with F3, FF11 and FF12. The configurations of the clock generation circuit G and the flip-flops FF1 to FF3 are the same as those in FIG. Flip flop FF
The outputs of 1 and FF2 are flip-flops FF1 and FF1, respectively.
1 and FF12. Clock signal CKC
Is output as a single clock signal CKC, and
It is also input to the clock terminals of the flip-flops FF11 and FF12. Flip-flops FF11 and F
The outputs of F12 are output as video signals DA and DB, respectively.

As is clear from the timing chart of FIG. 14, in the present embodiment, the timings of the divided video signals DA, DB and DC output from the signal division circuit A are matched and also matched with the timing of the clock signal CKL. There is. Therefore, according to this embodiment, only the clock signal CKL is required as the clock signal sent from the signal division circuit A to the source driver B. Therefore, the source driver B
It is possible to reduce the number of input terminals of the LSI configuring the.

The structure of the source driver B is shown in FIG.
According to this embodiment, as the source driver B, a source driver that is used in a conventional drive circuit and simultaneously samples RGB signals can be used.

The configurations of the signal dividing circuit A and the source driver B in the embodiment in which the configuration of FIG. 13 is divided into two are shown in FIGS. 17 and 18, respectively. FIG. 1 shows a timing chart of each clock signal and video signal in this embodiment.
9 shows. In the case of this embodiment, the speeds of the divided video signal and the sampling clock signal are both reduced to one half of the original signal.

Further, the basic structure of the embodiment applied to the structure in which the RGB signals of FIG. 17 are independently and simultaneously input is shown in FIG.
It shows in 0. FIG. 21 shows a signal division circuit A of this embodiment, and FIG. 22 shows a source driver B thereof.

The signal division circuit A may be realized inside a computer or the like.

[0030]

As is apparent from the above description, according to the present invention, a system that operates geologically at a speed at least twice as high as the maximum sampling speed limited by the characteristics of the LSI constituting the drive circuit. Will be possible.

Further, since the video signal dividing means (and the clock signal generating means or the timing matching means) is a small-scale circuit, there is no particular need for an LSI, and high-speed elements can be used. .

Further, basically, only one video signal dividing means (and clock signal generating means or timing matching means) need be provided for a plurality of source drivers.
Therefore, even if those means are realized by an expensive high-speed element, the effect on the overall cost is not so large.

As described above, according to the present invention, high-speed sampling, which was impossible by the conventional method, can be made possible as a system, so that the effect is extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a signal division circuit according to a first embodiment.

FIG. 3 is a circuit diagram of a shift clock generation circuit according to a first embodiment.

FIG. 4 is a timing chart of the shift clock generation circuit of FIG.

FIG. 5 is a timing chart of the first embodiment.

FIG. 6 is a diagram showing a source driver of the first embodiment.

FIG. 7 is a diagram showing a signal division circuit according to a second embodiment.

FIG. 8 is a timing chart of the second embodiment.

FIG. 9 is a diagram showing a source driver according to a second embodiment.

FIG. 10 is a block diagram showing a basic configuration of a third embodiment.

FIG. 11 is a diagram showing a signal division circuit according to a third embodiment.

FIG. 12 is a diagram showing a source driver according to a third embodiment.

FIG. 13 is a block diagram showing a basic configuration of a fourth embodiment.

FIG. 14 is a timing chart of the fourth embodiment.

FIG. 15 is a diagram showing a signal dividing circuit according to a fourth embodiment.

FIG. 16 is a diagram showing a source driver according to a fourth embodiment.

FIG. 17 is a diagram showing a signal division circuit according to a fifth embodiment.

FIG. 18 is a diagram showing a source driver according to a fifth embodiment.

FIG. 19 is a timing chart of the fifth embodiment.

FIG. 20 is a block diagram showing the basic structure of a sixth embodiment.

FIG. 21 is a diagram showing a signal division circuit according to a sixth embodiment.

FIG. 22 is a diagram showing a source driver according to a sixth embodiment.

FIG. 23 is a diagram showing a conventional source driver.

FIG. 24 is a diagram showing a portion corresponding to each source line in the source driver of FIG. 23.

FIG. 25 is a diagram showing another conventional source driver.

[Explanation of symbols]

A signal division circuit B source driver D digital video signal DA-DC split video signal CKA to CKC Multiple clock signals CKL Single clock signal

Claims (3)

[Claims] 1. A drive circuit for a display device to which a digital video signal is input, the video signal dividing means dividing the digital video signal into a plurality of divided video signals and outputting the divided video signals, and the plurality of divided video signals. Drive circuit for a display device, comprising a clock signal generating means for transmitting a plurality of clock signals synchronized with the respective timings. 2. A drive circuit of a display device to which a digital video signal is input, the video signal dividing means for dividing the digital video signal into a plurality of divided video signals and outputting the divided video signals, and the plurality of divided video signals. Drive circuit of a display device provided with divided video signal timing matching means for matching the timings of the above. 3. The drive circuit according to claim 2, further comprising clock signal generating means for transmitting a single clock signal synchronized with the timing of the plurality of aligned divided video signals.