KR100218534B1 - Timing control device of liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing control apparatus of a liquid crystal display device having odd data driving integrated circuits and even data driving integrated circuits arranged in a row on either the top or the bottom of a liquid crystal panel.

Converts the data of the color signal so as to appear in odd data and even data alternately by the number of channels of a driving circuit, and provides the odd data and even data to the odd data driving integrated circuits and the even data driving integrated circuits, By driving the liquid crystal panel simultaneously by one of the data driving integrated circuits and one of the even data driving integrated circuits, the driving frequency can be reduced as compared with the conventional art, and by providing color signal data in a format similar to a single bank, Data driving integrated circuits may be disposed above or below, thereby enabling compact design of the data driving integrated circuit.

Description

Timing Control Device of Liquid Crystal Display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing control apparatus for a liquid crystal display, and more particularly, to a timing control apparatus for providing a color signal to a data driving integrated circuit having an improved single bank structure.

In general, a liquid crystal display module (LCD module) is composed of a plurality of gate lines and source lines, the liquid crystal panel (LCD panel) having a switching transistor and a pixel (pixel) formed at the intersection of each gate line and source line, A gate driver sequentially applying a turn-on voltage to each gate line of the liquid crystal panel, a data driver (also referred to as a 'source driver') of applying a gray voltage corresponding to a color signal at line intervals to a source line of the liquid crystal panel, and a liquid crystal display A timing controller for outputting a control signal and a RGB signal for driving the gate driver and the data driver by inputting vertical and horizontal synchronization signals and color signals from a graphic controller external to a device module, gate turn on and turn off. A voltage generator which generates a voltage and a common electrode voltage and outputs the voltage to the gate driver; The gray voltage generator generates a gray voltage provided to the other driver.

In the liquid crystal display module, the data driver includes a plurality of source driver ICs, and the gate driver includes a plurality of gate driver ICs. Each of the data driving integrated circuits includes a plurality of shift registers for storing input color signals by one bit for each source line. For example, if one data driver integrated circuit covers 50 source lines in an input panel, each data driver integrated circuit includes 50 shift registers connected in series with each other.

As is known, there are two methods for arranging such data driving integrated circuits, a dual bank and a single bank. The dual bank has odd-numbered (or even) source lines connected to upper data driver integrated circuits and even-numbered (or odd) source lines are connected to upper and lower data drive integrated circuits with data driver integrated circuits positioned above and below the liquid crystal panel. The data driving integrated circuits are arranged to be connected to a circuit, and the single bank is to arrange the data driving integrated circuits in a row on either side of the liquid crystal panel.

1 shows a conventional liquid crystal display having a dual bank structure.

As shown in Fig. 1, the PC-SET 11 is a graphic controller and generates control signals and data signals. Here, the control signal is a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock signal MCLK. The data signals are even data DATA_EVEN and odd data DATA_ODD.

The interface device 12 controls the drive circuits 13, 14, and 15 in accordance with the control signals and data signals transmitted from the PC-SET 11. The interface device 12 transmits the even data DATA_EVEN to the UP SOURCE IC 14, and the odd data DATA_ODD to the DOWN SOURCE IC 15. . The liquid crystal panel 16 is driven by the gate driving circuit 13 and the upper and lower data driving circuits 14 and 15.

In the dual bank liquid crystal display, the upper data driving integrated circuits are connected to each other so that color data can be shifted in series, and the lower data driving integrated circuits are the same. For example, in a dual bank data driver having 800 source lines of the liquid crystal panel and eight data driver integrated circuits covering 100 source lines, four data driver integrated circuits are respectively disposed on the upper and lower portions of the liquid crystal panel. The upper four data driving integrated circuits are connected to each other, and the final shift register output terminal of the immediately preceding integrated circuit is connected to the first shift register input terminal of the current integrated circuit, and the lower four data driving integrated circuits are the same as above. Connected to the structure.

Assuming a single bank data driver having the same source line, eight data driver integrated circuits are arranged in a row above or below the liquid crystal panel, and eight data driver integrated circuits are arranged in front of the integrated circuits arranged in a row. Is configured to be connected to the first shift register input of the current integrated circuit.

At this time, the structure and function of the timing controller are also different in the dual bank and the single bank. For example, if a color signal having a single bank data array is input from the graphic controller, in the dual bank, the timing controller may use an odd part and an even part for each color signal RGB signal input from the graphic controller. After separating and arranging, the data driver ICs are provided to the upper data driver integrated circuits and the lower data driver integrated circuits of the data driver. In contrast, in a single bank, the timing controller does not need to go through the separation process.

Meanwhile, in the dual bank data driver, odd-numbered and even-numbered color signals provided from the timing controller are simultaneously input to the upper data driver integrated circuits and the lower data driver integrated circuits.

Therefore, in the dual bank data driver, the upper data driver integrated circuits and the lower data driver integrated circuits drive all the source lines of the liquid crystal panel at the same time, whereas in the single bank data driver, the data driver integrated circuits disposed on either the top and the bottom of the liquid crystal are liquid crystal. Drive all source lines of the panel.

If the sustain periods of the data pulses applied to the source line are the same in both the dual bank and the single bank, the single bank data driver drives twice the time of driving the source line. Therefore, in order to make the driving time the same, the operating frequency of the single bank data driver must be twice the operating frequency of the dual bank data driver.

In general, when the operating frequency is large, electromagnetic interference (EMI) is also active, so the single bank data driver is less advantageous than the dual bank data driver in view of the operating frequency.

However, since the dual bank data driver is provided with data driver integrated circuits on both the top and the bottom of the liquid crystal panel, the area occupied by the liquid crystal display module is larger than that of the single bank data driver. Thus, the single bank data driver is advantageous in that it makes the compact design easier than the dual bank data driver.

Recently, as notebook computers have been widely used, single bank data drivers for enabling compact designs have been very popular. For this reason, the development of the liquid crystal display driver which has a low operating frequency and enables compact design is calculated | required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing control apparatus for a liquid crystal display device capable of reducing not only an area occupied by a driving circuit in the liquid crystal display but also an operating frequency.

1 is a configuration diagram of a liquid crystal display device having a conventional dual bank arrangement structure;

2 is a configuration diagram of a timing control device of a liquid crystal display device according to a first embodiment of the present invention;

3 is a configuration diagram of a data signal processor shown in FIG. 2;

4 is a configuration diagram of the shift unit shown in FIG. 3;

5 is a configuration diagram of the latch unit shown in FIG.

FIG. 6 is a configuration diagram of the first and second synthesis parts shown in FIG. 3;

7 is a waveform diagram of signals of respective parts of the timing control device of the liquid crystal display according to the first embodiment of the present invention;

Fig. 8A is a waveform diagram showing the timing relationship between the vertical and horizontal synchronization signals and the data enable signal.

FIG. 8B is a waveform diagram showing a relationship between the signal shown in FIG. 8A and a color signal having a dual bank arrangement structure;

FIG. 9 is a waveform diagram showing an output signal of the latch unit shown in FIG. 5;

FIG. 10 is a waveform diagram illustrating a process of generating a color signal having an improved single bank arrangement structure according to the present invention by sequential signals in the first and second synthesizers of FIG. 6;

Fig. 11 is a configuration diagram of a liquid crystal display device illustrating that a color signal having an improved single bank arrangement structure according to the present invention is input to a data driving circuit.

12 is a waveform diagram showing an arrangement state of color signals having an improved single bank arrangement structure according to the present invention;

13 is a configuration diagram of a timing control device of a liquid crystal display device according to a second embodiment of the present invention;

14 is a configuration diagram of the data signal processor of FIG. 13;

FIG. 15 is a configuration diagram of the shift unit shown in FIG. 14;

Fig. 16 is a configuration diagram of the latch portion of Fig. 14,

FIG. 17 is a configuration diagram of the first and second synthesis portions of FIG. 14;

18 is a waveform diagram of signals of respective parts of the timing control device of the liquid crystal display according to the second embodiment of the present invention;

19 is a block diagram of a data signal processing unit according to a third embodiment of the present invention;

20 is a configuration diagram of the latch portion of FIG. 19;

FIG. 21 is a configuration diagram of the first and second synthesis portions of FIG. 19;

Fig. 22 is a waveform diagram of signals of each part used in the data signal processing part of the liquid crystal display according to the third embodiment of the present invention.

23 is a configuration diagram of a timing control device of a liquid crystal display device according to a fourth embodiment of the present invention;

24 is a configuration diagram of the data signal processor shown in FIG. 23;

FIG. 25 is a configuration diagram of a circuit for converting a color signal having a single bank array structure into a dual bank array structure in the data divider shown in FIG.

FIG. 26 is a configuration diagram of the latch pulse generator shown in FIG. 23;

FIG. 27 is a circuit diagram of the latch unit shown in FIG. 24;

28 and 29 are circuit diagrams of the first and second combining units shown in FIG. 24;

Fig. 30 is a waveform showing the relationship between the vertical and horizontal synchronization signals, the data enable signal, the single bank array color signal, and the improved single bank array color signal used in the timing control apparatus of the liquid crystal display according to the fourth embodiment of the present invention. Degree,

31 is a waveform diagram illustrating a process of obtaining an improved single bank array color signal according to the present invention from a single bank array color signal;

32 is a waveform diagram illustrating a control process performed by the data arranging unit of FIG.

A liquid crystal display device to which a timing control device according to the present invention is applied includes a liquid crystal panel and a data driver having a plurality of data driving integrated circuits arranged in one line above or below the liquid crystal panel. The timing controller provides a color signal and a control signal to the data driver.

In the data driver, all odd-numbered data driving integrated circuits are connected to sequentially shift data of a color signal, and all even data driving integrated circuits are connected to sequentially shift data of a color signal. Each of the data driving integrated circuits includes a memory device such as a shift register, and the number of data driving integrated circuits for driving one horizontal line on the liquid crystal panel is included in each of the data driving integrated circuits. It depends on the number of shift registers. For example, if a liquid crystal panel has 1000 data lines per horizontal line, and each data driver integrated circuit has 100 memory elements therein, each data driver integrated circuit may drive 100 data lines. . At this time, the timing controller separates the data of 1000 color signals sequentially input into the odd-numbered and even-numbered data by 100 in order to drive one horizontal line on the liquid crystal panel, and separates each of the odd-numbered data and the even-numbered data. Data is added to each other, the summed odd-numbered data is input to the first of the five odd-numbered data driver integrated circuits, and the summed even-numbered data is inputted to the first of the five even-numbered data driver integrated circuits. Type in In the present invention, such a data array is called an improved single bank array. As already mentioned, the odd-numbered data driver integrated circuits may transfer data to each other sequentially, and the even-numbered data driver integrated circuits may transfer data to each other sequentially, so that each of the data driver integrated circuits may have 1000 The data of the color signal is completely filled. Therefore, one horizontal line on the liquid crystal panel may be driven by the data filled in the data driving integrated circuits.

From the above description, if the same time as the single bank method is given to drive one horizontal line, the even-numbered data driver integrated circuits and the odd-numbered data driver integrated circuits are driven simultaneously, so that driving for one data line is performed. In time it can be seen that the scheme according to the invention is twice that of the single bank scheme. Therefore, not only the pixel driving time on the liquid crystal panel is increased as compared with the single bank method, but also the frequency of the main clock can be reduced by half of the single bank method. In addition, since the data driving integrated circuits are arranged in a line above or below the liquid crystal panel similarly to a single bank, the liquid crystal display according to the present invention enables the compact design of the data driving unit.

A timing control apparatus according to the first aspect of the present invention converts a data signal having a dual bank arrangement structure into a data signal having an improved single bank arrangement structure.

In order to achieve the first feature, the timing control device according to the present invention,

A control signal processor for inputting vertical and horizontal synchronization signals and a main clock signal to generate control signals for the gate driver and the data driver of the liquid crystal display;

A sequential signal generator which receives a main clock signal and a data enable signal and generates a latch control signal and a sequential control signal;

A plurality of shift units for sequentially shifting and simultaneously outputting odd data and even data of a dual bank color signal according to the main clock signal;

A plurality of latch units for simultaneously outputting n odd data and n even data output from the shift unit according to the latch control signal;

A plurality of products that alternately multiply n / 2 odd data and n / 2 even data output from the latch unit with the sequential control signal, and generate an odd component of a color signal by ORing the result of each AND operation; 1 synthesis part; And

Alternately logically multiply the remaining n / 2 odd data and the remaining n / 2 even data output from the latch unit with the sequential control signal, and generate an even component of the color signal by ORing the result of each AND operation It includes a plurality of second synthesis portion.

In the timing control apparatus according to the first aspect of the present invention, the odd data and even data of the dual bank color signal are alternately multiplied by the sequential control signal by the first synthesis section and the second synthesis section, thereby causing the dual bank color signal. Is rearranged to obtain an improved single bank color signal according to this invention.

The timing control device according to the second aspect of the present invention converts a data signal having a single bank array structure into a data signal having an improved single bank array structure.

In order to achieve the second aspect, the timing control apparatus according to the present invention,

A control signal processor which receives the vertical and horizontal synchronization signals and the main clock signal and generates control signals for the gate driver and the data driver of the liquid crystal display, a bi-division clock signal obtained by dividing the main clock signal into two, and a latch clock signal;

A sequential signal generator for generating a sequential control signal from a data enable signal and the divided clock signal;

A plurality of shift units which receive a single bank color signal and sequentially shift and simultaneously output data of the color signal according to the main clock signal;

A plurality of latch units for separating the data of the color signal output from the shift unit by n and outputting the separated 2n data simultaneously according to the latch clock signal;

A first synthesizer for logically multiplying n pieces of data output from the latch unit with the sequential control signal, and generating an odd component of a color signal by logically adding the result of each logical product operation; And

And a second synthesizer for logically multiplying the remaining n data output from the latch unit with the sequential control signal, and generating an even component of the color signal by logically adding the result of each logical product operation.

In the timing control apparatus according to the second aspect of the present invention, the first synthesizer and the second synthesizer separate n data of a single bank color signal by n, and the separated data are logically multiplied by a sequential control signal. An improved single bank color signal is obtained. In particular, the sequential control signal is made from a two-division clock signal, and the data section of the improved single bank color signal is twice the data section of the single bank color signal.

The timing controller according to the third aspect of the present invention converts a single bank color signal into an improved single bank color signal without using a shift unit.

In order to achieve the third aspect, the timing control apparatus according to the present invention,

A control signal processor configured to receive vertical and horizontal synchronization signals and a main clock signal, and generate a control signal for a gate driver and a data driver of the liquid crystal display, and a two-division clock signal divided into two main clock signals;

A latch control signal and a two-division clock having a high level section equal to one clock pulse section of the main clock signal for every n clock pulses of the main clock signal by receiving a main clock signal, a divided clock signal, and a data enable signal. A sequential signal generator for generating a sequential control signal having a high level interval equal to one clock pulse interval of the two divided clock signals for every n clock pulses of the signal;

Receives a single bank color signal and the latch control signal, sequentially outputs data of the single bank color signal in the high section of the latch control signal, and maintains the output state until the next high section of the latch control signal is input. A plurality of latch portions to allow;

A plurality of first synthesizing units which logically multiply data of the color signals output from the latch unit with the sequential control signals within the sustain period, and generate odd components of the color signals by ORing the result of each AND operation; And

And a plurality of second synthesis units which logically multiply the data of the color signals output from the latch unit within the sustain period with the sequential control signals whose order is adjusted, and generate an even component of the color signal by logically adding the result of each logical product operation. do.

In the timing control apparatus according to the third aspect of the present invention, a color signal obtained by extending the data section in the first and second synthesizing sections is obtained while the output state of the color signal data is maintained in the latch section. This is achieved by adjusting the order of the sequential control signal when the logical product operation between the sequential control signal and the latch output data is performed in the second synthesizer, and the expansion of the data section is a sequential control signal made from a two-division clock signal. Is achieved by. Thus, the timing control apparatus according to the third aspect can convert the single bank color signal into the improved color signal according to the present invention without the shift portion.

The timing control device according to the fourth aspect of the present invention converts a single bank or dual bank color signal into a data signal having an improved single bank arrangement structure according to an external selection signal, and reduces the signal line of the control signal to be used as a flip-flop. And reduce the number of gate elements.

The timing control apparatus of the liquid crystal display device which concerns on the 4th characteristic of this invention,

A control signal processor for inputting vertical and horizontal synchronization signals and a main clock signal to generate a signal for controlling the gate driver and the data driver of the liquid crystal display, and generating a clock signal obtained by dividing the main clock signal into two;

When the color signal input from the external selection signal is a single bank, the single bank color signal is converted into a dual bank color signal according to the two-division clock signal. When the color signal input from the external selection signal is a dual bank, the color signal without conversion is performed. A data divider for outputting a;

Receiving a data enable signal and a divided clock signal, and generating a first sequential control signal and a second sequential control signal from the data enable signal and the divided clock signal, and generating at least two or more of the first sequential control signals A plurality of latch pulse generators for generating a latch control signal by performing an OR operation, and generating an addition control signal by performing an OR operation on at least two of the second sequential control signals; And

For each color signal, odd data and even data of the dual bank color signal outputted from the data divider are latched in accordance with the latch control signal, and the odd component of the color signal is generated by a logical operation between the latched data and the summing control signal. It includes a plurality of data arrays for generating even components.

In this case, the latch control signal and the sum control signal are previously determined such that data of a color signal alternates with the number of channels of the data driving integrated circuit in the odd component and the even component, and the odd component is an odd data driving integrated circuit of the data driver. The even data is input to the even data driver integrated circuits of the data driver.

Therefore, even though the data driver has a structure in which data driver integrated circuits are arranged in a line similar to the single bank method, the data lines on the liquid crystal panel may be driven in the dual mode by the even data and the odd data.

In the timing control apparatus according to the fourth aspect of the present invention described above, since the number of signal lines of the latch control signal and the sequential control signal is smaller than the number of channels, the number of flip-flop elements and gate elements used in the timing control apparatus is reduced.

The above features, objects, and effects will be more clearly understood through the following description of the examples.

[First Embodiment]

First, the timing control apparatus of the liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS.

As shown in Fig. 2, the timing control apparatus of the liquid crystal display according to the second embodiment of the present invention includes a control signal processor 21 and a data signal processor 22.

The control signal processor 21 receives the vertical and horizontal synchronization signals HSYNC and VSYNC, the data enable signal DE, and the main clock signal MCLK from an external device such as a graphic controller. And control signals required by the data driver (not shown). That is, the control signal processor 21 uses the input signal to start a horizontal start signal (STHO, STHE), start vertical signal (STV), gate clock signal (CPV), and line inversion. The signal RVS and the load signal TP are generated. The signals generated by the control signal processor 21 are provided to a gate driver and a data driver of the liquid crystal display.

The data signal processor 22 receives a color signal and a main clock signal MCLK having a dual bank array structure from an external device such as a graphic controller. Referring to FIG. 8B, in the color signal having the dual bank arrangement structure, two signals divided into odd and even portions of data are provided for one color signal. For example, for the R (red) signal, as shown in Fig. 8B, the RA (0: 5) and RB (0: 5) signals are provided. Here, (0: 5) means that the RA signal is composed of 6 bits, which is for multi-gradation display of the color signal.

The data signal processing section 22 rearranges the data of the color signals having the dual bank arrangement structure, and thus the color signal having the improved single bank arrangement structure according to the present invention (hereinafter referred to as the improved single bank color signal) [RO ( 0: 5), RE (0: 5), GO (0: 5), GE (0: 5), BO (0: 5), BE (0: 5)]. The improved single bank color signal has odd and even components for one color. The odd component RGB_ODD of the improved single bank color signal is input to an odd-numbered data driver IC in the liquid crystal display shown in FIG. 11, and the even component RGB_EVEN is input to an even-numbered data driver integrated circuit. Is entered. As shown in Fig. 11, in the liquid crystal display device using the improved single bank color signal, since the data driving integrated circuit can be disposed on either the upper side or the lower side, this enables compact design of the liquid crystal display apparatus. FIG. 12 shows an arrangement of data input to each data driving integrated circuit of FIG. 11, in which n pieces of data are sequentially input to each data driving integrated circuit. Where n is the number of channels in the data driver integrated circuit. In general, data driving integrated circuits are sequentially inputted with data of color signals, and the improved single bank color signals according to the present invention must be separated into odd and even components. Data array is required. For example, the odd component RGB_ODD of the improved single bank color signal according to the present invention is formed by aggregating the odd numbered pieces of the n separated data. In Fig. 12, odd components (RGB_ODD) are D1 to Dn, D2n + 1 to D3n, D4n + 1 to D5n. The even components (RGB_EVEN) are Dn + 1 to D2n, D3n + 1 to D4n, and D5n + 1 to D6n. Has an array of The following describes how the arrangement of the improved single bank color signal is made from the dual bank color signal.

3 illustrates the data signal processor of FIG. 2 in detail.

Referring to FIG. 3, the data signal processor 22 receives a main clock signal MCLK and a data enable signal DE and generates a sequential signal generator 23 and a plurality of sequential control signals L1 to Ln. Data processing cells 24-26. Each data processing cell receives an odd data of one bit line of a dual bank color signal, an even data of one bit line, a sequential control signal and a main clock signal MCLK output from the sequential signal generator 23, and is improved. One bit odd component and one bit even component of the color signal are generated. As described above, in the first embodiment of the present invention, since 6 bits are allocated to each color of the dual bank color signal, a total of 18 colors are required to process three colors of R (red), G (green), and B (blue). Data processing cells are required. 3, only one 24 of 18 data processing cells is shown in detail, and the other has the same internal configuration as the data processing cell shown in detail. The data processing cell 24 receives RA (0) and RB (0) of the dual bank color signals to generate odd component RO (0) and even component RE (0) of the improved single bank color signal.

More specifically, the data processing cell 24 is composed of a shift unit 241, a latch unit 242, and first and second combining units 243 and 244. The shift unit 241 receives the RA (0), the RB (0), and the main clock signal MCLK of the 1-bit line and outputs them while sequentially shifting the dual bank color signals RA (0) and RB (0). The latch unit 242 simultaneously outputs the output of the shift unit 241 in units of n of each color signal by the latch clock signal LATCK. Here, although one of the sequential control signals is used as the latch clock signal LATCK, the technical scope of the present invention is not limited thereto. The first and second combiners 243 and 244 receive the output of the latch unit 242 and the sequential control signal output from the sequential signal generator 23 and an odd number part RO (0) of the improved single bank color signal. And even component RE (0) are generated respectively.

4 shows the shift section 241 in detail.

As shown in Fig. 4, the shift unit 241 is composed of 2n D-flip flops, n D-flip flops are connected in series with each other, and the remaining n D-flip flops are also connected in series with each other. The main clock signal MCLK is input to each clock terminal of 2n D flip-flops in common, and RA (0) is input to the data terminal of the first flip-flop among the n D-flip flops, and RB (0) Is input to the data terminal of the first flip-flop of the other n D flip-flops. The output terminals of the 2n D flip-flops are connected to the latch unit 242. Each D-flip-flop transmits a signal of a data terminal to an output terminal in response to a clock pulse of the main clock signal MCLK. Therefore, the data of the dual bank color signal RA (0) is provided to the latch unit 242 while being sequentially shifted, and provided to the latch unit 242 while the data of the RB (0) is sequentially shifted by another n flip-flops. do. The shift unit 241 continuously performs the operation as described above based on the main clock signal MCLK.

8A shows the timing relationship between the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, and the data enable signal DE. Referring to FIG. 8A, there are a plurality of horizontal synchronizing signal HSYNC pulses during one pulse of the vertical synchronizing signal VSYNC. The frequency of the data enable signal DE is equal to the horizontal sync signal, and one pulse duration is less than that of the horizontal sync signal. In the high pulse period of the data enable signal DE, data is displayed on the liquid crystal panel by the data driving integrated circuit. 8B shows the signals shown in FIG. 8A and the dual bank color signals RA (0: 5), RB (0: 5), GA (0: 5), GB (0: 5), BA (0: 5), The timing relationship with BB (0: 5) is shown. The shift unit 241 sequentially shifts the data of RA (0) and RB (0) shown in FIG. 8B.

5 shows the latch portion 242 in detail.

As shown in Fig. 5, the latch portion 242 is composed of 2n D-flip flops. The n D flip-flops are for latching the n color signals RA (0) provided from the shift unit 241, and the other n D-flip flops are for latching the n color signals RB (0). The latch clock signal LATCK is commonly input to 2n D-flip flops. In addition, the output terminals of the 2n D-flip flops of FIG. 4 and the input terminals of the 2n D-flip flops of FIG. 5 are connected to each other with the same numbers. The n D-flip flops have n output terminals A1 to An, and the other n D-flip flops have n output terminals B1 to Bn. Each D-flip-flop of the latch unit 242 simultaneously transfers data of the input terminal to the corresponding output terminal in response to the pulse of the latch clock signal LATCK. Referring to FIG. 7, it can be seen that the first sequential control signal L1 is used as the latch clock signal LATCK in the first embodiment of the present invention. Accordingly, n data D1 to D2n-1 of the RA (0) signal are held at the output terminals A1 to An of the n flip-flops by the first clock pulse of the sequential control signal L1. In (B1 to Bn), n pieces of data (D2 to D2n) of the RB (0) signal are held. The latch clock signal LATCK has one clock pulse for every n clocks of the main clock signal, and a waveform of the latch clock signal LATCK is shown in FIG. 9. The high level section of the latch clock signal LATCK is the same as one clock pulse section of the main clock signal MCLK, as shown in FIG. As shown in Fig. 9, at the output terminals A1 to An of the latch unit 242, n odd data of the dual bank color signal RA (0) until the next clock pulse of the latch clock signal LATCK is input. Is maintained, and n even data of the dual bank color signal RB (0) is similarly retained at the output terminals B1 to Bn.

The output of the latch portion 242 is provided to the first and second composite portions 243 and 244, and the first and second composite portions 243 and 244 are shown in detail in FIG.

Each combining section 243 and 244 is composed of n logical multiplication elements and one logical sum element. As shown in FIG. 6, in the first synthesis section 243, each logical multiplication device has two input terminals, and one input terminal of each logical multiplication device has one of n sequential control signals L1 to Ln. One of the output terminals A1 to An / 2 and one of the output terminals B1 to Bn / 2 of the latch unit 242 are alternately input to the other input terminal of each logical multiplication element. That is, the sequential control signal L1 and the signal of the output terminal A1 of the latch unit 242 are input to the first logical multiplication device of the first synthesis unit 243, and the sequential control signal L2 is input to the second logical multiplication device. And an output terminal B1 signal of the latch unit 242 are input, and a sequential control signal L3 and an output terminal A2 signal are input to the third logical product. In the same manner as described above, the sequential control signal Ln-1 and the output terminal An / 2 signal are input to the n−1 th logical multiplication device, and the sequential control signal Ln and the output stage Bn / are input to the n th logical multiplication device. 2) A signal is input. Similarly, a sequential control signal L1 and an output terminal (An / 2 + 1) signal of the latch unit 242 are input to the first logical multiplication device of the second synthesis unit 244, and to the second logical multiplication device. The sequential control signal L2 and the output terminal Bn / 2 + 1 signals are input, and the sequential control signal Ln-1 and the output terminal An signal are input to the n-1 th logical product, and the n th logical product. The control signal Ln and the output terminal Bn are sequentially input to the element. The OR elements of each synthesis section OR the outputs of the n AND elements to produce odd component RO (0) and even component RE (0) of the improved single bank color signal. The logical combinations of the outputs of the latch sections 242 with the control signals L1 to Ln in turn in the synthesis sections 243 and 244 are for changing the data arrangement of the dual bank color signals. In this way, odd data and even data of the dual bank color signal are sequentially mixed with each other, and are separated into n components of the color signal into odd component RO (0) and even component RE (0) of the first synthesizer. Referring to FIGS. 7 and 9, the single bank color signal is improved by rearranging the output of the latch unit 242 as described above by n sequential control signals L1 to Ln having sequential high level pulse intervals. It can be seen that the odd components RO (0) and even components RE (0) of are obtained. Referring to Fig. 9, the data of the odd component RO (0) is D1 to Dn, D2n + 1 to D3n,... As described above, the sequential n data are arranged alternately, and the data of even component RE (0) is alternately arranged as sequential n data such as Dn + 1 to D2n and D3n + 1 to D4n. Fig. 10 shows that the odd component RO (0) and even component RE (0) are generated by the sequential control signals L1 to Ln. The first and second synthesis units 243 and 244 repeat the above operation whenever 2n color signals are input from the latch unit 242.

The first embodiment of this invention described above converts a dual bank color signal into an improved single bank color signal. In the improved single bank color signal, odd components and even components are separated, and each of them is inputted to an odd data driver integrated circuit and an even data driver integrated circuit, thereby simultaneously providing liquid crystals by the odd data driver integrated circuit and the even data driver integrated circuit. The panel can be driven. Therefore, the panel driving frequency can be reduced to 1/2 of the panel driving frequency of the liquid crystal display having the single bank structure.

Further, the improved single bank color signal enables the data driving integrated circuit to be arranged in one line on either side of the liquid crystal panel, thereby achieving a compact design of the data driving integrated circuit in the liquid crystal display device.

Second Embodiment

Next, a timing control apparatus of the liquid crystal display according to the second embodiment of the present invention will be described with reference to FIGS. 13 to 18.

The timing control apparatus of the liquid crystal display according to the second embodiment of the present invention converts the single bank color signal into the improved single bank color signal according to the present invention. The data pulse duration of the improved single bank color signal is twice the data pulse duration of the single bank color signal. In addition, it is required that n pieces of data of a single bank color signal are separated into odd and even components. Based on this point of view, a timing control device according to a second embodiment of this invention is described below.

13 is a configuration diagram of a timing control device of the liquid crystal display according to the second embodiment of the present invention.

As shown in Fig. 13, the timing control apparatus of the liquid crystal display according to the second embodiment of the present invention is composed of a control signal processor 31 and a data signal processor 32.

The control signal processor 31 receives the vertical and horizontal sync signals HSYNC and VSYNC, the data enable signal DE, and the main clock signal MCLK from an external device such as a graphic controller. And control signals required by the data driver (not shown). That is, the control signal processing unit 31 uses the input signal to start a horizontal start signal (STHO, STHE), a vertical start signal (STV), a gate clock signal (CPV), and line inversion. A signal RVS, a gate-on enable signal OE, a load signal TP, a latch clock signal LATCK, and a bi-division clock signal 2CLK are generated. The signals generated by the control signal processor 31 are provided to the gate driver, the data driver, and the data signal processor 32 of the liquid crystal display.

The data signal processor 32 receives the color signals R (0: 5), G (0: 5), B (0: 5) and the main clock signal MCLK having a single bank arrangement from an external device such as a graphic controller. The controller receives the two-division clock signal 2CLK and the latch clock signal LATCK from the control signal processor 31. The data signal processor 32 rearranges the data of the single bank color signal to improve the single bank color signals RO (0: 5), RE (0: 5), GO (0: 5), and GE (0: 5). , BO (0: 5), BE (0: 5)

14 shows the data signal processor 32 of FIG. 13 in detail.

As shown in FIG. 14, the data signal processor 32 receives a two-division clock signal 2CLK and a data enable signal DE to sequentially generate the control signals L1 to Ln. ) And a plurality of data processing cells 34 to 36. Each data processing cell receives the data of the 1-bit line of the single bank color signal, the sequential control signals L1 to Ln, the main clock signal CLK, and the latch clock signal LATCK output from the sequential signal generator 33. Generate odd and even components of the improved single bank color signal. In the second embodiment of the present invention, since 6 bits are allocated to each color of the single bank color signal, a total of 18 data processing cells are required to process three colors of R (red), G (green), and B (blue). Do. 14, only one of the 18 data processing cells 34 is shown in detail, and the other has the same internal configuration as the data processing cells shown in detail. The data processing cell 34 receives R (0) of the single bank color signal and generates odd component RO (0) and even component RE (0) of the improved single bank color signal.

More specifically, the data processing cell 34 is composed of a shift unit 341, a latch unit 342, and first and second synthesis units 343 and 344. The shift unit 341 receives the color signal R (0) and the main clock signal CLK of one bit line and outputs the color signal R (0) while sequentially shifting the color signal R (0). The shift unit 341 has 2n output lines. The latch unit 342 classifies the outputs of the shift unit 341 by n and outputs the 2n data at the same time by the latch clock signal LATCK. The first and second synthesis units 343 and 344 respectively receive n pieces of data from the latch unit 342, and receive the sequential control signals L1 to Ln respectively output from the sequential signal generator 23. Generate odd component RO (0) and even component RE (0) of the improved single bank color signal, respectively. Here, the latch clock signal LATCK has one high level section for every 2n clock pulses of the main clock signal MCLK as shown in FIG. 18, and the high level section has one clock pulse section of the main clock signal. Is the same as In addition, each of the sequential control signals shown in FIG. 18 has one high level section for every 2n clock pulses of the main clock signal MCLK, and the high level section is the same as two clock pulse sections of the main clock signal. .

15 shows the shift portion 341 of FIG. 14 in detail.

As shown in Fig. 15, the shift section 34 is composed of 2n D-flip flops connected in series with each other. The main clock signal CLK is input to the clock terminal of each of the D-flip flops, and the data of the single bank color signal R (0) is input to the data terminal of the first D-flip flop. Each D flip-flop transmits a signal of a data terminal to an output terminal in response to a clock pulse of the main clock signal CLK. Therefore, the data of the color signal R (0) is sequentially shifted by the main clock signal CLK and output to the latch unit 342. The output of each D-flip-flop constitutes 2n shift units 341 output stages 1 to 2n.

16 shows the latch portion 342 in more detail.

As shown in FIG. 16, the latch unit 342 is composed of 2n D-flip flops that receive the latch clock signal LATCK in common. Each of the upper n D-flip flops receives data from the output stages 1 to n of the shift unit 341 in turn, and each of the lower n D-flip flops is output from the output terminals n + 1 to the shift unit 341. 2n) Enter data in order. Each output terminal of the upper n D-flip flops constitutes an output terminal A1 to An of the latch unit 342, and each output terminal of the lower n D-flip flops is an output terminal B1 to N of the latch unit 342. Constitute Bn). Each of the 2n D-flip flops transmits data from the input terminal to the output terminal whenever the clock pulse of the latch clock signal LATCK is input. In addition, at the output terminal of each D-flip-flop, the data of the output terminal is maintained whenever the next clock pulse of the latch clock signal is input. As described above, in the latch clock signal LATCK, there is one high level section for every 2n clock pulses of the main clock signal MCLK, so that the output terminals A1 to An and B1 to Bn of the latch unit 342 are present. ) Data is held for 2n clock pulse intervals of the main clock signal MCLK. The first and second synthesis units 343 and 344 perform data rearrangement while the output data of the latch unit 342 is maintained.

Fig. 17 shows the first and second composite portions 343 and 344 in detail.

As shown in FIG. 17, the first synthesizing unit 343 includes n logical multiplication devices and logical multiplication devices receiving the outputs of the logical multiplication devices. Similarly, the second synthesis unit 344 is composed of n logical multiplication elements and logical sum elements receiving the outputs of the logical multiplication elements. Each logical multiplication device of the first synthesis unit 343 and the second synthesis unit 344 has two input terminals. Data of the output terminals A1 to An of the latch unit 342 are sequentially input to one input terminal of each logical multiplication element of the first synthesis unit 343, and the sequential control signals L1 to Ln are sequentially input to the first control unit. It is input in turn to the other input terminal of each logical product of the synthesis section 343. Data of the output terminals B1 to Bn of the latch unit 342 are sequentially input to one input terminal of each logical multiplication element of the second combining unit 344, and the sequential control signals L1 to Ln are input to the second. It is input in turn to the other input terminal of each logical multiplication element of the synthesis section 344.

Referring to Fig. 18, the data D1 to D2n of the single bank color signal RO (0) is output to the output terminals A1 to An and B1 to Bn of the latch unit 342 by the first clock pulse of the latch clock signal LATCK. Is maintained in turn. At this time, the data D1 to Dn are held for 2n clock pulse intervals of the main clock signal MCLK at the output terminals A1 to An, and the data Dn + 1 to D2n are the main clock signals at the output terminals B1 to Bn. It is held during the 2n clock pulse period of (MCLK). Referring to Fig. 18, each of the sequential control signals L1 to Ln has a high section repeated every 2n clock pulses of the main clock signal MCLK, and the high sections of two neighboring sequential control signals are sequentially located. Can be. In the first synthesis section 343, the logical AND element is logical AND operation of the two inputs, so that in any one logical AND element the corresponding output terminal data of the latch unit 342 during the high level period of the corresponding sequential control signal It is provided at the output of the logical multiplication device. At this time, since the high level section of the sequential control signal is the same as the two clock pulse section of the main clock signal MCLK, the pulse section of the data output from each logical multiplication device is doubled. The logical sum element of the first synthesizer 343 performs a logical sum operation on the outputs of the n logical multiplication elements, and then outputs the result as an odd component RO (0) of the improved single bank color signal. Referring to Fig. 18, the first synthesizing unit 343 processes the odd-numbered n data D1 to Dn, D2n + 1 to D3n, ... of the single bank color signal R (0), and the second synthesizing unit ( 344 processes the even-numbered n data (Dn + 1 to D2n, D3n + 1 to D4n, ...) of the single bank color signal R (0). The odd component RO (0) and the even component RE (0) of the improved single bank color signal obtained from the first and second synthesis sections 343 and 344 are combined with the odd data driving integrated circuit shown in Fig. 11 of the first embodiment. Each is input to an even data driving integrated circuit, thereby achieving a panel driving frequency reduction and compact design as already described.

The timing control apparatus of the liquid crystal display according to the second embodiment of the present invention is distinguished from the first embodiment in that it converts the single bank color signal into the improved single bank color signal according to the present invention.

Third Embodiment

Next, a timing control apparatus of the liquid crystal display according to the third embodiment of the present invention will be described with reference to FIGS. 19 to 22.

The timing control apparatus of the liquid crystal display according to the third embodiment of the present invention is similar to the second embodiment in that it converts the single bank color signal into the improved single bank color signal according to the present invention. However, the timing control device of this embodiment differs from the timing control device of the second embodiment in that a shift unit of the timing control device of the second embodiment is not used. Incidentally, the timing control device of this embodiment has a configuration similar to that of the timing control device of the second embodiment shown in FIG. The detailed configuration of the data signal processing section of this embodiment is different from that of the second embodiment, which is shown in Figs.

Fig. 19 shows in detail the data signal processor according to the third embodiment of the present invention.

As shown in FIG. 19, the data signal processor of the timing controller according to the third embodiment of the present invention inputs a main clock signal MCLK, a bi-division clock signal 2CLK, and a data enable signal DE. And a sequential signal generator 43 for generating latch control signals L1 to Ln and sequential control signals L_1 to L_n and a plurality of data processing cells 44 to 46.

Each data processing cell receives the data of the 1-bit line of the single bank color signal, the latch control signals L1 to Ln output from the sequential signal generator 43, and the sequential control signals L_1 to Ln. Odd and even components of the generated single bank color signal are generated. In the third embodiment of the present invention, since six bits are allocated to each color of a single bank color signal, a total of 18 data processing cells are required to process three colors of red (R), green (G), and blue (B) colors. Do. 19, only one of the 18 data processing cells 44 is shown in detail, and the other has the same internal configuration as the data processing cell shown in detail.

The data processing cell 44 receives the single bank color signal R (0) and generates odd component RO (0) and even component RE (0) of the improved single bank color signal.

In more detail, the data processing cell 44 includes a latch portion 441 and first and second synthesis portions 442 and 443. The latch unit 441 receives a color signal R (0) and latch control signals L1 to Ln of one bit line and outputs data of the color signal R (0) in response to the latch control signals L1 to Ln. . The latch portion 441 has n output lines. The latch control signals L1 to Ln are generated by the main clock signal CLK in the sequential signal generation unit 43. As shown in FIG. 22, each of the latch control signals L1 to Ln is represented as a main signal. It has a high level section repeated every n clock pulses of the clock signal CLK. The high level section is the same as the one clock pulse section of the main clock signal CLK, and each high level section is sequentially positioned in two neighboring latch control signals.

The first and second synthesis units 442 and 443 rearrange the data output from the latch unit 441 according to the control signals L_1 to L_n to improve the odd component RO (0) of the single bank color signal. And even component RE (0).

20 shows the latch portion 441 of FIG. 19 in more detail.

As shown in Fig. 20, the latch portion 441 is composed of n D-flip flops. A single bank color signal R (0) is commonly input to the data terminal of each D-flip-flop, and one of the latch control signals L1 to Ln is sequentially input to each clock terminal. In addition, the output terminals of the n D flip-flops form the n latch portions 441 output terminals A1 to An. Each D-flip-flop transfers the data of the data terminal to the output terminal whenever the clock pulse of the corresponding latch control signal is input, and maintains the current data at the output terminal until the next clock pulse of the latch control signal is input. . Referring to Fig. 22, the data D1 of the color signal R (0) is latched at the first D-flip flop by the first high level of the latch control signal L1, and the first high level of the latch control signal L2 is latched. By the level, the data D2 of the color signal R (0) is latched in the second D flip-flop. In a similar manner, the data Dn of the color signal R (0) is latched at the nth D-flip flop by the first high level of the latch control signal Ln. The data Dn + 1 of the color signal R (0) is then latched on the first D-flip flop by the second high level of the latch control signal L1. Therefore, at the output terminal A1 of the first D flip-flop, the data D1 of the color signal R (0) is maintained until the second high level is input from the first high level of the latch control signal L1. The same operation is performed on the other flip-flop. The output terminals A1 to An of the latch unit 441 are commonly input to the first synthesis unit 442 and the second synthesis unit 443. Since the output of the latch portion 441 is commonly input to the first and second synthesis portions 442 and 443, the output terminal of the latch portion 441 is denoted as '2n line' in FIG.

21 shows the first and second composite portions 442 and 443 in detail.

As shown in FIG. 21, the first synthesizing unit 442 includes n logical multiplication devices and logical multiplication devices receiving the outputs of the logical multiplication devices. Similarly, the second combining unit 443 includes n logical products and logical logic devices receiving the outputs of the logical products. Each logical multiplication device of the first and second synthesis units 442 and 443 has two input terminals.

In the first synthesis unit 442, one of n sequential control signals L_1 to L_n is sequentially input to one input terminal of each logical multiplication device, and the latch unit 441 of the latch unit 441 is input to the other input terminal of each logical multiplication device. One of the n output terminal A1 to An signals is input in turn.

As shown in Fig. 22, each of the n sequential control signals L_1 to L_n has a high level section appearing for every 2 n clock pulses of the main clock signal CLK, and the high level section is the main clock signal CLK. It is equal to 2 clock pulse interval of). Each high level of any two neighboring sequential control signals is sequentially located with each other.

The first synthesizing unit 442 of FIG. 21 sequentially ORs the sequential control signals L_1 to L_n and the output terminal A1 to An signals of the latch unit 441, and logically sums the result of the AND operation. Generate an odd component RO (0) of the improved single bank color signal shown in FIG. The data interval extended by twice the odd component RO (0) is obtained by each of the sequential control signal high level intervals.

In the second synthesis unit 443, one of the n latch unit 441 output terminals (A1 to An) signals is sequentially input to one input terminal of each logical multiplication device, and n sequentially to the other input terminal of each logical multiplication device. Control signals L_1 to L_n are input. At this time, the input order of the sequential control signals L_1 to L_n is different from that of the first synthesis unit 442. As shown in Fig. 21, the sequential control signal starts from the first half of n / 2 (L_n / 2 + 1) and the first half of n / 2 (L_n / 2) is sequentially input to each logical element. . After the n single bank color signal data is latched in the latch section 441, when the next n data is latched, the second synthesizer 443 logically operates the latched data to improve even components of the single bank color signal. Create

By adjusting the input order of the sequential control signals described above, the first synthesizing unit 442 processes the odd number n data of the single bank color signal, and the second synthesizing unit 443 processes the even n data of the single bank color signal. To process

As described above, the third embodiment according to the present invention latches a single bank color signal by a latch control signal, and outputs a single bank color signal improved by a logic operation of the first or second synthesizer before the next latch operation occurs. Create Therefore, the timing control device according to the third embodiment of the present invention does not require the shift portion, and the circuit becomes simpler.

Fourth Embodiment

Next, a timing control apparatus according to a fourth embodiment of the present invention will be described with reference to FIGS.

The timing controller according to the fourth embodiment of the present invention generates an improved single bank color signal even when a dual bank color signal or a single bank color signal is input. Further, the timing control apparatus according to the fourth embodiment of the present invention reduces the number of gate elements used by reducing the number of control signals. This is described in more detail below.

First, referring to FIG. 23, the timing control apparatus of the liquid crystal display according to the fourth exemplary embodiment of the present invention includes a control signal processor 51 and a data signal processor 52.

The control signal processor 51 receives the vertical and horizontal synchronization signals HSYNC and VSYNC, the data enable signal DE, and the main clock signal MCLK from an external device such as a graphic controller, and is required by the gate driver and the data driver. To generate control signals. That is, the control signal processor 51 uses a start signal to start a horizontal start signal (STHO, STHE), a vertical start signal (STV), a gate clock signal (CPV), and line inversion. A two-division clock signal 2CLK is generated by dividing the signal RVS, the gate-on enable signal OE, the load signal TP, and the main clock signal MCLK. The signals generated by the control signal processor 51 are provided to a gate driver (not shown), a data driver (not shown), and the data signal processor 52 of the liquid crystal display.

The data signal processor 52 receives a color signal and a main clock signal MCLK from an external device such as a graphic controller, and inputs a clock selection signal CLK-SEL from a switching device (not shown) such as an external jump switch. The controller receives a two-division clock signal 2CLK from the control signal processor 51. The clock selection signal CLK-SEL indicates whether the color signal input to the data signal processor 52 is a dual bank format or a single bank format. That is, the color signal is in the form of a single bank or a dual bank according to the type of graphic controller, and the one shown in FIG. 23 is a dual bank format. In the dual bank format, two signals are provided for one color signal by separating odd and even portions of data. For example, for the R (red) signal, as shown in Fig. 23, the RA (0: 5) and RB (0: 5) signals are provided. Here, (0: 5) means that the RA signal is composed of 6 bits, which is for multi-gradation display of the color signal. If the color signal is in the form of a single bank, RA (0: 5), GA (0: 5), and BA (0: 5) signals are input to the data signal processor 52.

The data signal processor 52 divides the color signals described above and arranges the data so that odd data [RO (0: 5), GO (0: 5), BO (0: 5)] and even data [ RE (0: 5), GE (0: 5), BE (0: 5)].

24 shows the data signal processor 52 of FIG. 23 in more detail.

Referring to FIG. 24, the data signal processing unit 52 is composed of a data divider 53, a latch pulse generator 54, and a plurality of data arrays 55 to 57, and the data array 55 A latch unit 551, an odd data adding unit 552, and an even data adding unit 553 are included.

Here, assuming that each color signal is composed of 6 bits, 18 data arrays are required for one data divider. However, in the fourth embodiment of the present invention, only one 55 is shown in detail in order to avoid the complexity of the drawing. It is. Therefore, the data signal processing unit 52 shown in FIG. 23 actually consists of one data divider, one latch pulse generator, and eighteen data arrays. Of course, each of these numbers depends on the number of bits of the color signal.

Referring to FIG. 24, the data divider 53 receives a signal of a corresponding bit of each color signal, a clock selection signal CLK-SEL, and a two-division clock signal 2CLK, and the clock selection signal CLK-SEL. Only when the color signal inputted from the single-bank format is divided, the inputted color signals are divided according to the two-division clock signal 2CLK, and the odd-numbered data and the even-numbered data are separated from the divided color signals to form a dual-bank type color signal. Create If the input color signal is of a dual bank format, the data divider 53 outputs the data as is without performing any additional processing. Conversion of the dual bank color signal according to the clock selection signal CLK-SEL may be implemented by a switching element such as a multiplex (not shown). Is not presented.

For example, when the color signals RA (0), GA (0), BA (0) of the single bank format are input to the data divider 53, the data divider 53 is subjected to the above-described division and separation operation. Accordingly, the dual bank format color signals RA '(0), RB' (0), GA '(0), GB' (0), BA '(0) and BB' (0) are generated. The circuit shown in Fig. 25 is circuit logic for converting the single bank color signal RA (0) into the dual bank color signal in the data divider 53. Referring to FIG. 25, a single bank color signal RA (0) is commonly input to data terminals of two D-flip flops, a two-division clock signal 2CLK is input to a clock terminal of an upper D-flip flop, and The inverted signal of the two-division clock signal is input to the clock terminal of the D flip-flop. A delay unit is connected to the output terminal of the upper D flip-flop. The upper D-flip-flop latches the single bank color signal RA (0) to the output at the rising edge of the two-division clock signal 2CLK, and the lower D-flip-flop is the falling edge of the two-division clock signal 2CLK. At the falling edge, the single bank color signal RA (0) is latched to the output terminal. Therefore, odd data ODD and even data EVEN of the single bank color signal RA (0) are separated. Since the period of the bi-division clock signal 2CLK is twice the period of the main clock signal MCLK, the data section of the odd data ODD and the even data EVEN is twice the data section of the single bank color signal. The delay unit delays the odd data by a predetermined time to match the start time of the odd data ODD and the even data EVEN.

Fig. 31 shows waveforms of the color signal RA (0: 5) in the single bank format and the color signals RA '(0: 5) and RB' (0: 5) in the dual bank format, and the respective color signals RA (0: 5). , Any one of six bits of RA '(0: 5) and RB' (0: 5) is shown. In FIG. 31, RO (0: 5) and RE (0: 5) are examples of odd and even components of the improved single bank color signal generated by the data arranging unit 55. FIG.

The latch pulse generator 54 receives the main clock signal CLK and the two-division clock signal 2CLK, and the latch control signal {C (1: L)} and the summation control signal {SAO (1: M), SBO. (1: M), SAE (1: M), SBE (1: M)}. Here, L is the number of flip-flops used in the latch unit 551, M is smaller than L and is a flexible value determined by the efficiency of the hardware design. In the fourth embodiment of the present invention, L is 36 and M is 26. For reference, the channel number of the data driving integrated circuit is 100.

As already mentioned, 18 data arrays are provided for one data divider. Referring to Fig. 24, the data arranging unit 55 processes the color signals RA '(0) and RB' (0) generated by the data dividing unit 53.

More specifically, the latch unit 551 may include the latch control signal {C (1) such that the color signals RA '(0) and RB' (0) generated by the data divider 53 have a predetermined data arrangement order. : L)}. The output of the latch unit 551 determined by the selection is provided to the first synthesis unit 552 and the second synthesis unit 553.

The first synthesis unit 552 performs a logical operation on the output of the latch unit 551 based on the sum order determined according to the summation control signals SAO (1: M) and SBO (1: M). The second combining unit 553 may perform an operation on the output of the latch unit 551 based on a sum order determined according to the summation control signals SAE (1: M) and SBE (1: M). Perform a logical operation. As a result, an odd component RO (0) is generated in the first synthesis unit 552 with respect to the color signals RA (0), RB (0) of the corresponding bit, and the even component RE in the second synthesis unit 553 is generated. (0) is generated. At this time, the latch control signal of the latch unit 551 and the sum control signal of the summation units 552 and 553 are equal to the number of channels of the data driving integrated circuit in the odd data RO (0) and the even data RE (0). n), it is predetermined to alternate data rows.

Referring to the waveform diagram of FIG. 30, the vertical synchronization signal HSYNC, the main clock signal MCLK, the data enable signal DE, any one color signal RA in the form of a single bank, and the color signal RA Odd and even components (RO, RE) and bi-division clock signal 2CLK are shown.

Fig. 30 shows waveforms of signals when the number of channels of the data driver integrated circuit (not shown) of the liquid crystal display device is 100. Figs. It can be seen from the waveform diagram that 100 data rows of the color signal RA alternately appear in the odd component RO and the even component RE of the color signal according to the present invention. Further, the data holding time of the odd component RO and the even component RE is twice the data holding time of the single bank color signal RA.

As already described with reference to Fig. 11, the odd component RO is input to the odd data driving integrated circuit, and the even component RE is input to the even data driving integrated circuit. Of course, odd and even components of other color signals are also input in the same manner as above. Each of the data driving integrated circuits drives the liquid crystal panel in dual mode by the color signals of the odd and even components. At this time, since the data holding time is twice that of the single bank method, the same display operation is made possible only by 1/2 of the driving frequency in the single bank method.

26 shows the latch pulse generator 54 of FIG. 24 in more detail.

As shown in FIG. 26, the latch pulse generator 54 is a block for generating first sequence control signals E1 to E100 and second sequence control signals E1 'to E100', and the first sequence. A first logical sum block for generating a latch control signal using the control signals E1 to E100, and a second logical sum block for generating a summation control signal using the second sequential control signals E1 'to E100'. It includes.

When the number of channels of the data driving integrated circuit of the liquid crystal display device is n, the block includes 2n D-flip flops and start pulse generators connected in series with each other. The start pulse generator receives the data enable signal DE and the two-division clock signal 2CLK and generates a start signal having a high section pulse repeated every n clock pulses of the two-division clock signal 2CLK. The start signal is input to the first D flip-flop. The two-division clock signal 2CLK is input to the clock terminal of the odd-numbered D-flip flop, and the inverted signal of the two-division clock signal is input to the clock terminal of the even-numbered D-flip flop. The odd-numbered D-flip-flop latches the data terminal signal to the output terminal at the rising edge of the two-division clock signal, and the even-numbered D-flip-flop latches the data terminal signal to the output terminal at the falling edge of the two-division clock signal. Each output terminal signal of the odd-numbered D-flip flop is transmitted to the flip-flop of the next stage and output as the first sequential control signals E1 to E100. Each output terminal signal of the even-numbered D-flip-flop is transmitted to the flip-flop of the next stage and output as the second sequential control signals E1 'to E100'. Since the first sequential control signal and the second sequential control signal are obtained by being latched at the divided clock signal, the rising edge and the poly edge, respectively, there is a phase difference corresponding to the half clock pulse of the divided clock signal.

The n first sequential control signals are input to the first logical sum block, and at least two or more first sequential control signals are ORed together to form one latch control signal. Similarly, n second sequential control signals are input to a second logical sum block, and at least two or more second sequential control signals are ORed together to form a summation control signal. As described above, by combining at least two sequential control signals to generate one latch control signal and the summation control signal, the number of the latch control signal and the summation control signal is smaller than the number of channels n, which is used in the data arranging unit. The number of flip-flops and the number of gate devices may be reduced.

Next, the data arranging unit 55 of FIG. 24 will be described in more detail with reference to the circuit diagrams of FIGS. 27 to 29 and the waveform diagram of FIG.

Referring to Fig. 27, the latch unit 551 includes L flip-flops FF1 to FF36 for latching the color signal RA '(0) input from the data divider 53 in accordance with the latch control signals C1 to C36. And L flip-flops FF37 to FF72 for latching the color signal RB '(0) in accordance with the latch control signals C1 to C36. Each flip-flop is a D-flip-flop, but the technical scope of the present invention is not limited thereto, and may be implemented as other types of flip-flops. As already assumed, L is 36.

The color signal RA '(0) is commonly input to the data input terminal of each flip-flop in the L flip-flops FF1 to FF36, and among the L latch control signals C1 to C36 to the clock input terminal of each flip-flop. The corresponding one is entered. In the L flip-flops FF37 to FF72, the color signal RB '(0) is commonly input to the data input terminal of each flip-flop, and among the L latch control signals C1 to C36 to the clock input terminal of each flip-flop. The corresponding one is entered.

Each flip-flop maintains a signal at the data input at the output edge at the rising edge of the clock input signal. Referring to FIG. 27, at the rising edge of the latch control signal C1, the flip-flop FF1 latches the data D1 of the color signal RA '(0) of the data input terminal to the output terminal, and the flip-flop FF1 is latched. The data D1 is held at the output terminal A1 until the next rising edge of the control signal C1. On the other hand, since one latch control signal C1 is connected to two flip-flops FF1 and FF37 at the same time, a pair of two flip-flops FF1 and FF37 on the top and the bottom are paired by the rising edge of the latch control signal C1. The color signals RA '(0) and RB' (0) 's first data (D1, D2) are simultaneously latched. In a manner similar to the above, the other flip-flop also latches the signal at the data input terminal by the corresponding latch control signal.

The output data of each of the flip-flops FF1 to FF72 are provided to the odd data adder 552 and the even data adder 553. Further, the latch control signals C1 to C36 cause the above operation to be repeated in units of n channels in the data strings of the color signals RA '(0) and RB' (0). If the number of channels of the data driving integrated circuit is 300, the latch operation by the latch control signals C1 to C36 is repeated for every 300 data of the color signals RA '(0) and RB' (0).

In addition, as shown in FIG. 32, since each latch control signal has at least two rising edges during n clock pulses of the bi-division clock signal, a much smaller number of latch control signals are used than the number of channels. Due to this, the number of flip-flops and the complexity of the circuit can be avoided.

Next, referring to FIG. 28, a first synthesis unit 552 is shown.

The first synthesis unit 552 includes M logical AND elements AND1 to AND26 for inputting summation control signals SAO1 to SAO26 and output signals of the latch unit 551 corresponding thereto, and the logical AND element ( Logical sum element OR1 for inputting the output signals of AND1 to AND26, M control signals SBO1 to SBO26, and M logical multiplication elements AND27 to AND52 for inputting the output signal of the latch unit 551 corresponding thereto. A logical sum element OR2 for inputting the output signals of the AND products AND27 to AND52 and an OR signal for inputting the output signals of the two OR elements OR1 and OR2 to generate an odd data signal RO (0); OR3).

In each AND device, an AND operation is performed on two input signals. An OR operation is performed on the OR signal OR1 and an AND2 operation is performed on an output signal of the AND products AND1 to AND26. The OR operation is performed on the output signals of the AND-AND devices AND27 to AND52, and the OR operation is performed on the output signals of the two OR devices OR1 and OR2.

Through the logic circuit of the above structure, the output signal of the corresponding latch portion 551 in the high level period of any summation control signal is provided as the odd data signal RO (0). For example, the summation control signal SAO1 and the output terminal signal A1 of the flip-flop FF1 are input to the AND product AND1, and as shown in FIG. 32, the summation control signal SAO1 is brought to a high level. Then, the output terminal signal A1 of the flip-flop FF1 at that time is provided as an odd data signal RO (0).

Further, from the waveform diagram shown in Fig. 32, the high level timing of each of the summation control signals SAO1 to SAO26, SBO1 to SBO26 indicates that the data of the color signals RA '(0) and RB' (0) are not included in the data driving integrated circuit. It is predetermined to alternate once every two times by the number corresponding to the number of channels. For example, when the number of channels of the data driving integrated circuit is 100, the odd component RO (0) and the even component RE (generated by the first and second synthesis units 552 and 553 of FIGS. 0) is as shown in FIG. That is, as shown in FIG. 30, the data of color signals alternately appear in units of 100 in the odd component RO. More specifically, the first 100 data of the color signal RA appear in the odd component RO and the next 100 data appear in the even component RE, which is repeated over and over again to produce an improved single bank color signal according to the invention. Create

29 is a circuit showing the second synthesis unit 553 in detail, and is the same circuit as the first synthesis unit 552. However, the input signal of each logical product of the second synthesis unit is different from that of the first synthesis unit.

Referring to FIG. 29, the second synthesis unit 553 includes M logical AND elements AND1 to AND26 for inputting the summation control signals SAE1 to SAE26 and the output signals of the latch units 551 corresponding thereto. Logical sum element OR1 for inputting the output signals of the AND products AND1 to AND26, M control elements SBE1 to SBE26, and M logical element elements for inputting the output signal of the latch unit 551 corresponding thereto. An even data signal RE (0) is generated by inputting the AND signals OR27 to AND52, the OR signal inputting the output signals of the AND products AND27 to AND52, and the output signals of the two OR signals OR1 and OR2. And a logical sum element OR3.

The odd and even components generated as described above are input to the odd data driving integrated circuit and the even data driving integrated circuit, respectively.

Accordingly, since the odd data driver integrated circuits are operated by the odd component and the even data driver integrated circuits are operated by the even component simultaneously, the odd data driver integrated circuits and the even data driver integrated circuit are operated in the dual mode. Can be driven. In addition, when the same driving time as that of the single bank method is given, the time required to drive one data line through the dual mode driving of the data line is doubled, so that the operating frequency is 1/2 of the single bank method. Can be reduced.

The fourth embodiment of the present invention described above can generate an improved single bank color signal according to the present invention even if a single bank color signal or a dual bank color signal is input, and the flip-flop and gate elements to be used by reducing the signal line of the control signal. Can be reduced.

The timing controller of the present invention generates an improved single bank color signal, thereby reducing the driving frequency of the liquid crystal panel, and allowing the data driving integrated circuit to be arranged on one side of the liquid crystal panel, thereby making the compact design of the liquid crystal display device possible. To make it possible.

Claims (24)

A control signal processor which receives the vertical and horizontal synchronization signals and the main clock signal and generates a control signal output to the gate driver and the data driver of the liquid crystal display; A sequential signal generator for receiving a main clock signal and a data enable signal and generating a latch clock signal and a sequential control signal; It is composed of two blocks each responsible for odd data and even data of the dual bank color signal according to the main clock signal, and each block sequentially shifts the applied data signal and simultaneously performs n odd data and n even data. A plurality of shift units for outputting; A plurality of latch units for simultaneously outputting n odd data and n even data output from the shift unit according to the latch clock signal; A plurality of products that alternately multiply n / 2 odd data and n / 2 even data output from the latch unit with the sequential control signal, and generate an odd component of a color signal by ORing the result of each AND operation; 1 synthesis part; And Alternately logically multiply the remaining n / 2 odd data and the remaining n / 2 even data output from the latch unit with the sequential control signal, and generate an even component of the color signal by ORing the result of each AND operation Including a plurality of second synthesis, Timing control device of liquid crystal display device. The method of claim 1, wherein one of the plurality of shift units is A first n-flip flop connected in series with each other to sequentially shift the odd data, and a second n-flip flop connected in series with each other to sequentially shift the even data; Each flip-flop performs a shift operation according to the main clock signal. Timing control device of liquid crystal display device. The method of claim 2, wherein one of the plurality of latch units And a third n-flip flop that receives the output of the first n-flip flop, and a fourth n-flip flop that receives the output of the second n-flip flop, respectively. The flop and the fourth n-flip flop simultaneously latch the input to an output terminal according to the latch clock signal; Timing control device of liquid crystal display device. The method of claim 3, wherein one of the plurality of first synthesis portions is N logical AND elements each having two input terminals and OR logically multiplying the two input terminal signals, and a logical sum element receiving the output of each logical AND element and performing an OR operation, The n / 2 outputs of the third n-flip-flop and the n / 2 outputs of the fourth n-flip-flop are alternately input to one input terminal of the n logical products, and the sequential control signal is n Input to the other input of the logical AND element in turn, Timing control device of liquid crystal display device. The method of claim 3, wherein one of the plurality of second synthesis portion is N logical AND elements each having two input terminals and OR logically multiplying the two input terminal signals, and a logical sum element receiving the output of each logical AND element and performing an OR operation, The remaining n / 2 outputs of the third n-flip flop and the remaining n / 2 outputs of the fourth n-flip flop are alternately input to one input terminal of the n logical multiplication elements, and the sequential control signal is Sequentially input to the other input terminals of the n logical products, Timing control device of liquid crystal display device. A control signal processor which receives the vertical and horizontal synchronization signals and the main clock signal and generates control signals for the gate driver and the data driver of the liquid crystal display; A sequential signal generator for receiving a main clock signal and a data enable signal and generating a latch clock signal and a sequential control signal; A plurality of shift units for sequentially shifting and simultaneously outputting odd data and even data of a dual bank color signal according to the main clock signal; A plurality of latch units for simultaneously outputting n odd data and n even data output from the shift unit according to the latch clock signal; A plurality of products that alternately multiply n / 2 odd data and n / 2 even data output from the latch unit with the sequential control signal, and generate an odd component of a color signal by ORing the result of each AND operation; 1 synthesis part; Alternately logically multiply the remaining n / 2 odd data and the remaining n / 2 even data output from the latch unit with the sequential control signal, and generate an even component of the color signal by ORing the result of each AND operation A plurality of second synthesis parts; A plurality of odd data driving integrated circuits each having n number of channels and receiving an odd component of color signals provided from the plurality of first synthesis units to generate a liquid crystal driving signal; A plurality of even data driving integrated circuits each having n number of channels and receiving even components of color signals provided from the plurality of second synthesis units to generate liquid crystal driving signals; And It includes a liquid crystal panel for performing a predetermined display operation in accordance with the liquid crystal drive signal provided from the plurality of data driving integrated circuit, Wherein the plurality of odd data driver integrated circuits and the plurality of even data driver integrated circuits are arranged in a line on either side of the liquid crystal panel; Liquid crystal display. A control signal processor which receives the vertical and horizontal synchronization signals and the main clock signal and generates control signals for the gate driver and the data driver of the liquid crystal display, a bi-division clock signal obtained by dividing the main clock signal into two, and a latch clock signal; A sequential signal generator for generating a sequential control signal from a data enable signal and the divided clock signal; A plurality of shift units which receive a single bank color signal and sequentially shift and simultaneously output data of the color signal according to the main clock signal; A plurality of latch units for separating the data of the color signal output from the shift unit by n and outputting the separated 2n data simultaneously according to the latch clock signal; A first synthesizer for logically multiplying n pieces of data output from the latch unit with the sequential control signal, and generating an odd component of a color signal by logically adding the result of each logical product operation; And And a second synthesizer configured to logically multiply the remaining n data output from the latch unit with the sequential control signal, and to generate an even component of a color signal by logically adding the result of each logical product operation. Timing control device of liquid crystal display device. 8. The method of claim 7, wherein one of the plurality of shift units is In order to sequentially shift the data of the single bank color signal, it is composed of 2n flip-flops connected in series, each flip-flop performs the data shift operation according to the main clock signal, Timing control device of liquid crystal display device. The method of claim 8, wherein one of the plurality of latch units A first n-flip-flop that receives n of the outputs of the 2n flip-flops, and a second n-flip-flop that receives the remaining n of the outputs of the 2n flip-flops, respectively; The first n-flip flop and the second n-flip flop simultaneously latch the input to an output terminal according to the latch clock signal; Timing control device of liquid crystal display device. 10. The method of claim 9, wherein one of the plurality of first synthesis portions N logical AND elements each having two input terminals and OR logically multiplying the two input terminal signals, and a logical sum element receiving the output of each logical AND element and performing an OR operation, The output of the first n-flip-flop is sequentially input to one input terminal of the n logical products, and the sequential control signal is sequentially input to the other input terminal of the n logical products, Timing control device of liquid crystal display device. The method of claim 9, wherein one of the plurality of second synthesis portions N logical AND elements each having two input terminals and OR logically multiplying the two input terminal signals, and a logical sum element receiving the output of each logical AND element and performing an OR operation, The output of the first n-flip-flop is sequentially input to one input terminal of the n logical products, and the sequential control signal is sequentially input to the other input terminal of the n logical products, Timing control device of liquid crystal display device. A control signal processor which receives the vertical and horizontal synchronization signals and the main clock signal and generates control signals for the gate driver and the data driver of the liquid crystal display, a bi-division clock signal obtained by dividing the main clock signal into two, and a latch clock signal; A sequential signal generator for generating a sequential control signal from a data enable signal and the divided clock signal; A plurality of shift units which receive a single bank color signal and sequentially shift and simultaneously output data of the color signal according to the main clock signal; A plurality of latch units for separating the data of the color signal output from the shift unit by n and outputting the separated 2n data simultaneously according to the latch clock signal; A first synthesizer for logically multiplying n pieces of data output from the latch unit with the sequential control signal, and generating an odd component of a color signal by logically adding the result of each logical product operation; A second synthesizer which logically multiplies the remaining n data output from the latch unit with the sequential control signal, and generates an even component of a color signal by ORing the result of each AND operation; A plurality of odd data driving integrated circuits each having n number of channels and receiving an odd component of color signals provided from the plurality of first synthesis units to generate a liquid crystal driving signal; A plurality of even data driving integrated circuits each having n number of channels and receiving even components of color signals provided from the plurality of second synthesis units to generate liquid crystal driving signals; And It includes a liquid crystal panel for performing a predetermined display operation in accordance with the liquid crystal drive signal provided from the plurality of data driving integrated circuit, Wherein the plurality of odd data driver integrated circuits and the plurality of even data driver integrated circuits are arranged in a line on either side of the liquid crystal panel; Liquid crystal display. A control signal processor configured to receive vertical and horizontal synchronization signals and a main clock signal, and generate a control signal for a gate driver and a data driver of the liquid crystal display, and a two-division clock signal divided into two main clock signals; N latch control signals having a high level section equal to one clock pulse section of the main clock signal for every n clock pulses of the main clock signal, receiving a main clock signal, a divided clock signal, and a data enable signal; A sequential signal generator for generating n sequential control signals having a high level interval equal to one clock pulse interval of the two divided clock signals for every n clock pulses of the two divided clock signals; Receives a single bank color signal and the latch control signal, sequentially outputs data of the single bank color signal in the high section of each latch control signal, and maintains the output state until the next high section of the latch control signal is input. A plurality of latch portions to hold; A plurality of first synthesizing units which logically multiply data of the color signals output from the latch unit with the sequential control signals within the sustain period, and generate odd components of the color signals by ORing the result of each AND operation; And And a plurality of second synthesis units which logically multiply the data of the color signals output from the latch unit within the sustain period with the sequential control signals whose order is adjusted, and generate an even component of the color signal by logically adding the result of each logical product operation. doing, Timing control device of liquid crystal display device. The method of claim 13, wherein one of the plurality of latch units N flip-flops which receive the single bank color signal in common at an input terminal, wherein each flip-flop latches data of the single bank color signal according to a corresponding one of n corresponding latch control signals; Timing control device of liquid crystal display device. 15. The method of claim 14, wherein one of the plurality of first synthesis portions N logical AND elements each having two input terminals and OR logically multiplying the two input terminal signals, and a logical sum element receiving the output of each logical AND element and performing an OR operation, The outputs of the n flip-flops are sequentially input to one input terminal of the n logical AND elements, and the sequential control signal is sequentially input to the other input terminals of the n logical AND elements. Timing control device of liquid crystal display device. 15. The method of claim 14, wherein one of the plurality of second synthesis portions N logical AND elements each having two input terminals and OR logically multiplying the two input terminal signals, and a logical sum element receiving the output of each logical AND element and performing an OR operation, The n flip-flop outputs are sequentially input to one input terminal of the n logical multiplication elements, and the sequential control signals are sequentially input from the second n / 2, and the first n / 2 are sequentially input, and then the input to the other input terminal of the n logical AND elements in turn, Timing control device of liquid crystal display device. A control signal processor configured to receive vertical and horizontal synchronization signals and a main clock signal, and generate a control signal for a gate driver and a data driver of the liquid crystal display, and a two-division clock signal divided into two main clock signals; N latch control signals having a high level section equal to one clock pulse section of the main clock signal for every n clock pulses of the main clock signal, receiving a main clock signal, a divided clock signal, and a data enable signal; A sequential signal generator for generating n sequential control signals having a high level interval equal to one clock pulse interval of the two divided clock signals for every n clock pulses of the two divided clock signals; Receives a single bank color signal and the latch control signal, sequentially outputs data of the single bank color signal in the high section of each latch control signal, and maintains the output state until the next high section of the latch control signal is input. A plurality of latch portions to hold; A plurality of first synthesizing units which logically multiply data of the color signals output from the latch unit with the sequential control signals within the sustain period, and generate odd components of the color signals by ORing the result of each AND operation; A plurality of second combining units which logically multiply data of the color signals output from the latch unit within the sustain period with the sequential control signals whose order is adjusted, and generate an even component of the color signals by logically adding the result of each logical product operation; A plurality of odd data driving integrated circuits each having n number of channels and receiving an odd component of color signals provided from the plurality of first synthesis units to generate a liquid crystal driving signal; A plurality of even data driving integrated circuits each having n number of channels and receiving even components of color signals provided from the plurality of second synthesis units to generate liquid crystal driving signals; And It includes a liquid crystal panel for performing a predetermined display operation in accordance with the liquid crystal drive signal provided from the plurality of data driving integrated circuit, Wherein the plurality of odd data driver integrated circuits and the plurality of even data driver integrated circuits are arranged in a line on either side of the liquid crystal panel; Liquid crystal display. A control signal processor for inputting vertical and horizontal synchronization signals and a main clock signal to generate a signal for controlling the gate driver and the data driver of the liquid crystal display, and generating a clock signal obtained by dividing the main clock signal into two; When the color signal input from the external selection signal is a single bank, the single bank color signal is converted into a dual bank color signal according to the two-division clock signal. When the color signal input from the external selection signal is a dual bank, the color signal without conversion is performed. A data divider for outputting a; Receiving a data enable signal and a divided clock signal, and generating a first sequential control signal and a second sequential control signal from the data enable signal and the divided clock signal, and generating at least two or more of the first sequential control signals A plurality of latch pulse generators for generating a latch control signal by performing an OR operation, and generating an addition control signal by performing an OR operation on at least two of the second sequential control signals; And For each color signal, odd data and even data of the dual bank color signal outputted from the data divider are latched in accordance with the latch control signal, and the odd component of the color signal is generated by a logical operation between the latched data and the summing control signal. A plurality of data arrays for generating even components, The latch control signal and the summation control signal are predetermined so that data of a color signal alternates with the number of channels of the data driving integrated circuit in the odd component and the even component, and the odd component is applied to the odd data driving integrated circuits of the data driver. At the same time the even data is input to the even-numbered data driving integrated circuits of the data driver. Timing control device of liquid crystal display device. 19. The system of claim 18, wherein one of the plurality of data arrays is A latch unit which receives a color signal from the data divider and latches data of the color signal according to the latch control signal; A first synthesis unit for performing an AND operation on the output of the latch unit according to the addition control signal, and generating an odd component of a color signal by performing an OR operation on each OR product result; And And an even data summing unit for ORing the output of the latch unit according to the summing control signal and generating an even data signal by ORing each OR product result. Timing control device of liquid crystal display device. The method of claim 19, wherein the latch unit Odd data of the dual bank color signal output from the data divider is commonly input to each data input terminal, one of the latch control signals is input through each clock input terminal, and data of a corresponding data input terminal according to the latch control signal is received. A first latch portion configured of a plurality of flip-flops for latching the to the output terminal; And The even data of the dual bank color signal output from the data divider is commonly input to each data input terminal, and one of the latch control signals is input through each clock input terminal, and data of a corresponding data input terminal according to the latch control signal is received. Has a second latch portion consisting of a plurality of flip-flops for latching the Timing control device of liquid crystal display device. 21. The apparatus of claim 20, wherein each of the flip-flops is a D-flip flop that latches data of a data input terminal to an output terminal at a rising edge of the latch control signal. The method of claim 20, wherein the first synthesis unit A plurality of logical AND elements configured to receive one output terminal signal among the plurality of flip-flops of the first latch unit and one of the summing control signals, and perform an AND operation on the two input signals; A plurality of logical AND elements configured to receive one output terminal signal among the plurality of flip-flops of the second latch unit and one of the summing control signals, and perform an AND operation on the two input signals; And Comprising a logical sum of the output signal of the logical AND device of the two groups, respectively, and the logical sum of the logical OR of the respective outputs, Timing control device of liquid crystal display device. The method of claim 20, wherein the second synthesis unit A plurality of logical AND elements configured to receive one output terminal signal among the plurality of flip-flops of the first latch unit and one of the summing control signals, and perform an AND operation on the two input signals; A plurality of logical AND elements configured to receive one output terminal signal among the plurality of flip-flops of the second latch unit and one of the summing control signals and perform an AND operation on the two input signals; And And a plurality of logical sum elements for respectively ORing the output signals of the two logical AND elements and re-ORing the respective ORed outputs. A control signal processor for inputting vertical and horizontal synchronization signals and a main clock signal to generate a signal for controlling the gate driver and the data driver of the liquid crystal display, and generating a clock signal obtained by dividing the main clock signal into two; When the color signal input from the external selection signal is a single bank, the single bank color signal is converted into a dual bank color signal according to the two-division clock signal. When the color signal input from the external selection signal is a dual bank, the color signal without conversion is performed. A data divider for outputting a; Receiving a data enable signal and a divided clock signal, and generating a first sequential control signal and a second sequential control signal from the data enable signal and the divided clock signal, and generating at least two or more of the first sequential control signals A plurality of latch pulse generators for generating a latch control signal by performing an OR operation, and generating an addition control signal by performing an OR operation on at least two of the second sequential control signals; For each color signal, odd data and even data of the dual bank color signal outputted from the data divider are latched in accordance with the latch control signal, and the odd component of the color signal is generated by a logical operation between the latched data and the summing control signal. A plurality of data arrays for generating even components; A plurality of odd data driving integrated circuits each having n number of channels and receiving an odd component of a color signal provided from the plurality of data arranging units to generate a liquid crystal driving signal; A plurality of even data driving integrated circuits each having n number of channels and generating even liquid crystal driving signals by receiving even components of color signals provided from the plurality of data arranging units; And It includes a liquid crystal panel for performing a predetermined display operation in accordance with the liquid crystal drive signal provided from the plurality of data driving integrated circuit, And the plurality of odd data driver integrated circuits and the plurality of even data driver integrated circuits are arranged in one line on either side of the liquid crystal panel.