JPH0420992A - Liquid crystal display driving system - Google Patents

Abstract

PURPOSE:To facilitate switching between double definition display and standard definition display by using two A/D converting circuits for one picture data in the case of column line driving and selecting whether data should pass a delay circuit or not by one converting circuit to generate digital gradation data. CONSTITUTION:One analog gradation data 1 is branched and is inputted to two A/D converting circuits 3 and 4, and tow-phase sampling clocks 5 and 6 are inputted there also, and the output of one circuit 3 passes a delay circuit 7 in the case of double definition display but does not pass the circuit 7 in the case of standard definition display and is selected by a selecting circuit 8, and two digital gradation data 9 and 10 corresponding to two adjacent picture data subjected to A/D conversion are stored in memories 111 to 115. Two S gradation data obtained by repeated read of these data are arranged by a processing part 12 and are converted to analog gradation data and are stored in memories 141 to 145. Data are outputted from source driving circuits 131 to 135, and one or two column lines are selectively driven with a control signal 16 by a gate driving circuit 15 to display a picture.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention enables image display on a multi-gradation liquid crystal display to be freely changed between S semi-definition display and double-definition display with double height and width. This invention relates to a liquid crystal display driving method that aims to achieve this.

[Conventional technology]

Conventionally, in a multi-gradation liquid crystal display, each line is divided into column lines (also called source lines and data lines) and row lines (also called gate lines) arranged in a two-dimensional matrix in a display panel. A drive circuit is provided for driving the.

An electric signal corresponding to gradation image data is set in the source drive circuit that drives the column lines, while the electric signal is sent from the source drive circuit while selectively driving the row lines by the gate drive circuit that selects the 9th row line. Gradation data is sent and written to all pixels (a pixel is the minimum display unit in a display panel) connected to one row line through a column line. This operation is repeated each time each row line is selected one after another.

Generally, when transferring analog image data to the source drive circuit of a multi-gradation liquid crystal display, voltage level conversion and pixel rearrangement are performed, and then the data is stored in the memory in the source drive circuit. After the pixel data is set, the source drive circuit outputs all pixel data of the row line through the column line, and in synchronization with this, the gate drive circuit selectively drives the row line. Transfer all pixel data of the line to another memory in the source drive circuit from the outside and set it, and when the output to the column line is completed and the selection drive of the row line is completed, the 9th row line is selected and the data is transferred to the memory. All corresponding pixel data within is outputted through the column line.

These operations are repeated from the bottom row to the bottom row of the two-dimensional matrix in the display panel to perform two-screen display.

As another method, for example, analog image data from a computer or the like is first converted into digital image data and then subjected to various image processing.

After that, digital analog (hereinafter referred to as A/D)
Conversion is performed and the two-tone analog image data is sequentially sent to the memory in the source drive circuit, and then.

As described above, analog image data is sent to all pixels in one row line by the operations of the source drive circuit and the gate drive circuit, and screen display is performed by repeating these operations.

When looking at the two-dimensional matrix within the display panel of a multi-gradation liquid crystal display, Figure 2 (1) shows.

As shown in (2) and (3), in the case of (1) monochrome,
The pixels are connected to one row line, but (2) in the case of color display, when the RGBtli elements of the color pixels are in a delta pixel arrangement, the RGB pixels are distributed and connected to two gate lines,
(3) In the case of color display, there are two types of pixel arrays in the display, such as connecting RGB pixels to one gate line in the case of a stripe pixel array, and each has two columns for storing data in the source drive circuit. The driving method by the gate driving circuit differs depending on the output to the line. Therefore, in the case of double-definition display and in the case of standard-definition display, a display panel having a different number of column lines and a different number of row lines, and a source drive circuit and a gate drive circuit to operate the panel are required.

A document that describes this type of technology is "Liquid Crystal Device Handbook" 2 Nikkan Kogyo Shimbunsha, 1989.
Chapter 6 (pages 387-466) describes drive writing methods for liquid crystal displays, and Chapter 7 (pages 467-52)
Page 3) describes the color display method of liquid crystal displays.

[Problem to be solved by the invention]

Conventional double-definition liquid crystal display panels and standard-definition liquid crystal display panels each require dedicated display panels. Furthermore, since the speeds of the input image signals handled are different, the operating speeds of the source drive circuit and gate drive circuit that drive the panel are different, and this has been dealt with by changing the configuration or using different drive circuits. These various drive circuits drive many column lines and 9 row lines in the panel, so dedicated multi-output ICs with a large number of drive terminals have been developed, and in addition, source drive circuits have two types of display: monochrome or monochrome.
Various ICs have been developed and used to process digital image signals depending on whether they are multicolor or full color, or to process analog image signals. However, these
Compatible with the high resolution 9-color LCD display panel,
2. For example, instead of using the same display panel or the same circuit configuration for both double-definition display and standard-definition display, we prepare a wide variety of products and select them according to the application. I had to choose.

An object of the present invention is to use a double-definition display panel to realize double-definition display and standard-definition display using the same panel, the same drive circuit, and the like.

[Means to solve the problem]

In order to achieve the above object, the present invention uses a 1x definition display panel, and in a source drive system circuit, 1x resolution display panel is used.
Two A/D conversion circuits are used for each image data, and the phase of the sampling clock applied to the two A/D conversion circuits is changed depending on whether the externally input analog image signal is a double-definition image signal or a standard-definition image signal. By doing this, data processing of the source drive system is performed, and as a result, the source drive circuit has the same circuit configuration, and when row line driving by the gate drive circuit is used, the output operation from the source drive circuit is changed in the case of double-definition display. Select one row line in synchronization, and in case of standard definition display, select two adjacent row lines at the same time, or select two adjacent row lines (gate lines) at the same time with one line in between. This method drives the liquid crystal display.

[Effect]

By applying the liquid crystal display driving method described above to perform liquid crystal display, the same liquid crystal display panel and the same circuit configuration can be used to
Switching between double-definition display and standard-definition display can be easily realized.

〔Example〕

First Embodiment An embodiment of a circuit configuration to which the liquid crystal display driving system of the present invention is applied is shown in FIG. 1. In this embodiment, there is only one externally input analog gradation data 1.

The liquid crystal gradation display panel 2 shown in FIG. 2(1) is composed of 2m (m is an integer) column lines and 2n (n is an integer) row lines.

In this embodiment, one analog gradation data 1 is divided into two A/D conversion circuits (A/Dx - A/D
, ) 3.4 and a two-phase sampling clock (S
CKI, 5CK2) 5.6 is input to the above A/D conversion circuit, and from one A/D conversion circuit it is passed through delay circuit (D) 7 for double definition display, and for standard definition display. is selected by the 9 selection circuit (S) 8 without passing through the delay circuit (D) 7.

2 corresponding to two adjacent pixel data that have been A/D converted
The digital gradation data 9 and 10 are stored in the memories 111 to 1.
1. Store in. In this case, the data is data of a pixel connected to one row line of the liquid crystal display. The digital gradation data is stored in the first memory 11 of the eight memories.
1 to Sth memory 11. m/8 times each,
This is stored repeatedly in sequence. After that, the eight memories 111 to 11. Parallel readout is repeated m/s times from m/s, and the processing unit 12 processes the 28 digital gradation data such as pixel position arrangement of the data, converts it into analog gradation data, and converts it into analog gradation data. Source drive circuits 13□ to 13. which are divided into S in accordance with . Each memory 14□ to 14. The gradation data of two adjacent pixel data 9 and 10 are stored one after another in parallel in S, and all 2m pixel data connected to one row line are sent to each of the source drive circuits 131 to 13. Memories 141 to 14.
Set to . After that, source drive circuits 131-13. Analog gradation data is output as pixel data for 2m column lines from 1 to 2m, and one row line each is output by a control signal 16 that specifies the mode of double-definition display or standard-definition display by the gate drive circuit 15. Selection drive or adjacent 2
The rows and lines of the book are selected and driven at the same time, and the above series of operations is sequentially repeated 2n times or n times to display the display on the liquid crystal display. however.

When performing interlaced driving in the case of double-definition display, select and drive every other row line mentioned above, repeat the above series of operations sequentially n times from the 1st line to the 2n-1 line, and then The liquid crystal display is displayed by sequentially repeating n@repeat up to 2n lines (9) by repeating 2 lines in total.

In this configuration, when the externally input analog gradation data is double-definition data, the double-definition analog gradation data is transferred to the two-phase sampling clock 5 as shown in FIG. 3 (1).
The output of the A/D conversion circuit sampled with the earlier clock 5CKI of CKI and 5CK2 is delayed by the phase difference (TJ + x - TJ) between the two-phase locks, and the output is sampled with the slower clock 5CK2. With the same phase as the output of the conversion circuit, the digital gradation data 9°10 is sent to the next stage memories 111-11. On the other hand, in the case of standard definition data, it is converted into two identical digital gradation data 9 and 10 using the same phase sampling clocks 5CKI and 5CK2 as shown in Figure 3 (2). and secondary stage memories 111-11. write to one of the sampling clocks and A/D
Using a conversion circuit, the output of this conversion circuit is converted into the digital gradation data 9.10 and stored in the memories 11□ to 1 of the next stage.
1. write to.

Parts of the pixel display on these double-definition and standard-definition panels are shown in FIGS. 4(1) (a) and (b), respectively, where the S-semi-definition case is compared to the double-definition case.

Both rows and 9 columns are displayed at twice the size.

Here, the subscripts (1, 2, 3,...) in Figure 4A are the third
This corresponds to the subscripts (1, 2, 3, . . . ) of time T in the figure.

Second Embodiment When the liquid crystal gradation display panel 2 has a color display/delta pixel arrangement as shown in FIG.
The embodiment shown in FIG. 1 can be considered as follows.

In the first (!I) embodiment, the configuration from external input analog gradation data 1 to memories 11□ to 11. is R, G.

B. Each externally input analog gradation data has the same configuration 9 A total of three configurations 6 Therefore, in FIG. 1, the number of inputs to each of the source drive circuits 13 □ to 13 is two. However, in this case, each of the three colors R, G, and B requires six workers. A/D when analog gradation data input for R, G, and B colors is double definition and standard definition
Two-phase sampling clock 5CK input to the conversion circuit
1.5CK2 phase and 9th stage memory 11□~1
1. The writing method is the same as in the first embodiment.

Parallel reading is repeated from 8 memories 11□~lls, and 28 pieces of digital gradation data are read out for each color light, a total of 6S pieces of digital gradation data for R, G, and B colors are repeated m/S times. The memory is read out in parallel, and the processing unit 12 processes data such as delta pixel arrangement for 2m pixels of each color, 6m pixels for RGB colors, which are connected to two adjacent row lines i and i+1 (i is an odd number). and source active circuits 13□ to 13. Memory 14□~14g in Figure 2 (2
) is set as +1 (k is an odd number).

After that, in the case of 9x resolution, source drive circuit 13□~1
Analog gradation data is sequentially output from 3s to 3m column lines as pixel data twice, and in synchronization with each output, two adjacent row lines i and i+1 are sequentially selected by the gate drive circuit 15. do. The above series of operations is repeated 2n times to display information on the liquid crystal display. however.

When performing interlaced driving, the above row lines are selectively driven every second row line, and the above series of operations is performed for row lines 1 and 2, row lines 5 and 6, and
...Repeat sequentially n times to row lines 4n-3, 4n-2, then 2nd row lines 3, 49 rows 7, 8...4n
-1,4n is repeated n times 9 In total, the liquid crystal display is displayed by repeating two lines.

In the case of standard definition, two A/D conversion circuits (A/D□, A/D,
) 3.4, convert to the same pixel data of two adjacent column lines or adjacent column lines with only one gap between them.
After processing similar to the double definition case, especially the source drive circuit 1
3□～13. Memory 14□ to 14. Figure 1 (2)
Pixel data is stored in the row lines in a pixel array of +1 (k is an odd number). When sending pixel data of two row lines in such a memory to the row lines, first, the gate drive circuit 15 selectively drives two adjacent row lines i and i+2 at the same time with one row line between them. .

Subsequently, the gate drive circuit 15 drives the row line i.
A total of two row lines i+l and i+3, which are adjacent row lines with only one spacing from the next row line adjacent to the row line, are selectively driven at the same time. A liquid crystal display is displayed while repeating the above series of operations successively n times.

Parts of the pixel display on these double-definition and standard-definition panels are shown in FIGS. 4(2)(a) and (b), respectively. Standard definition compared to double definition.

Both rows and columns are displayed at twice the size.

Here, the subscripts added to each of R, G, and B in FIG. 4 correspond to the subscript of time T in FIG. 3, as in the description of the first embodiment.

Third Embodiment When the liquid crystal gradation display panel 2 has a color display as shown in FIG. 2 (3) and has a stripe pixel arrangement, the panel is 6 m
The embodiment shown in FIG. 1, which is composed of (m is an integer) column lines and 2n (n is an integer) row lines, can be considered as follows.

In the embodiment shown in FIG. 1, the configuration from external input analog gradation data 1 to memories 111 to lls is R and G.

Each of the B externally input analog gradation data has the same configuration, resulting in a total of three configurations. In FIG. 1, source drive circuits 131-13. The number of inputs for each circuit is two, but in this case, the power for each of the three colors R2O and B requires six people. R,G.

The phases of the two-phase sampling clocks 5CKI and 5CK2 that are input to the A/D conversion circuit when the B color analog gradation data input is double definition and standard definition, and the secondary stage memories 11□ to l1g The writing method is the same as in the previous embodiment.

8 memories 111-11 for each color light. 28 pieces of digital gradation data for each read color light, a total of 6S pieces of digital gradation data for R, G, and B colors, are read out in parallel m/3 times from the memory, and one The processing unit 12 performs processing such as stripe pixel arrangement on the data of all 2m pixels of each color, 6m pixels for R, G, and B colors connected to the row lines, and then sends the data to the liquid crystal source drive circuits 13□ to 1.
Memory 14□ to 14 within 3s. are set as shown in the row lines in Figure 2 (3).

After that, in the case of 9x resolution, source drive circuit 13□~1
3. Analog gradation data is output as pixel data to 6m column lines from 1 to 6m, and one row line is selected by the gate drive circuit 15 in synchronization with this output. The above series of operations is repeated 2n times to display information on the liquid crystal display.

However, when performing interlaced driving in the case of double-definition display, every other row line is selectively driven.

Repeat the above series of operations sequentially n times from line 1 to line 2n-1, then repeat n times sequentially from line 2 to line 2n 9
The liquid crystal display is displayed by repeating a total of 2n times.

In the case of standard definition, two A/D conversion circuits (A/D engineering, A/D2
) 3 and 4, the pixel data is converted into the same pixel data of adjacent column lines with a gap of two lines in between.

After processing similar to the case of double definition, the source drive circuit 13,
~13. Pixel data is stored in the memories 141 to 141 in the memory so that the pixels are arranged along the row lines in FIG. 2(3). When sending out the pixel data in the memory to the row lines, two row lines are simultaneously selected by the gate drive circuit 15 in synchronization with the output.

A liquid crystal display is displayed while repeating the above series of operations successively n times.

Parts of the pixel display on these double-definition and standard-definition panels are shown in FIGS. 4(3) (a) and (b), respectively. The standard definition case is compared to the double-definition case.

Both rows and 9 columns are displayed at twice the size.

Here, the subscripts R, G, and H in FIG. 4 are also 1. As in the case of the second embodiment, this corresponds to the subscript of time T in FIG.

In the above embodiments, the source drive circuit and the gate drive circuit are shown arranged on one side of the panel 1, but both or one of the circuits may be arranged and driven on both sides of the panel 1.

Even in the case where the row lines are driven from the gate drive circuits on both sides, if attention is focused only on driving the 9th row line, the result will be as described above regardless of the arrangement of the gate drive circuits.

For example, in the case of the first and third embodiments in a configuration in which gate drive circuits are arranged on both left and right sides of the panel.

A configuration in which every other row line is connected from the left and right gate drive circuits. During 0x definition display, the left and right gate drive circuits drive the row lines alternately, and * during semi-definition display, the left and right gate drive circuits are connected alternately. It is sufficient to simultaneously drive one adjacent row line from the gate drive circuit, and in the case of the second embodiment, in a configuration in which the gate drive circuits are arranged on both the left and right sides of the panel, the row lines are driven from the left and right gate drive circuits. For 0x resolution display, the gate drive circuit on one side sequentially drives two adjacent row lines, and then the gate drive circuit on the opposite side drives two adjacent row lines. Sequentially drive the two row lines to
Either repeat these operations to achieve non-interlaced driving, or sequentially drive two adjacent row lines from the gate drive circuit on one side.

Skip two row lines and sequentially drive two adjacent row lines from the same side gate drive circuit.

Repeat 2 times Next, drive the two adjacent row lines sequentially from the gate drive circuit on the other end, skip the two row lines, and drive the two adjacent row lines from the gate drive circuit on the same side. Drive sequentially and repeat this n times.

It is sufficient to perform interlaced driving that is repeated 2n times in total for one screen display.When displaying in standard definition, two adjacent row lines are sequentially driven, and at this time, the gate driving circuits on both sides are simultaneously driven. It is sufficient to display the screen by repeating n times.

In the example, two A/D conversion circuits are provided for one analog gradation data, and the explanation is made by operating these two A/D conversion circuits for both 9x definition display and standard definition display. In the case of standard definition display, one A/D conversion circuit may be operated to convert the data after A/D conversion into two identical data and write them into the memories 11□ to 116.

In the embodiment, the memories 11□ to 11s and the processing section 12 are shown separated from the source drive circuits 13□ to 13g.

As explained above, from these memories 11□ to lls, the processing unit 1
A configuration in which the inner points up to 2 are located in the source drive circuits 13□ to 13s may also be used.

Because double-definition data is a high-speed signal, the memory 11 is divided into S to perform serial input/parallel output conversion operations.In line with this, the source drive circuit 13 is also divided into S to perform parallel input operation. As described in the example, if a source drive circuit with high-speed input operation is available, the number of divisions S may be reduced depending on the speed, or S may be set to 1.

In the embodiment, the row line selection range II for double-definition display! (Number of scanning lines) and column line display range are each twice that of standard definition display, but the panel itself has twice the configuration, and in the case of double definition display, the number of rows and columns may vary depending on the data. Regarding both or one of the numbers.

It is also possible to display two images using a part of them. In this case, data is written to the source drive circuit by unconditionally converting the data of some pixels from the left and right ends of the 9th row line out of all the pixels connected to the row line to black data, and writing the data of the pixels other than the above. The data is set using externally input analog gradation data, and row line selection from the gate drive circuit is controlled so as not to drive some row lines from the top and bottom ends of the panel, for example.
The number of times the row lines are sequentially driven in the embodiment is different from the number of times the row lines and column lines are actually driven for display. The rest can be considered in exactly the same way.

〔Effect of the invention〕

As explained above, the liquid crystal display drive system of the present invention uses a double-definition display panel, and the source drive system uses two A/D conversion circuits for one analog image signal light, and inputs from the outside. By simply changing the phase of the sampling clock of the A/D conversion circuit in accordance with the definition of the analog image signal, source drive circuits with the same circuit configuration can be used, making it possible to share and integrate nine circuit configurations. become.

Furthermore, depending on whether the display is 9x definition or standard definition, the gate drive circuit selects one row line, two adjacent row lines, or one row line in synchronization with the output operation of the source drive circuit. By gate-selecting whether to select two adjacent row lines with a main gap at the same time, it becomes possible to display both double-definition and standard-definition displays with one type of double-definition display panel, making it possible to use a single type of double-definition display panel. As it expands.

There is no need to prepare both a double-definition display device and a standard-definition display device, and the installation space can be used more effectively.

Furthermore, it goes without saying that in a display to which the present invention is applied, non-interlaced vertical display and interlaced drive display can be switched freely.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 shows a two-dimensional matrix in a multi-gradation liquid crystal display panel.
1) is for monochrome display, (2) is for color display and the RGB color pixel array is a delta pixel array, (3) is for color display and the RGB pixel array is a stripe pixel array, and Figure 3 shows the external display in the present invention. Input analog gradation data 2
The figure shows the phase relationship of two-phase sampling clocks when converted by two A/D conversion circuits. (1) is for double-definition display, and (2) is for standard-definition display. FIGS. 4(1), (2), and (3) show part of the pixel display on the panel when the present invention is applied to display an image on the panel, and (1), (2) in FIG. , (3) respectively. Explanation of symbols> 1...External input analog gradation data 2...Display panel 3.4...A/D conversion circuit 5.6...Sampling clock 7...Delay circuit 8... Selection circuit 11.1
4...Memory 9.10...Digital gradation data 12...Processing section 13...Source drive circuit 15...Gate drive circuit 16...Control signal ('+
) and 3) Figure 3 m + m + 11114201 + 31044 m + 5J
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L,,,,L=,,L,,,1. ．． 1. ,L-,,
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Claims (1)

[Claims] 1. Double-definition display using a double-definition liquid crystal display panel in which row lines (gate lines) and column lines (source lines) are each twice as large as those of a standard-definition liquid crystal display panel. This is a liquid crystal display drive method that displays images by switching between standard definition display and column line drive using source drive circuits, which prepares two A/D conversion circuits for each image data and converts the input analog gradation data. When is a double-definition image signal, data processing is performed by shifting the phase of the sampling clock applied to the above two A/D conversion circuits by 180 degrees, and when it is a standard definition image signal, data processing is performed by shifting the phase of the sampling clock applied to the above two A/D conversion circuits. Data processing is performed with the sampling clocks applied to the two A/D conversion circuits being in phase, or data processing is performed with the output of one of the A/D conversion circuits being made into two identical data, and based on such data, the column line In addition to driving the gate drive circuit and outputting analog gradation data to the pixels, the row line drive by the gate drive circuit is synchronized with the output operation from the source drive circuit. Repeat the sequential selection of row lines in a book, or repeat the selection of one row line and skip over one row line in interlaced driving, or the sequential selection of two adjacent row lines and the next two row lines. By repeatedly performing the row line skipping operation, or by repeatedly selecting two adjacent row lines when displaying in standard definition, or simultaneously selecting two adjacent row lines with only one spacing between them. , a liquid crystal display driving system characterized in that an image is displayed on the display panel.