CN113178423A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN113178423A
CN113178423A CN202010725127.5A CN202010725127A CN113178423A CN 113178423 A CN113178423 A CN 113178423A CN 202010725127 A CN202010725127 A CN 202010725127A CN 113178423 A CN113178423 A CN 113178423A
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layer
semiconductor device
adhesive layer
substrate
manufacturing
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CN113178423B (zh
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筑山慧至
高久悟
菅生悠树
天野彩那
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Kioxia Corp
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Kioxia Corp
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Abstract

本发明涉及一种半导体装置及其制造方法。本实施方式的半导体装置具备：衬底、第1粘接层、第1半导体芯片、及第2粘接层。第1粘接层设置在衬底的第1面上方，包含分子量不同的多种树脂及填料。第1半导体芯片设置在第1粘接层的上方。第2粘接层设置在衬底与第1粘接层之间的至少一部分的第1区域，包含多种树脂中分子量小于其它种类的树脂的至少1种树脂、及浓度低于第1粘接层的填料。

Description

半导体装置及其制造方法
相关申请的引用
本申请是基于2020年01月27日提出申请的先前的日本专利申请第2020-011131号的优先权的权益，且谋求该权益，通过引用使其全部内容包含于本文。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
半导体装置的封装步骤中，已知有使用DAF(Die Attach Film，芯片粘接膜)积层半导体芯片的方法。一般来说，以在布线衬底表面填充DAF的方式设定工艺的条件。
但是，难以将布线衬底与DAF之间的间隙完全填埋，有时会在封装体内产生空腔。该空腔内的水分(水蒸气)例如在安装回焊及吸湿回焊可靠性试验等中因高温而膨胀。因此，在空腔较大的情况下，空腔内成为高压，封装体有可能破损。
发明内容
提供一种能够抑制热处理时的破损的半导体装置及其制造方法。
本实施方式的半导体装置具备：衬底、第1粘接层、第1半导体芯片、及第2粘接层。第1粘接层设置在衬底的第1面上方，包含分子量不同的多种树脂及填料。第1半导体芯片设置在第1粘接层的上方。第2粘接层设置在衬底与第1粘接层之间的至少一部分的第1区域，包含多种树脂中分子量小于其它种类的树脂的至少1种树脂、及浓度低于第1粘接层的填料。
根据所述构成，可提供一种能够抑制热处理时的破损的半导体装置及其制造方法。
附图说明
图1是表示第1实施方式的半导体装置的构成的剖视图。
图2是表示第1实施方式的粘接层的放大图。
图3是表示第1实施方式的半导体装置的制造方法的流程图。
图4是表示安装初期的制造中途的半导体装置的一例的剖视图。
图5是表示从安装中到固化后为止的制造中途的半导体装置的一例的剖视图。
图6是表示第2实施方式的半导体装置的构成的剖视图。
图7是表示第2实施方式的半导体装置的制造方法的流程图。
图8是表示安装初期的制造中途的半导体装置的一例的剖视图。
图9是表示从安装中到固化后为止的制造中途的半导体装置的一例的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不限定本发明。以下实施方式中，半导体衬底的上下方向表示将设置半导体元件的面设为上时的相对方向，有时与按照重力加速度的上下方向不同。附图为示意性或概念性，各部分的比率等未必与实际相同。在说明书及附图中，对与上文中关于已出附图叙述过的要素相同的要素标注相同符号，适当省略详细说明。
(第1实施方式)
图1是表示第1实施方式的半导体装置1的构成的剖视图。半导体装置1具备：布线衬底11、作为第1层的粘接层21、半导体芯片CH1、导线W1、作为第2层的粘接层22、树脂23、及金属凸块B。
此外，在图1所示的例子中，半导体芯片CH1经由粘接层21在纵向上以2段积层。纵向是相对于布线衬底11的衬底上表面F1大致垂直的方向。但是，半导体芯片CH1的积层数并不限于2段，可任意变更。
布线衬底11具有布线111、及树脂层112、113。布线衬底11例如为印刷衬底等衬底。此外，布线衬底11只要能够经由导线W1与半导体芯片CH1连接即可，衬底的种类并无限定。布线衬底11例如可为硅衬底等。
布线111将布线衬底11的衬底上表面F1上的电极垫(未图示)与布线衬底11的衬底下表面上的金属凸块B电连接。布线111例如可使用铜或钨等导电性金属。布线111具有所积层的多个布线层L1～L3。布线层L1～L3通过层间的树脂层得以绝缘。另外，布线层L1～L3例如可通过导孔等而使一部分电连接。
树脂层112例如可使用阻焊剂等绝缘材料。树脂层113包含补强部113a，强度及刚性高于树脂层112。树脂层113例如为预浸体。补强部113a例如为玻璃布等纤维状补强材。
另外，在布线衬底11设置着凹部114。此外，关于凹部114的详细情况，将参照图2在下文进行说明。
粘接层21设置在布线衬底11的衬底上表面F1上方。另外，粘接层21包含分子量不同的多种树脂及填料。粘接层21例如为膜状树脂(DAF(Die Attach Film))。另外，填料例如为二氧化硅填料。
另外，更详细来说，粘接层21包含丙烯酸系橡胶及聚酰亚胺的至少一种、以及环氧树脂及酚树脂的至少一种。丙烯酸系橡胶及聚酰亚胺的分子量大于环氧树脂及酚树脂的分子量。丙烯酸系橡胶的分子量例如为40万～100万。聚酰亚胺的分子量例如为5万～30万，更优选7万～20万。环氧树脂及酚树脂的分子量例如为1000～3000。另外，粘接层21的调配比率例如以可获得未硬化状态下的流动性及弹性模量等所需特性的方式设定。关于粘接层21的调配比率，例如填料为约50重量％、丙烯酸系橡胶为约10重量％～约25重量％、环氧树脂为约5重量％～约20重量％、酚树脂为约5重量％～约20重量％。此外，丙烯酸系橡胶的一部分可为聚酰亚胺。
半导体芯片CH1设置在粘接层21的上方。更详细来说，半导体芯片CH1通过粘接层21而粘接到布线衬底11上及其它半导体芯片CH1上。半导体芯片CH1的积层数例如可为1段～16段的范围。另外，半导体芯片CH1如图1所示呈阶梯状错开积层。由此，抑制半导体芯片CH1的电极垫(未图示)上重叠其它半导体芯片CH1，使导线W1能够连接在各半导体芯片CH1的电极垫。半导体芯片CH1例如可为分别具有相同构成的存储器芯片。存储器芯片例如为NAND((Not AND，与非))芯片。半导体芯片CH1的积层数是根据所需的存储器容量来设定的。
导线W1将布线衬底11与半导体芯片CH1电连接。导线W1例如可使用金等导电性金属。此外，导线W1例如也可使用银或铜等。
粘接层22设置在布线衬底11与粘接层21之间的至少一部分区域。更详细来说，如图1所示，粘接层22设置在布线衬底11的凹部114与粘接层21之间的区域。如其后所说明，粘接层22以填埋布线衬底11与粘接层21之间的间隙(空腔)的方式形成。空腔因吸湿回焊及安装回焊等高温处理而成为高压。因此，通过将空腔进行填埋(变小)，能够抑制热处理时的压力所导致的封装体破损。粘接层22在制造中途从粘接层21渗出，从粘接层21分离。此外，关于粘接层22的形成的详细情况，将参照图3～图5在下文进行说明。
图2是第1实施方式的粘接层22的放大图。图2也是图1的虚线框D的放大图。另外，图2中省略补强部113a。
凹部114例如为回蚀开口。回蚀开口是在利用镀覆设置布线111的情况下用以将多余的引线切断或去除的开口部。回蚀开口容易成为较深的凹部，容易在与粘接层21之间产生较大间隙。
粘接层21的一部分在凹部114中向下方延伸。另外，粘接层21与粘接层22的边界的形状向下凸起。其原因在于，当将半导体芯片CH1粘接到布线衬底11时，粘接层21被来自上方的压力压抵。因此，粘接层22的最大高度在衬底上表面F1的树脂层112的高度以下。另外，粘接层22的最大高度也在凹部114的开口缘的高度以下。
另外，粘接层22包含多种树脂中分子量小于其它种类的树脂的至少1种树脂、及浓度低于粘接层21的填料。也就是说，粘接层21内所含的树脂中分子量较小的一部分树脂作为粘接层22分离。此外，“浓度低的填料”也包括粘接层22中不存在填料(0重量％)的情况。
另外，更详细来说，粘接层22包含环氧树脂及酚树脂的至少一种。也就是说，粘接层22中，包含分子量较小的树脂，与此相对，不含像丙烯酸系橡胶及聚酰亚胺那样分子量较大的树脂。因此，丙烯酸系橡胶及聚酰亚胺的至少一种残留在粘接层21内。另外，环氧树脂及酚树脂相比于丙烯酸系橡胶不易水解。因此，通过使粘接层22中包含环氧树脂或酚树脂，例如能够抑制因布线111中的金属迁移所导致的树脂的绝缘性能劣化。另外，能够提升高温高湿偏压试验下的评估。
如图1所示，树脂23将半导体芯片CH1、粘接层21及导线W1在衬底上表面F1上进行密封。由此，树脂23保护半导体芯片CH1、粘接层21及导线W1免受外部冲击或外部气体的影响。树脂23例如可使用环氧树脂等。另外，树脂23包含填料。
金属凸块B设置在与衬底上表面F1为相反侧的布线衬底11的衬底下表面，与布线层L3的一部分连接。金属凸块B是为了将半导体装置1电连接到外部的安装衬底(未图示)等而设置。金属凸块B例如可使用焊料等导电性金属。在该情况下，金属凸块B例如为焊料球。
接下来，对半导体装置1的制造方法进行说明。此外，以下对晶圆步骤后的组装步骤进行说明。
图3是表示第1实施方式的半导体装置1的制造方法的流程图。此外，以下，粘接层21有时也称为DAF。
首先，在晶圆表面(上表面)贴附保护带(S10)。接着，以晶圆厚度成为所需厚度的方式对晶圆背面(下表面)进行研磨(S20)。接着，在晶圆下表面贴附具有DAF的切晶带，剥离保护带(S30)。接着，利用刀片将晶圆切断为各半导体芯片CH1(S40)。也就是说，以与布线衬底11的衬底上表面F1对向的方式，在半导体芯片CH1(晶圆)的芯片下表面F2(晶圆下表面)设置包含分子量不同的多种树脂及填料的膜状粘接层21。
接着，使半导体芯片CH1粘接到布线衬底11上(安装)(S50)。也就是说，经由粘接层21将半导体芯片CH1设置在衬底上表面F1上。作为安装时的条件，例如温度约70℃～约150℃，压力约0.1MPa～约0.5MPa，更优选约0.2MPa～约0.4MPa。此外，DAF例如在约70℃～约150℃下，弹性模量大幅减少，变得柔软。接着，进行DAF的硬化(固化)及释气的排出(S60)。也就是说，通过对粘接层21加压，而在布线衬底11与粘接层21之间的间隙内形成粘接层22。作为固化时的条件，例如温度为约100℃～约200℃，压力为约0.5MPa以上，更优选约0.9MPa以上。压力越高，则粘接层21的填充性越提升，因此更优选压力较高。另外，作为固化时的条件，处理时间为约30分钟～约2小时。
另外，更详细来说，通过半导体芯片CH1向布线衬底11的设置、及粘接层21的硬化处理的至少一种来形成粘接层22。也就是说，安装时及固化时均可通过对粘接层21加压来形成粘接层22。此外，固化时相比于安装时会施加更高的压力，因此有时容易形成粘接层22。此外，关于从安装到固化的粘接层22的详细情况，将参照图4及图5在下文进行说明。
接着，利用导线W1使半导体芯片CH1上的电极与布线衬底11连接(S70)。在尚未安装所有半导体芯片CH1的情况下(S80的否(NO))，再次执行步骤S50～S70。此外，在第2次以后的步骤S50中，使半导体芯片CH1粘接到已安装的其它半导体芯片CH1上。因此，将所需芯片数的半导体芯片CH1积层到布线衬底11上。在已安装所有半导体芯片CH1的情况下(S80的是(YES))，在模具内配置布线衬底11并填充树脂23，将金属凸块B搭载于布线衬底11的衬底下表面的电极(S90)。
图4是表示安装初期的制造中途的半导体装置1的构成的一例的剖视图。图5是表示从安装中到固化后为止的制造中途的半导体装置1的构成的一例的剖视图。
如图4所示，在安装初期，凹部114内存在间隙24。其原因在于，难以利用粘接层21将凹部114内完全填充。如图4及图5所示，在安装中或固化中，通过对粘接层21加压，而在布线衬底11的凹部114与粘接层21之间的间隙24内形成粘接层22。利用安装中及固化中的热使分子量较小的树脂(例如环氧树脂及酚树脂)的流动性变高。分子量较小的树脂因压力而从粘接层21渗出，作为粘接层22分离。另外，在凹部114为回蚀开口的情况下，间隙24的面积例如为约100μm见方～约200μm见方。此外，间隙24的形状可为数100μm×约5mm等任意形状。另外，间隙24的深度例如为约10μm。
另外，分子量不同的多种树脂中，分子量的最小值相对于最大值的比率优选为规定值以下。规定值例如为10分之1以下，更优选1000分之1～100分之1。粘接层21内的树脂的分子量的差越大，分子量较小的树脂越容易从粘接层21渗出而分离。例如，丙烯酸系橡胶因为分子量较大，且相连的分子形状的分子彼此的交联较强，所以维持膜状。因此，丙烯酸系橡胶的各分子不易移动。例如，环氧树脂因为分子量小于丙烯酸系橡胶，所以容易穿过丙烯酸系橡胶的网状分子的间隙。因此，环氧树脂能够通过压力从粘接层21分离。另外，填料的粒径例如为数μm程度，较大。进而，填料通过硅烷偶联等而与粘接层21内的树脂较强地结合。因此，填料容易挂在丙烯酸系橡胶的网状分子上，不易穿过分子的间隙。
另外，分离的树脂的分子量越小，越能更容易地填埋布线衬底11的表面。
如上所述，根据第1实施方式，粘接层21包含分子量不同的多种树脂及填料。另外，粘接层22设置在布线衬底11与粘接层21之间的至少一部分区域，包含多种树脂中分子量较小的至少1种树脂、及浓度低于粘接层21的填料。
通常，在安装时及固化时，以在布线衬底11表面填充粘接层21的方式设定工艺的条件。但是，难以将布线衬底11与粘接层21之间的间隙完全填埋，有时封装体内会产生空腔。该空腔内的水分(水蒸气)例如在安装回焊或吸湿回焊可靠性试验等中因高温而膨胀。安装回焊是例如通过约260℃以上的高温使金属凸块B熔解，而用于将半导体装置1与安装衬底电连接的热处理。另外，吸湿回焊可靠性试验是在刻意地使封装体中含有水分的状态下进行热处理的可靠性试验。因此，在空腔较大的情况下，空腔内成为高压，有因高压水蒸气的爆炸而导致封装体破损的可能性。此外，封装体的破损例如也包含树脂23与半导体芯片CH1的剥离、及树脂23的龟裂产生等。
在第1实施方式中，通过使分子量较小的树脂分离而在空腔内形成粘接层21，从而能使空腔减小、或填埋空腔。结果，能够抑制热处理时的封装体的破损，且能够提高可靠性。此外，因树脂的分离而产生的粘接层21内的空腔的影响较小。
另外，在第1实施方式中，利用安装时及固化时的至少任一者填埋间隙24。因此，能够不增加工艺数且将间隙24填埋(变小)。另外，粘接层22的最大高度在衬底上表面F1的树脂层112的高度以下。
此外，粘接层21内的一部分树脂也可具有羧基及环氧基等反应性官能基。也就是说，也可使用包含预先被赋予反应性官能基的丙烯酸系橡胶的粘接层21。由此，容易进行丙烯酸系橡胶的交联反应，粘接层21内的树脂的分子量的差变大。结果，粘接层22容易从粘接层21分离，能够对间隙24进一步填埋(变得更小)。
(第2实施方式)图6是表示第2实施方式的半导体装置1的构成的剖视图。第2实施方式在设置半导体芯片CH2的方面与第1实施方式不同。
半导体装置1还具备半导体芯片CH2及导线W2。
半导体芯片CH2设置在布线衬底11与粘接层21之间。半导体芯片CH2设置在半导体芯片CH1下方，由粘接层21被覆。半导体芯片CH2例如为控制器芯片。在该情况下，半导体芯片CH2控制半导体芯片CH1的动作。
导线W2将布线衬底11与半导体芯片CH2电连接。布线衬底11还具备与导线W2连接的接合垫115。因此，更详细来说，导线W2将接合垫115与半导体芯片CH2电连接。另外，在导线W2的上方设置着粘接层21。导线W2例如可使用金等导电性金属。此外，导线W2例如也可使用银或铜等。
因为导线W2成为阻力，所以粘接层21不易进入到导线W2的下方。因此，在导线W2的下方，与凹部114同样地容易产生较大间隙。此外，粘接层21的一部分也可存在于导线W2的下方。其原因在于，例如有粘接层21的一部分从沿图8的纸面垂直方向设置着多个的导线W2一端的拱进入的可能性。此外，所进入的一部分粘接层21的位置并不限于图8所示的例子，可为导线W2与该导线W2下方的布线衬底11及半导体芯片CH2的至少一个之间的任一位置。
粘接层22设置在导线W2与该导线W2下方的布线衬底11、粘接层21及半导体芯片CH2的至少一个之间的区域。如其后所说明，粘接层22以填埋导线W2下方的间隙的方式形成。因此，粘接层22的最大高度在导线W2的高度以下。
第2实施方式的半导体装置1的其它构成与第1实施方式的半导体装置1的对应构成相同，因此省略其详细说明。此外，在图6所示的例子中，与第1实施方式中的图1同样地示出凹部114及凹部114内的粘接层22。但是，第2实施方式并不限于设置凹部114的情况。
图7是表示第2实施方式的半导体装置1的制造方法的流程图。此外，步骤S10～S40与第1实施方式中的图3的流程图相同。
在步骤S40后，将半导体芯片CH2设置在布线衬底11上(S41)。半导体芯片CH2例如通过粘接层(未图示)粘接到布线衬底11上。接着，利用导线W2使布线衬底11与半导体芯片CH2连接(S42)。也就是说，在将半导体芯片CH1设置在衬底上表面F1上之前，在衬底上表面F1上设置半导体芯片CH2，利用导线W2使布线衬底11与半导体芯片CH2电连接。之后，执行步骤S50。
步骤S50～S90与第1实施方式中的图3的流程图相同。此外，步骤S41、S42并不限于图7所示的顺序。例如步骤S41、S42也可与步骤S10～S40同步执行。
图8是表示安装初期的制造中途的半导体装置1的构成的一例的剖视图。图9是表示从安装中到固化后为止的制造中途的半导体装置1的构成的一例的剖视图。
如图8所示，在安装初期，在导线W2的下方存在间隙25。如图8及图9所示，在安装中或固化中，通过对粘接层21加压，而在导线W2与该导线W2下方的布线衬底11、粘接层21及半导体芯片CH2的至少一个之间的间隙25内形成粘接层22。
第2实施方式的半导体装置1可获得与第1实施方式相同的效果。
关于其它实施方式此外，在第1、第2实施方式中，粘接层21可不使用膜，而使用液状或膏状的粘接层21。关于此时的制造方法，首先，利用灌注、网版印刷、喷墨等各种方法将液状或膏状的粘接层21涂布到布线衬底11的衬底上表面F1上方。之后，经由粘接层21在布线衬底11安装半导体芯片CH1并进行固化。也就是说，在衬底上表面F1设置粘接层21，并经由粘接层21，以与衬底上表面F1对向的方式将半导体芯片CH1的芯片下表面F2设置在衬底上表面F1上。即使如此使用液状或膏状的粘接层21，也能使粘接层22分离至间隙24、25，能获得与第1、第2实施方式相同的效果。
对本发明的若干实施方式进行了说明，但这些实施方式是作为例子提出的，并非意图限定发明的范围。这些实施方式可通过其它各种方式来实施，可在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含于发明的范围或主旨，且同样地包含于权利要求书所记载的发明及其均等范围内。

Claims (19)

1.一种半导体装置，具备：衬底；
第1层，设置在所述衬底的第1面上方，包含分子量不同的多种树脂及填料；
第1半导体芯片，设置在所述第1层的上方；以及
第2层，设置在所述衬底与所述第1层之间的至少一部分的第1区域，包含多种所述树脂中分子量小于其它种类的所述树脂的至少1种所述树脂、及浓度低于所述第1层的所述填料。
2.根据权利要求1所述的半导体装置，其中
所述第2层设置在所述衬底的凹部与所述第1层之间的第2区域。
3.根据权利要求1所述的半导体装置，其还具备：第2半导体芯片，设置在所述衬底与所述第1层之间；及
导线，将所述衬底与所述第2半导体芯片电连接；且
所述第2层设置在所述导线与该导线下方的所述衬底、所述第1层及所述第2半导体芯片的至少一个之间的第3区域。
4.根据权利要求3所述的半导体装置，其中所述第3区域包含由所述导线形成且由所述第2层填充的间隙。
5.根据权利要求1所述的半导体装置，其中分子量不同的多种所述树脂中，分子量的最小值相对于最大值的比率为规定值以下。
6.根据权利要求5所述的半导体装置，其中所述规定值为1/10以下。
7.根据权利要求6所述的半导体装置，其中所述规定值在1/100～1/1000之间。
8.根据权利要求1所述的半导体装置，其中所述第1层包含丙烯酸系橡胶及聚酰亚胺的至少一种、以及环氧树脂及酚树脂的至少一种，且
所述第2层包含环氧树脂及酚树脂的至少一种。
9.根据权利要求1所述的半导体装置，其中所述填料包含二氧化硅。
10.根据权利要求2所述的半导体装置，其中所述第2层的上表面低于所述凹部的上端。
11.根据权利要求2所述的半导体装置，其中所述第2层在所述凹部内为凸状。
12.一种半导体装置的制造方法，包括：在衬底的第1面设置包含分子量不同的多种树脂及填料的第1层；
经由所述第1层，以与所述第1面对向的方式将第1半导体芯片的第2面设置在所述第1面上；
通过对所述第1层加压，而在所述衬底与所述第1层之间的第1间隙内形成第2树脂层，所述第2树脂层包含多种所述树脂中分子量小于其它种类的所述树脂的至少1种所述树脂、及浓度低于所述第1层的所述填料。
13.根据权利要求12所述的半导体装置的制造方法，其包括：贴膜而形成所述第1层。
14.根据权利要求12所述的半导体装置的制造方法，其包括：由液体形成所述第1层。
15.根据权利要求12所述的半导体装置的制造方法，其包括：于0.1～0.5Mpa以上使所述第2层固化。
16.根据权利要求12所述的半导体装置的制造方法，其包括：于0.5Mpa以上使所述第2层固化。
17.根据权利要求12所述的半导体装置的制造方法，其包括：由构成所述第1层的一部分物质形成所述第2层。
18.根据权利要求12所述的半导体装置的制造方法，其包括：于固化或安装中形成所述第2层。
19.根据权利要求12所述的半导体装置的制造方法，其包括：由膏形成所述第1层。
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