CN113130473B - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

Info

Publication number
CN113130473B
CN113130473B CN202010076846.9A CN202010076846A CN113130473B CN 113130473 B CN113130473 B CN 113130473B CN 202010076846 A CN202010076846 A CN 202010076846A CN 113130473 B CN113130473 B CN 113130473B
Authority
CN
China
Prior art keywords
chip
spacer
circuit board
package structure
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010076846.9A
Other languages
English (en)
Other versions
CN113130473A (zh
Inventor
苏志彦
林俊德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Publication of CN113130473A publication Critical patent/CN113130473A/zh
Application granted granted Critical
Publication of CN113130473B publication Critical patent/CN113130473B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种芯片封装结构，包括电路板、第一芯片、间隔件以及第二芯片。第一芯片设置于电路板上，间隔件设置于电路板上，其中间隔件包括间隔部以及至少一穿孔结构，且穿孔结构贯穿间隔部。第二芯片设置于第一芯片与间隔件上，且第二芯片通过间隔件电连接到电路板。

Description

芯片封装结构
技术领域
本发明有关于一种芯片封装结构，特别是有关于一种具有多芯片堆叠的芯片封装结构。
背景技术
随着电子产品的微小化与多功能化，多芯片的封装结构在许多电子产品越来越常见，其系将两个或两个以上的芯片封装在单一封装结构中，以缩减整体体积。常见的多芯片封装结构系将两个以上的芯片彼此并排地设置于同一基板上，但并排设置芯片将使得封装结构的面积随着芯片数量的增加而加大。为解决此问题，目前发展出使用堆叠的方式来配置芯片。然而，堆叠芯片的方式仍存在缺点，例如垂直堆叠芯片会造成封装结构的厚度过高，以及堆叠在最上方的芯片电连接到电路板的电阻会变大，以致于增加功率消耗。
发明内容
根据本发明的一实施例，提供一种芯片封装结构，其包括电路板、第一芯片、间隔件以及第二芯片。第一芯片设置于电路板上，间隔件设置于电路板上，其中间隔件包括间隔部以及至少一第一穿孔结构，且第一穿孔结构贯穿间隔部。第二芯片设置于第一芯片与间隔件上，且第二芯片通过间隔件电连接到电路板。
通过具有穿孔结构的间隔件，可有效地焊线的长度，以降低焊线的电阻值。藉此，可提升芯片封装结构的效能或降低芯片封装结构的功率消耗，还可降低芯片封装结构的整体宽度。
附图说明
图1绘示本发明第一实施例的芯片封装结构的俯视示意图。
图2绘示沿着图1的剖线A-A’的剖视示意图。
图3绘示本发明第二实施例的芯片封装结构的剖视示意图。图4绘示本发明第三实施例的芯片封装结构的剖视示意图。图5绘示本发明第四实施例的芯片封装结构的剖视示意图。图6绘示本发明第五实施例的芯片封装结构的剖视示意图。图7绘示本发明第六实施例的芯片封装结构的剖视示意图。
附图标记：
1，2，3，4，5，6：芯片封装结构
12：电路板
12a，14a：上接垫
12b，14b：下接垫
12c：上保护层
12d：下保护层
12e：内连线
12f：绝缘层
12S，14S，161S，562S1，163S：上表面
14：间隔件
14P：间隔部
161：第一芯片
161a，162a，163a：输入/输出接垫
161b，50：导电凸块
162，462，562：第二芯片
163：第三芯片
181：第一焊线
182：第二焊线
183：第三焊线
201，202，542，642：连接件
22：底部填充胶
24，26，32：粘着层
28：封装胶体
30：导电球
34，36，44，46：介电层
38，48：导电层
562a：接垫
562D：元件
562M：芯片主体
562S2：下表面
D1，D2：方向
L1，L2：长度
T：厚度
TH1：第一穿孔结构
TH2：第二穿孔结构
VD：俯视方向
W1，W2，W3：宽度
具体实施方式
通过参考以下的详细描述并同时结合图式可以理解本发明，须注意的是，为了使读者能容易了解及图式的简洁，本发明的图式只绘出芯片封装结构的至少一部分，且图式中的特定元件并非依照实际比例绘图。此外，图式中各元件的数量及尺寸仅作为示意，并非用来限制本发明的范围。
本发明通篇说明书与所附的权利要求范围中会使用某些术语来指称特定元件。本领域技术人员应理解，电子设备制造商可能会以不同的名称来指称相同的元件。本文并不意在区分那些功能相同但名称不同的元件。在下文说明书与权利要求范围中，“含有”与“包括”等词为开放式词语，因此其应被解释为“含有但不限定为…”之意。
应了解到，当元件或膜层被称为在另一个元件或膜层“上”或“连接到”另一个元件或膜层时，它可以直接在此另一元件或膜层上或直接连接到此另一元件或层，或者两者之间存在有插入的元件或膜层。相反地，当元件被称为“直接”在另一个元件或膜层“上”或“直接连接到”另一个元件或膜层时，两者之间不存在有插入的元件或膜层。
须知悉的是，以下所举实施例可以在不脱离本发明的精神下，将数个不同实施例中的技术特征进行替换、重组、混合以完成其他实施例。
图1绘示本发明第一实施例的芯片封装结构的俯视示意图，图2绘示沿着图1的剖线A-A’的剖视示意图。芯片封装结构1包括电路板12以及设置于电路板12上的至少一间隔件14与至少二芯片(例如第一芯片161与第二芯片162)，其中一个芯片(例如第一芯片161)设置在间隔件14与另一个芯片(例如第二芯片162)上，且设置在间隔件14上的芯片可通过间隔件14电连接电路板12，藉此缩小水平方向上的芯片封装结构1的宽度W1及/或降低芯片封装结构1的厚度T。水平方向可例如为平行于电路板12上表面12S的方向D1、方向D2或平行于电路板12上表面12S且不同于方向D1与方向D2的方向。
电路板12可例如为印刷电路板(printed circuit board)或其他类型的电路板，但不限于此。在一些实施例中，电路板12可例如单层线路或多层线路的电路板。举例来说，图2所示的电路板12可包括多个上接垫12a、多个下接垫12b、上保护层12c、下保护层12d、多个内连线12e以及绝缘层12f，上保护层12c设置于绝缘层12f上并可具有开口曝露出上接垫12a，下保护层12d设置于绝缘层12f下并可具有开口曝露出下接垫12b，且内连线12e贯穿绝缘层12f，使得上接垫12a可通过对应的内连线12e电连接到对应的下接垫12b。电路板12的上表面12S可例如为上保护层12c的外表面，但不限于此。本发明的电路板12不以此为限，且可依据实际需求调整电路板12的结构。
如图1与图2所示，第一芯片161可例如通过芯片倒装焊方式与电路板12焊接并电连接。举例来说，第一芯片161可包括导电凸块161b，设置于第一芯片161的下表面，用以将第一芯片161焊接在电路板12的上接垫12a上。在一些实施例中，第一芯片161与电路板12的电连接方式不限为芯片倒装焊焊接，也可通过打线(wire bonding)方式达成。在一些实施例中，第一芯片161与电路板12之间例如还可设置有底部填充胶(underfill)22，用以增强第一芯片161与电路板12的焊接可靠度。在本实施例中，第二芯片162下可另设置有粘着层24，用以将第二芯片162粘贴于第一芯片161与间隔件14上。并且，第二芯片162可通过打线方式与间隔件14电连接。
本发明的芯片可例如为特殊应用集成电路(application specific integratedcircuit，ASIC)芯片、存储器芯片或其他类型的芯片，但不限于此。存储器芯片可例如为快闪存储器(flash memory)芯片或其他类型的存储器芯片，但不限于此。不同的芯片可具有相同或不相同的功能。芯片也可被称为半导体芯片、芯片或集成电路芯片。在一实施例中，第一芯片161与第二芯片162可具有不同的功能。举例来说，第二芯片162可为存储器芯片，而第一芯片161可为ASIC芯片，用于控制或驱动存储器芯片。在此情况下，第一芯片161可具有较多的输入/输出接垫161a，因此可通过芯片倒装焊方式与电路板12焊接，而第二芯片162可具有较少的输入/输出接垫162a，因此第二芯片162可通过打线方式与间隔件14电连接。举例来说，第一芯片161的输入/输出接垫161a的数量可多于第二芯片162的输入/输出接垫162a的数量，但不限于此。在一些实施例中，第一芯片161与第二芯片162也可具有相同功能，例如皆为存储器芯片。在此情况下，第一芯片161可通过打线方式与电路板12电连接，且第二芯片162可通过打线方式与间隔件14电连接。
间隔件14与第一芯片161并排设置于电路板12上，使得间隔件14与第一芯片161可用于支撑第二芯片162。举例来说，间隔件14可通过粘着层32粘贴在电路板12上。在本实施例中，间隔件14可包括间隔部14P以及至少一第一穿孔结构TH1，且第一穿孔结构TH1贯穿间隔部14P。间隔部14P可例如包括半导体材料、高分子材料或其他合适的支撑材料，但不限于此。半导体材料可例如包括硅，但不限于此。第一穿孔结构TH1可包括导电材料。在图2所示的实施例中，间隔件14可包括多个第一穿孔结构TH1，垂直贯穿间隔部14P，且间隔件14可另包括至少一个上接垫14a以及多个下接垫14b，上接垫14a设置于间隔部14P上并与对应的第一穿孔结构TH1连接，下接垫14b设置于间隔部14P下并与对应的第一穿孔结构TH1连接，使得上接垫14a可通过对应的第一穿孔结构TH1电连接到对应的下接垫14b。下接垫14b可电连接至对应的电路板12的上接垫12a。举例来说，第一穿孔结构TH1垂直贯穿间隔部14P，使得上接垫14a与下接垫14b在俯视方向VD上彼此重叠，且间隔件14可另包括连接件201，用以将下接垫14b电连接至电路板12的上接垫12a。在一实施例中，电路板12的上接垫12a与间隔件14的下接垫14b在俯视方向VD上可不重叠，因此电路板12的至少一上接垫12a可与至少一第一穿孔结构TH1在芯片封装结构1的俯视方向VD上不重叠，但不以此为限。在图2所示的实施例中，连接件201可例如为单一导电层。导电层可例如包括金属或其他适合的导电材料。虽然图2中的连接件201与下接垫14b未连接，但实际上连接件201可在其他地方与下接垫14b连接，以将彼此对应的下接垫14b与上接垫12a电连接。下接垫14b与连接件201可由相同的导电层所形成或由不同的导电层所形成。所述导电层可例如包括金属或其他合适的导电材料，但不限于此。在一些实施例中，连接件201可例如包括重布线层，但不限于此。需说明的是，为了降低设置在间隔件14与第一芯片161上的第二芯片162的倾斜，间隔件14的间隔部14P的上表面14S的高度与第一芯片161的上表面161S可实质上位于同一水平面，举例来说，间隔部14P的上表面14S与电路板12的上表面12S之间的间距以及第一芯片161的上表面161S与电路板12的上表面12S之间的间距可大致上相同。
如图2所示，在一实施例中，芯片封装结构1可包括至少一条第一焊线181，从第二芯片162(例如第二芯片162的输入/输出接垫162a)延伸到间隔件14(例如间隔件14的上接垫14a)，使得第二芯片162可通过第一焊线181电连接到间隔件14的上接垫14a、第一穿孔结构TH1与下接垫14b，进而通过间隔件14电连接到电路板12。在一实施例中，第一焊线181的一端可直接与第二芯片162的输入/输出接垫162a焊接，另一端可直接与间隔件14的上接垫14a焊接，但本发明不限于此。值得一提的是，由于间隔件14的上接垫14a的高度高于电路板12的上接垫12a的高度，因此第一焊线181的长度可缩短，以降低第一焊线181的电阻值。并且，间隔件14的第一穿孔结构TH1的电阻值可小于第一焊线181的电阻值，因此第二芯片162电连接到电路板12的电阻值可有效地降低，进而提升芯片封装结构1的效能或降低芯片封装结构1的功率消耗。此外，由于第一焊线181投影在水平方向上的长度L1可缩短，因此可缩减芯片封装结构1在水平方向上的整体宽度W1。
在一些实施例中，如图1与图2所示，芯片封装结构1还可包括第三芯片163、另一粘着层26以及至少一条第二焊线182。需说明的是，虽然图2同时显示第一焊线181与第二焊线182，但第一焊线181与第二焊线182可位于不同的剖面上。第三芯片163通过粘着层26粘贴在第二芯片162上，且第二焊线182从第三芯片163的输入/输出接垫163a(第三芯片163的上表面)延伸到间隔件14的上接垫14a，用以将第三芯片163电连接到间隔件14中的第一穿孔结构TH1，因此第三芯片163可通过第二焊线182与间隔件14电连接到电路板12。在一实施例中，第二焊线182的一端可直接与第三芯片163的输入/输出接垫163a焊接，另一端可直接与间隔件14对应的上接垫14a焊接，但本发明不限于此。需注意的是，第三芯片163与第二芯片162可分别电连接至不同且彼此绝缘的上接垫14a，以传送不同的信号。在一些实施例中，当第三芯片163的其中一输入/输出接垫163a与第二芯片162的其中一输入/输出接垫162a传送相同的信号时，所述输入/输出接垫163a与对应的输入/输出接垫162a可电连接至相同或彼此电连接的上接垫14a。值得说明的是，第二焊线182的长度可因间隔件14的设置而缩短，进而降低第二焊线182的电阻值，以提升芯片封装结构1的效能或降低芯片封装结构1的功率消耗。并且，由于间隔件14的设置降低了第二焊线182两端的高低落差，因此可降低第二焊线182高于第三芯片163的部分的高度，还可缩短第二焊线182投影在水平方向上的长度L2，进而缩减芯片封装结构1在水平方向上的整体宽度W1。在一些实施例中，第三芯片163可与第二芯片162具有相同的功能，例如皆为存储器芯片。粘着层24、26、32可例如分别包括芯片粘着膜(die attach film，DAF)或其他适合的绝缘粘着材料。
在一些实施例中，芯片封装结构1可包括多个间隔件14、多个第二芯片162以及多个第三芯片163。在图1与图2所示的芯片封装结构1的实施例中，间隔件14的数量、第二芯片162的数量以及第三芯片163的数量以两个为例，但不限于此。在一些实施例中，间隔件14可分别设置于第一芯片161的两侧，举例来说，间隔件14的第一穿孔结构TH1可位于堆叠芯片的外侧，但不限于此。第二芯片162除了设置于对应的间隔件14上之外可堆叠在同一第一芯片161上，且第三芯片163可分别设置在对应的第二芯片162上，使得第二芯片162与第三芯片163皆可通过间隔件14电连接到电路板12，以缩减第一焊线181与第二焊线182的电阻值。在一些实施例中，每个间隔件14可具有类似或相同的结构，每个第二芯片162可具有类似或相同的功能，每个第三芯片163可具有类似或相同的功能，但不以此为限。
在一些实施例中，芯片封装结构1还可包括封装胶体28，设置于第一芯片161、第二芯片162、第三芯片163、第一焊线181、第二焊线182与间隔件14上，并将其密封在电路板12上，因此可用以保护芯片、焊线与间隔件14。在一些实施例中，芯片封装结构1还可包括多个导电球30，分别设置在电路板12的下接垫12b上，使芯片封装结构1可进一步设置并电连接至其他元件、载板或电路板上。
本发明的芯片封装结构并不以上述实施例为限，且以下将进一步描述本揭露的其他实施例。为方便比较各实施例与简化说明，下文中将使用相同标号标注相同元件，且下文将详述不同实施例之间的差异，并不再对相同部分作赘述。
请参考图3，其绘示本发明第二实施例的芯片封装结构的剖视示意图。本实施例的芯片封装结构2与上述实施例的差异在于，连接件202可包括重布线层，形成于间隔部14P的下表面与下接垫14b上。在图3的实施例中，重布线层可包括两层介电层34、36以及一层导电层38，导电层38设置于介电层34、36之间，且介电层34可具有开口，使导电层38可通过介电层34的开口与下接垫14b电连接。另外，介电层36可具有开口，对应电路板12的上接垫12a，使得导电层38可通过导电凸块40电连接到电路板12。在一些实施例中，重布线层可包括三层或更多的介电层以及两层或更多的导电层。
请参考图4，其绘示本发明第三实施例的芯片封装结构的剖视示意图。本实施例的芯片封装结构3与上述实施例的差异在于，芯片封装结构3可另包括至少一第三焊线183，从第一芯片161的上表面161S延伸到电路板12的其中一上接垫12a，使第一芯片161可通过第三焊线183电连接至电路板12。举例来说，第一芯片161可具有较少的接垫，因此接垫设置在第一芯片161的上表面161S。第一芯片161与第二芯片162可例如具有相同功能，例如均为存储器芯片。在一些实施例中，第三焊线183的数量不限如图3所示，且可为多条。需说明的是，用于将第二芯片162粘贴在第一芯片161上的粘着层24的厚度需大于第三焊线183位于第一芯片161的上表面161S上的部分的高度，以降低第二芯片162的设置对第三焊线183的损坏。在一些实施例中，芯片封装结构3可具有图2或图3所示的实施例或两者的组合的内容。
请参考图5，其绘示本发明第四实施例的芯片封装结构的剖视示意图。本实施例的芯片封装结构4与上述实施例的差异在于，在水平方向(例如方向D1)上，第二芯片462的宽度W2大于第一芯片161的宽度W3。在一些实施例中，第二芯片462的面积可大于第一芯片161的面积，但不限于此。在图5的实施例中，芯片封装结构4可仅包括单一第二芯片462，设置在第一芯片161与两间隔件14上，且第三芯片163设置在第二芯片462上，但本发明不以此为限。在一些实施例中，第二芯片462的范围可依据实际需求调整，而堆叠在第一芯片161与至少一间隔件14上。在一些实施例中，芯片封装结构4可具有图2、图3或图4所示的实施例或两者的组合的内容。
请参考图6，其绘示本发明第五实施例的芯片封装结构的剖视示意图。本实施例的芯片封装结构5与上述实施例的差异在于，至少一个第二芯片562可另包括芯片主体562M、至少一第二穿孔结构TH2以及接垫562a，第二穿孔结构TH2贯穿芯片主体562M从芯片主体562M的上表面562S1延伸到芯片主体562M的下表面562S2，且第二焊线182系从第三芯片163的上表面163S延伸到第二芯片562的接垫562a。在一实施例中，第二穿孔结构TH2在俯视方向VD上可与接垫562a重叠。此外，第二芯片562还可包括连接件542，设置于芯片主体562M的下表面562S2上，并与第二穿孔结构TH2电连接。通过连接件542，电连接第二焊线182的第二芯片562的接垫562a可电连接到间隔件14的上接垫14a。在一实施例中，间隔件14与第二穿孔结构TH2电连接的第一穿孔结构TH1可在俯视方向VD上可与第二芯片562重叠，使得连接件542可通过间隔件14的上接垫14a与第一穿孔结构TH1电连接。在一实施例中，彼此电连接的第一穿孔结构TH1与第二穿孔结构TH2在俯视方向VD上可重叠或不重叠。需注意的是，接垫562a与芯片主体562M中的元件562D是电性绝缘，也就是说，接垫562a不同于第二芯片562中用于元件562D的信号输入或输出的输入/输出接垫162a(如图1所示)。并且，第二芯片562的输入/输出接垫162a(如图1所示)仍可通过第一焊线181电连接到间隔件14。在图6的实施例中，连接件542可例如为单层导电层，但不限于此。所述导电层可例如包括金属或其他合适的导电材料，但不限于此。在一些实施例中，芯片封装结构5可仅包括单一个第三芯片163，通过粘着层26设置于至少两个第二芯片562上。在一些实施例中，芯片封装结构5可具有图2、图3、图4或图5所示的实施例或上述实施例的任两者的组合的内容。
值得说明的是，通过第二穿孔结构TH2的设置，第二焊线182仅需从第三芯片163的上表面163S延伸到第二芯片562的接垫562a，而不需延伸到位于第二芯片562下的间隔件14，因此可降低第二焊线182的长度。例如，缩短第二焊线182投影在水平方向(例如方向D1)的长度L2，或降低第二焊线182位于第三芯片163的上表面163S上的部分的高度。因此，可提升芯片封装结构5的效能或降低芯片封装结构5的功率消耗，还可降低芯片封装结构5的整体宽度W1。
请参考图7，其绘示本发明第六实施例的芯片封装结构的剖视示意图。本实施例的芯片封装结构6与上述实施例的差异在于，第二芯片562的连接件642可包括重布线层，形成于芯片主体562M的下表面562S2上。在图7的实施例中，重布线层可包括两层介电层44、46以及一层导电层48，导电层48设置于介电层44、46之间，且介电层44可具有开口，使导电层48可通过介电层44的开口与第二穿孔结构TH2电连接。另外，介电层46可具有开口，对应间隔件14的上接垫14a，使得导电层48可通过导电凸块50电连接到间隔件14，进而电连接到电路板12。在一些实施例中，重布线层可包括三层或更多的介电层以及两层或更多的导电层。所述导电层可例如包括金属或其他合适的导电材料，但不限于此。在一些实施例中，芯片封装结构6可具有图2、图3、图4或图5所示的实施例或上述实施例的任两者的组合的内容。
综合上述，在本发明的芯片封装结构中，通过具有穿孔结构的间隔件及/或具有穿孔结构的芯片，可有效地焊线的长度，以降低焊线的电阻值。藉此，可提升芯片封装结构的效能或降低芯片封装结构的功率消耗，还可降低芯片封装结构的整体宽度。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种芯片封装结构，其特征在于，包括：
一电路板；
一第一芯片，设置于该电路板上；
一间隔件，设置于该电路板上，其中该间隔件包括一间隔部以及至少一第一穿孔结构，且所述至少一第一穿孔结构贯穿该间隔部；以及
一第二芯片，设置于该第一芯片与该间隔件上，且该第二芯片通过该间隔件电连接到该电路板；
另包括一第三芯片以及至少一第二焊线，该第三芯片设置于该第二芯片上，且该至少一第二焊线连接该第三芯片的上表面；该第二芯片包括一芯片主体以及至少一第二穿孔结构，从该芯片主体的上表面延伸到该芯片主体的下表面，且该第三芯片通过该至少一第二焊线与该至少一第二穿孔结构电连接该间隔件。
2.如权利要求1所述的芯片封装结构，其特征在于，另包括至少一第一焊线，从该第二芯片的上表面延伸到该间隔件，且该第二芯片通过该至少一第一焊线电连接至该至少一第一穿孔结构。
3.如权利要求1所述的芯片封装结构，其特征在于，该第一芯片以芯片倒装焊方式与该电路板焊接。
4.如权利要求2所述的芯片封装结构，其特征在于，该第一芯片与该第二芯片具有不同功能。
5.如权利要求1所述的芯片封装结构，其特征在于，该间隔件另包括一连接件，设置于该间隔部与该电路板之间。
6.如权利要求1所述的芯片封装结构，其特征在于，该第二芯片的面积大于该第一芯片的面积。
7.如权利要求1所述的芯片封装结构，其特征在于，该电路板包括至少一上接垫，电连接至该至少一第一穿孔结构，且该至少一上接垫与该至少一第一穿孔结构在该芯片封装结构的俯视方向上不重叠。
8.如权利要求1所述的芯片封装结构，其特征在于，该至少一第二焊线从该第三芯片的上表面延伸到该间隔件，且该第三芯片通过该至少一第二焊线电连接该间隔件。
9.如权利要求1所述的芯片封装结构，其特征在于，另包括至少一第三焊线，从该第一芯片的上表面延伸到该电路板，且该第一芯片通过该至少一第三焊线电连接至该电路板。
10.如权利要求9所述的芯片封装结构，其特征在于，该第一芯片与该第二芯片具有相同功能。
CN202010076846.9A 2019-12-31 2020-01-23 芯片封装结构 Active CN113130473B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW108148495A TWI711131B (zh) 2019-12-31 2019-12-31 晶片封裝結構
TW108148495 2019-12-31

Publications (2)

Publication Number Publication Date
CN113130473A CN113130473A (zh) 2021-07-16
CN113130473B true CN113130473B (zh) 2024-04-05

Family

ID=74202542

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010076846.9A Active CN113130473B (zh) 2019-12-31 2020-01-23 芯片封装结构

Country Status (3)

Country Link
US (1) US11133291B2 (zh)
CN (1) CN113130473B (zh)
TW (1) TWI711131B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI778560B (zh) 2021-03-30 2022-09-21 力成科技股份有限公司 封裝結構及其製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102867821A (zh) * 2007-09-12 2013-01-09 瑞萨电子株式会社 半导体器件
CN109727948A (zh) * 2018-12-24 2019-05-07 西安飞芯电子科技有限公司 一种封装结构以及芯片安装单元

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100674907B1 (ko) * 2003-11-26 2007-01-26 삼성전자주식회사 고신뢰성을 갖는 스택형 반도체 패키지
DE10360708B4 (de) * 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
US7613010B2 (en) * 2004-02-02 2009-11-03 Panasonic Corporation Stereoscopic electronic circuit device, and relay board and relay frame used therein
KR100665217B1 (ko) * 2005-07-05 2007-01-09 삼성전기주식회사 반도체 멀티칩 패키지
TWI312569B (en) * 2006-10-12 2009-07-21 Siliconware Precision Industries Co Ltd Semiconductor package on which a semiconductor device is stacked and production method thereof
US7872356B2 (en) * 2007-05-16 2011-01-18 Qualcomm Incorporated Die stacking system and method
US20090051043A1 (en) * 2007-08-21 2009-02-26 Spansion Llc Die stacking in multi-die stacks using die support mechanisms
US8700874B2 (en) * 2010-09-24 2014-04-15 Telefonaktiebolaget L M Ericsson (Publ) Digital counter segmented into short and long access time memory
KR101774938B1 (ko) * 2011-08-31 2017-09-06 삼성전자 주식회사 지지대를 갖는 반도체 패키지 및 그 형성 방법
US9067342B2 (en) * 2012-09-26 2015-06-30 Intel Corporation Mold chase for integrated circuit package assembly and associated techniques and configurations
KR102247916B1 (ko) * 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
US20170040266A1 (en) * 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
US9679873B2 (en) * 2015-06-18 2017-06-13 Qualcomm Incorporated Low profile integrated circuit (IC) package comprising a plurality of dies
KR20170075125A (ko) * 2015-12-22 2017-07-03 에스케이하이닉스 주식회사 반도체 패키지 및 제조 방법
US9773757B2 (en) * 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US10199318B2 (en) * 2016-05-19 2019-02-05 Mediatek Inc. Semiconductor package assembly
US10727208B2 (en) * 2016-09-29 2020-07-28 Intel Corporation Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same
US10944379B2 (en) * 2016-12-14 2021-03-09 Qualcomm Incorporated Hybrid passive-on-glass (POG) acoustic filter
US10461022B2 (en) * 2017-08-21 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
FR3076659B1 (fr) * 2018-01-05 2020-07-17 Stmicroelectronics (Grenoble 2) Sas Entretoise isolante de reprise de contacts
WO2019144129A1 (en) * 2018-01-22 2019-07-25 InSyte Systems, Inc. Chip-scale sensing device for low density material
US10276511B1 (en) * 2018-04-27 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package and manufacturing method thereof
US11043730B2 (en) * 2018-05-14 2021-06-22 Mediatek Inc. Fan-out package structure with integrated antenna
US11270953B2 (en) * 2018-08-31 2022-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with shielding structure
US20200343184A1 (en) * 2019-04-23 2020-10-29 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US11380653B2 (en) * 2019-08-27 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102867821A (zh) * 2007-09-12 2013-01-09 瑞萨电子株式会社 半导体器件
CN109727948A (zh) * 2018-12-24 2019-05-07 西安飞芯电子科技有限公司 一种封装结构以及芯片安装单元

Also Published As

Publication number Publication date
US20210202444A1 (en) 2021-07-01
TWI711131B (zh) 2020-11-21
TW202127593A (zh) 2021-07-16
US11133291B2 (en) 2021-09-28
CN113130473A (zh) 2021-07-16

Similar Documents

Publication Publication Date Title
US7446420B1 (en) Through silicon via chip stack package capable of facilitating chip selection during device operation
US8873245B2 (en) Embedded chip-on-chip package and package-on-package comprising same
US7939924B2 (en) Stack type ball grid array package and method for manufacturing the same
US8384200B2 (en) Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies
US20080029884A1 (en) Multichip device and method for producing a multichip device
KR101478247B1 (ko) 반도체 패키지 및 이를 이용한 멀티 칩 패키지
US20230163099A1 (en) Semiconductor package
US7652361B1 (en) Land patterns for a semiconductor stacking structure and method therefor
KR20100088514A (ko) 반도체 패키지
US7659620B2 (en) Integrated circuit package employing a flexible substrate
KR100621547B1 (ko) 멀티칩 패키지
KR101123803B1 (ko) 스택 패키지
JP2007134426A (ja) マルチチップモジュール
US7030489B2 (en) Multi-chip module having bonding wires and method of fabricating the same
JP4538830B2 (ja) 半導体装置
CN113130473B (zh) 芯片封装结构
KR101219484B1 (ko) 반도체 칩 모듈 및 이를 갖는 반도체 패키지 및 패키지 모듈
US8237291B2 (en) Stack package
KR100808582B1 (ko) 칩 적층 패키지
KR20110055985A (ko) 스택 패키지
EP3182449A1 (en) Semiconductor package
US8441129B2 (en) Semiconductor device
KR20080067891A (ko) 멀티 칩 패키지
US20230422521A1 (en) Stack-type semiconductor package
KR102499034B1 (ko) 다수의 반도체 칩을 갖는 반도체 패키지

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant