CN113128148B - Trigger signal synchronization system and method based on delay chain and semiconductor test equipment - Google Patents
Trigger signal synchronization system and method based on delay chain and semiconductor test equipment Download PDFInfo
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- CN113128148B CN113128148B CN202110405600.6A CN202110405600A CN113128148B CN 113128148 B CN113128148 B CN 113128148B CN 202110405600 A CN202110405600 A CN 202110405600A CN 113128148 B CN113128148 B CN 113128148B
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- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
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- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G06F30/32—Circuit design at the digital level
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Abstract
The invention discloses a trigger signal synchronization system and method based on a delay chain in ATE (automatic test equipment) semiconductor test equipment and the semiconductor test equipment, and belongs to the field of integrated circuit test in the microelectronic industry. The programmable logic device is arranged on the back plate, and the interconnection synchronous trigger signals of all the service boards in communication connection with the back plate are wired on the programmable logic device, so that the problem of numerous and complicated wiring of the back plate is solved. The trigger signal is sent and received by the input signal delay unit and the output signal delay unit for delay processing, so that the problem of accurate synchronism of the trigger signals of all service boards sent to other service boards is solved, and meanwhile, the trigger signal is easier to be synchronously calibrated.
Description
Technical Field
The invention relates to the field of integrated circuit testing in the microelectronic industry, in particular to a trigger signal synchronization system and method based on a delay chain in ATE semiconductor testing equipment and the semiconductor testing equipment.
Background
The back plate is a kind of PCB (printed circuit board). Particularly, the backplane is a main board for bearing a daughter board or a line card, and can realize a user-defined function. The primary function of the backplane is to "carry" the circuit board and distribute power, signal, etc. functions to each daughter board in order to obtain the appropriate electrical connections and signal transmission. The service board and the backboard work together, communication connection is carried out between the service board and the backboard, and the backboard can guide the whole system to run smoothly logically.
The problem of high wiring difficulty exists in the existing back plate wiring design due to the fact that the number of wires is large. Taking 16 business boards as an example, 16 business boards are plugged on the backplane. To interconnect 16 traffic boards two by two, 16 × 2 (bidirectional) × 2 (differential signal) =1024 lines are required. The backboard sends out a trigger signal, then the service boards are synchronously triggered, and at the moment, if the service boards are synchronously triggered, the wiring on the backboard needs to be equal in length. However, since the wires are laid on the backplane, if the wires need to be of equal length, complicated wire design is required under the condition that the area of the backplane is limited, which causes great difficulty for technicians to implement equal length of wires. Especially, when the number of the service boards needing synchronous triggering is increased, the back board only can enlarge the area, so that the cost is increased, and the difficulty of equal length of wiring is greatly increased.
In addition, in the field of chip testing, extremely high testing precision is required, and synchronous trigger errors between service boards are limited to microsecond level. The traditional back plate wiring design is difficult to meet the requirement of high-precision synchronous triggering in the test field.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a trigger signal synchronization system and method based on a delay chain in ATE semiconductor test equipment and the semiconductor test equipment. The trigger signal transmitted by the service board is processed through the programmable logic device, and the problem that the trigger signal is synchronous to a plurality of service boards is solved. The synchronization of the trigger signal to the service board is realized through the cooperation of the programmable logic device in the backboard and the semiconductor test board.
In order to achieve the purpose, the invention adopts the following technical scheme:
a trigger signal synchronization system based on a delay chain comprises a backboard and a plurality of service boards;
the back plate is provided with a programmable logic device which is in communication connection with the service plate and is used for receiving, processing and distributing a trigger signal with the service plate;
a plurality of circuit module groups are arranged in the programmable logic device, and each circuit module group is used for corresponding to each service board one by one and carrying out communication connection;
each circuit module group comprises an input signal delay unit, an output signal delay unit, a trigger selection circuit module and a logic OR circuit module, wherein:
the trigger selection circuit module is in signal connection with the corresponding service board and is used for receiving a trigger signal sent by the service board and fanning out the trigger signal to the correspondingly selected logic OR circuit module;
the logic or circuit module is in signal connection with the service board, and is used for receiving all the trigger signals, performing logic or processing on the trigger signals and sending the processed trigger signals to the corresponding service board;
the input signal delay unit is connected with the trigger selection circuit modules and used for adjusting the time for the trigger selection circuit modules to receive the trigger signals so as to realize that the trigger selection circuit modules receive the trigger signals at the same time;
the output signal delay unit is connected with the logic or circuit and is used for adjusting the time for sending the trigger signal by the logic or circuit module so as to realize that a plurality of service boards receive the trigger signal at the same time;
each trigger selection circuit module is in communication connection with any one of the logic or circuit modules.
In a specific embodiment, the input signal delay unit includes an input delay subunit (IDELAY) and an input delay carry chain, and an output terminal of the input delay subunit (IDELAY) is connected to an input terminal of the input delay carry chain;
the delay adjustable precision of the input delay subunit (IDELAY) is higher than that of the input delay carry chain;
the output signal delay unit comprises an output delay subunit (ODELAY) and an output delay carry chain, and the output end of the output delay carry chain is connected with the input end of the output delay subunit (ODELAY);
the delay adjustable precision of the output delay subunit (ODELAY) is higher than that of the output delay carry chain.
In a specific embodiment, the input delay carry chain includes a delay selector and a plurality of delay units connected in series, output taps of the plurality of delay units are respectively connected to the delay selector, and the delay selector is configured to select an appropriate number of the delay units according to a preset carry chain delay configuration;
the output delay carry chain and the input delay carry chain have the same structure.
In a specific embodiment, the trigger selection circuit module comprises an input synchronous trigger, a plurality of logic AND circuits and a plurality of fan-out triggers;
the input end of each logic and circuit is respectively connected with the input synchronous trigger and a preset fan-out selection signal source, and the output end of each logic and circuit is connected with one fan-out trigger;
the input signal delay unit is connected with the input synchronous trigger;
the logic or circuit module comprises a logic or circuit and an output synchronous trigger, wherein the input end of the output synchronous trigger is connected with the output end of the logic or circuit, and the output end of the output synchronous trigger is connected with the output signal delay unit.
In a particular embodiment, the communication connection includes:
a differential transmission connection line for differentially transmitting the trigger signal between the service board and the circuit module group;
the communication protocol connecting circuit is used for transmitting the configuration signal of the trigger selection circuit module corresponding to the service board and comprises a UART protocol connecting circuit, an IIC protocol connecting circuit or an SPI protocol connecting circuit;
wherein the differential transmission connection line comprises:
the sending signal connecting circuit is used for transmitting the triggering signal sent by the service board to the triggering selection circuit module for fan-out;
and the receiving signal connecting line is used for sending the trigger signal processed by the logic or circuit module to the service board.
In a specific embodiment, the service board is a semiconductor test board, a wafer test board or a package test board;
the programmable logic device is a CPLD or an FPGA.
A triggering signal synchronization method based on a delay chain is suitable for a system comprising a backboard and a plurality of service boards, wherein a programmable logic device is arranged on the backboard, a plurality of circuit module groups are arranged in the programmable logic device, and the circuit module groups correspond to the service boards one by one and transmit triggering signals;
the method comprises the following steps:
establishing communication connection between the backboard and each service board through a programmable logic device;
the time for receiving the trigger signal by the circuit module groups is adjusted through the input signal delay unit, so that the circuit module groups can simultaneously receive the trigger signal and meet the establishment and retention time of the input trigger signal latch;
receiving a trigger signal sent by the service board through a trigger selection circuit module, and fanning out the trigger signal to the correspondingly selected logic or circuit module;
receiving all the trigger signals through a logic or circuit module, carrying out logic or processing, and sending the processed trigger signals to the corresponding service boards;
the time for the logic or circuit module to send the trigger signal is adjusted through the output signal delay unit, so that the plurality of service boards receive the trigger signal at the same time and the establishment and retention time of the trigger signal latches on the service boards is met.
In a specific embodiment, the input signal delay unit includes an input delay subunit (IDELAY) and an input delay carry chain, and the output signal delay unit includes an output delay subunit (ODELAY) and an output delay carry chain;
the "adjusting, by the input signal delay unit, the time for receiving the trigger signal by the plurality of circuit module groups to achieve that the plurality of circuit module groups receive the trigger signal at the same time" specifically includes:
an input delay subunit (IDELAY) carries out first time delay processing on the trigger signal according to a preset reference clock and a preset delay configuration;
the input delay carry chain carries out second time delay processing on the trigger signal according to the preset carry chain delay configuration;
after two time delay treatments, a plurality of circuit module groups receive the trigger signal at the same time;
the "adjusting, by the output signal delay unit, the time for the logic or circuit module to send the trigger signal to realize that a plurality of the service boards receive the trigger signal at the same time" specifically includes:
the output delay carry chain carries out first time delay processing on the trigger signal according to the delay configuration of a preset carry chain;
an output delay subunit (ODELAY) carries out second time delay processing on the trigger signal according to a preset reference clock and a preset delay configuration;
after two time delay treatments, a plurality of service boards receive the trigger signal at the same time.
In a specific embodiment, the method further comprises the following steps: acquiring a first time difference of a plurality of circuit module groups for receiving trigger signals and a second time difference of each service board for receiving the trigger signals through a calibration board;
each input delay unit respectively adjusts the delay time according to the first time difference, so that the time for each input synchronous trigger to receive each trigger signal is the same, the establishment and holding time of each input trigger is met, and the circuit module groups can simultaneously receive the trigger signals;
and the output delay unit adjusts the time for the logic or circuit module to send the trigger signal according to the second time difference, so that the plurality of service boards receive the trigger signal at the same time and the establishment and retention time of the trigger signal latches on each service board is met.
A semiconductor test device based on the trigger signal synchronization method based on the delay chain comprises the following steps:
the test backboard is provided with a programmable logic device;
the semiconductor test boards are in communication connection with the programmable logic devices;
the programmable logic device is used for receiving, processing and distributing trigger signals with the semiconductor test board.
The invention has the beneficial effects that:
according to the trigger signal synchronization system based on the delay chain in the ATE semiconductor test equipment, the programmable logic device is arranged on the back plate, all wiring in communication connection with the back plate is realized on the programmable logic device, the wiring on the traditional back plate is equivalently replaced, the problem that the wiring of the back plate is numerous and complicated is solved, the equal length precision is high, and meanwhile, the trigger signal is easy to synchronize. By arranging the signal delay unit, corresponding signal delay is carried out based on the signal difference, each service board can be ensured to simultaneously send and receive the trigger signal, and the signal synchronization precision can be controlled at the picosecond (ps) level, thereby completely meeting the test requirement.
The invention discloses a trigger signal synchronization method based on a delay chain in ATE semiconductor test equipment, which processes a trigger signal transmitted by a service board through a programmable logic device and solves the problem that the trigger signal is synchronized to the service board.
According to the semiconductor test equipment provided by the invention, through the matching of the test backboard and the semiconductor test board, the test backboard is provided with the programmable logic device, the equal-length layout wiring can be carried out in the programmable logic device, and the test backboard is in communication connection with the semiconductor test board, so that the problem of numerous and complicated wiring on the backboard is solved, the phenomenon that the whole backboard cannot be used due to the fact that the traditional backboard is prone to error caused by too many wirings is avoided, meanwhile, the synchronous test of the trigger signals is optimized, whether the signals are synchronous can be tested only at the output end of the programmable logic device, the complicated detection caused by the fact that the trigger signals of each line need to be synchronously detected on the traditional backboard wiring is avoided, the detection time is greatly shortened, and the efficiency is higher.
Drawings
Fig. 1 is a schematic structural diagram of a trigger signal synchronization system based on a delay chain according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a specific structure of the trigger signal synchronization system based on the delay chain in FIG. 1;
FIG. 3 is a schematic diagram illustrating a connection between a test backplane and a semiconductor test board of the chip test apparatus according to the embodiment;
FIG. 4 is a schematic diagram of a conventional backplane and service board wiring connection;
FIG. 5 is a block diagram of a trigger selection circuit;
FIG. 6 is a block diagram of a logic or circuit block;
FIG. 7 is a circuit configuration diagram of an input signal delay unit;
FIG. 8 is a circuit diagram of an output signal delay unit;
fig. 9 is a flowchart of a trigger signal synchronization method based on a delay chain.
In the figure:
1. a back plate; 2. a service board; 3. a programmable logic device; 4. a circuit module group; 5. a trigger selection circuit module; 6. a logic or circuit module; 41. an input signal delay unit; 42. an output signal delay unit; 7. a differential transmission connection line; 71. a receiving signal connection line 72 and a transmitting signal connection line; 8. a communication protocol connection circuit; 9. testing the back plate; 10. a semiconductor test board.
Detailed Description
The technical scheme of the invention is further explained by the specific embodiment in combination with the attached figures 1-9 of the specification.
Example 1
As shown in fig. 1, the present embodiment provides a system for synchronizing trigger signals based on delay chains in ATE semiconductor test equipment, including:
a backboard 1 and a plurality of service boards 2; the service board 2 is used to implement preset functions.
The back plate 1 is provided with a programmable logic device 3, the programmable logic device 3 is in communication connection with the service plate 2 and is used for receiving, processing and distributing the trigger signal with the service plate 2, the service plate 2 transmits the trigger signal to the programmable logic device 3, and the programmable logic device 3 receives, processes and distributes the trigger signal transmitted by the service plate 2.
In the programmable logic device 3, routing and transmission of signals can be realized by programming. Specifically, equal-length layout and wiring can be performed through an EDA tool to obtain a netlist circuit, and then the netlist circuit is mapped onto the programmable logic device 3 through a downloading tool to achieve a circuit with a preset target, so that wiring on the traditional backboard 1 is equivalent, and the method is more convenient and faster than wiring on the traditional backboard 1. Because the internal wiring of the programmable logic device 3 is different from the traditional arrangement of the entity circuit on the back plate, the programmable logic device is not influenced by the area of the traditional back plate 1, the programmable logic device 3 is easier to be wired with equal length, the trigger signal can be synchronously sent to each service board 2, and each service board 2 can work simultaneously.
With reference to fig. 1 and fig. 2, the programmable logic device 3 is programmed with a plurality of circuit module groups 4, and the circuit module groups 4 are in one-to-one correspondence with the service boards 2 and are in communication connection. Each circuit module group 4 corresponds to a service board 2, so that each service board 2 can transmit a trigger signal to the programmable logic device 3.
Specifically, each circuit module group 4 includes a trigger selection circuit module 5, a logic or circuit module 6, an input signal delay unit 41, and an output signal delay unit 42.
The trigger selection circuit module 5 is in signal connection with the corresponding service board 2 and is used for receiving the trigger signal sent by the service board 2 and fanning out the trigger signal to the correspondingly selected logic or circuit module 6; specific fan-out selection circuit structure fig. 5 shows that the trigger selection circuit module comprises an input synchronous trigger, a plurality of logic and circuits and a plurality of fan-out triggers. The fan-out selection circuit selected by the present embodiment includes an input synchronization flip-flop and a plurality of fan-out flip-flops. Specifically, the D pin of the input synchronous flip-flop is connected to the input signal delay unit 41, the clk pin is connected to the synchronous clock, the output signal of the Q pin and the fan-out selection signal correspond to the input of the and circuit, and the output of the and circuit is connected to the fan-out flip-flop.
The input end of each logic and circuit is respectively connected with an input synchronous trigger and a preset fan-out selection signal source, and the output end of each logic and circuit is connected with a fan-out trigger;
a logic or circuit module 6, which is in signal connection with the service board 2, and is used for receiving all the trigger signals, performing logic or processing, and then sending to the corresponding service board 2; the specific logic or circuit structure diagram is shown in figure 6 of the specification. The logic or circuit is connected with a D pin of the output trigger, a CLK pin of the output trigger is connected with the synchronous clock, and a Q pin of the output trigger is connected with the output driver. Each trigger selection circuit block 5 is also communicatively connected to any one of the or logic circuit blocks 6. The logic or circuit module 6 comprises a logic or circuit and an output synchronous trigger, wherein the input end of the output synchronous trigger is connected with the output end of the logic or circuit, and the output end of the output synchronous trigger is connected with the output signal delay unit.
The input signal delay unit 41 is connected to the trigger selection circuit module 5, and the input signal delay unit 41 is connected to the input synchronous trigger and is configured to adjust a time for the trigger selection circuit module 5 to receive the trigger signal. As shown in fig. 5 in the specification, the input signal delay unit 41 is connected to the trigger selection circuit module 5, specifically to the D port of the input synchronous flip-flop. In the present application, the trigger signal is transmitted in the form of a differential signal, and the trigger signal enters the input signal delay unit 41 after being buffered by the differential input buffer. The input signal delay unit 41 adjusts the time for receiving the trigger signal by the trigger selection circuit modules 5, so that the trigger selection circuit modules 5 receive the trigger signal at the same time, and further, the trigger signal of the service board is received by the circuit modules at the same time, the establishment and retention time of the input trigger signal latch is met, and the problem that the trigger signal is not received synchronously due to different distances between the service boards and the back board is solved.
And the output signal delay unit 42 is connected with the logic or circuit, and is used for adjusting the time when the logic or circuit module 6 sends the trigger signal after logic or processing. As shown in fig. 6, the input terminal of the output signal delay unit 42 is connected to the Q pin of the output synchronous flip-flop, and the D pin of the output synchronous flip-flop is connected to a logic or circuit. The output signal delay unit 42 adjusts the time for the logic or circuit module 6 to send the trigger signal, so that a plurality of service boards receive the trigger signal at the same time, the establishment and retention time of the trigger signal latches on each service board is met, and the problem that the trigger signal is received asynchronously by the service boards due to different distances between the service boards and the back board is solved.
In this embodiment, the input signal delay unit 41 includes an input delay subunit (IDELAY) and an input delay carry chain, and both the input delay subunit (IDELAY) and the input delay carry chain have a delay function, as shown in fig. 7 in the specification, an output end of the input delay subunit (IDELAY) is connected to an input end of the input delay carry chain. The output signal delay unit 42 includes an output delay sub-unit (ODELAY) and an output delay carry chain, both of which have a delay function, as shown in fig. 8, and an input end of the output delay sub-unit (ODELAY) is connected to an output end of the output delay carry chain.
The input delay subunit (IDELAY) is IDELAY, wherein the DIN pin receives the trigger signal, the CLK pin is connected to the reference clock, and the CFG pin is connected to the delay configuration. The time delay configuration can be preset, the circuit module group with the slowest time for receiving the trigger signal is taken as a reference according to the time difference of receiving the trigger signal by each circuit module group, and the corresponding time delay configuration is set according to the time difference of other circuit module groups and the circuit module group, so that the plurality of circuit module groups can receive the trigger signal at the same time. The adjustable delay precision of the input delay subunit (IDELAY) is higher than that of the input delay carry chain.
The output delay subunit (ODELAY) is ODELAY, wherein the DIN pin is connected to the delay selector, the CLK pin is connected to the reference clock, and the CFG pin is connected to the delay configuration. The time delay configuration can be preset, the time difference of receiving the trigger signal by each service board is used as a reference, the service board with the slowest time for receiving the trigger signal is used, and the corresponding time delay configuration is set according to the time difference between other service boards and the service board, so that the plurality of service boards can receive the trigger signal at the same time. The delay adjustable precision of the output delay subunit (ODELAY) is higher than that of the output delay carry chain.
The input delay carry chain comprises a plurality of delay units and a delay selector, wherein the delay units are connected in series, and output taps of the delay units are respectively connected to the delay selector. The delay selector selects a proper number of delay units to form a delay carry chain with a proper length according to the delay configuration of the preset carry chain. The structure of the output delay carry chain is the same as that of the input delay carry chain, and the specific structure is shown in the attached figures 7 and 8 in the specification.
IDELAY and ODELAY are used as small-particle delay tools, and the delay adjustable precision can be controlled to be a few picoseconds. The delay-carry chain large-particle delay tool has delay adjustable precision slightly lower than IDELAY and ODELAY and delay adjustable precision of tens of picoseconds. The particle delay tool is increased through the small particle delay tool, so that the signal synchronization precision between the service boards can be controlled to be picosecond level, and the requirement of test precision is met.
Fig. 4 provides a schematic diagram of wiring connection between a conventional backplane and a service board, which is compared with fig. 4 and 2. In the conventional wiring connection manner shown in fig. 4, each service board is connected to the backplane through wiring, and each service board must be connected to the backplane 1 through differential lines and transmission lines, which are not less than the number of the service boards 2, and each line must have equal length to achieve selective fan-out and trigger synchronization of the trigger signal; in the synchronization system of the present invention shown in fig. 2, each service board 2 only needs to pass through a set of differential lines and a trigger signal transmission line, and the synchronization of the trigger signal is realized by the programmable logic device 3 in the backplane 1. By a wide margin reduced the wiring on backplate 1, avoided on backplate 1 because the wiring too many and easily go wrong phenomenon that leads to whole backplate 1 to be unable to use, trigger signal synchronous test becomes more optimized simultaneously, only need can record at programmable logic device 3's output whether synchronous of signal, avoided the tradition on backplate 1 wiring, need detect the loaded down with trivial details detection that the trigger signal synchronous of every circuit produced, the time of detection has significantly reduced, it is more efficient.
Specifically, through such setting, the trigger signal sent by the service board 2 needs to pass through the trigger selection circuit module 5 first, the trigger selection circuit module 5 identifies the trigger signal, and the identified trigger signal can be fanned out to one or more preset corresponding logic or circuit modules 6; the logic or circuit module 6 screens and distributes the trigger signals identified by the trigger selection circuit module 5, and then transmits the trigger signals to the service boards 2, and the service boards 2 work according to the instructions of the trigger signals, thereby realizing the pairwise interconnection of all the service boards 2. For example, in combination with the business board No. 1,1 (i.e., "business board 1" in fig. 1), a trigger signal is sent out and transmitted to all the business boards No. 2 to n through the programmable logic device 3 to perform the trigger operation, or transmitted to any one of the business boards No. 2 to n to perform the trigger operation.
Preferably, the programmable logic device 3 is embodied as a CPLD or FPGA.
The CPLD adopts programming technologies such as CMOS EPROM, EEPROM, FLASH memory, and SRAM, etc., thereby forming a high-density, high-speed, and low-power consumption programmable logic device, and the advent of a reconfigurable programmable logic device based on SRAM (static random access memory) creates conditions for a system designer to dynamically change the logic function of the programmable logic device In an operating Circuit, and the programmable logic device uses SRAM cells to store configuration data, which determine the interconnection relationship and logic function inside the programmable logic device, and changes the data, that is, the logic function of the device, and since the data of SRAM is volatile, the data must be stored In a non-volatile memory such as EPROM, EEPROM, or FLASH ROM, etc., outside the programmable logic device, so that the system downloads it to the SRAM cells of the programmable logic device at an appropriate time, thereby implementing a Circuit reconfigurable ICR (In-Circuit reconfiguration).
The FPGA device belongs to a semi-custom circuit in an application-specific integrated circuit, is a programmable logic array, and can effectively solve the problem that the number of gate circuits of the original device is small. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit. The FPGA adopts a Logic Cell Array (LCA) concept, the FPGA internally comprises a Configurable Logic module CLB (Configurable Logic Block), an Input-Output module IOB (Input Output Block) and an internal connection (Interconnect), the FPGA is a programmable device, compared with the traditional Logic circuit and gate arrays (such as PAL, GAL and CPLD devices), the FPGA has different structures, the FPGA utilizes a small lookup table (16 x 1) to realize combined Logic, each lookup table is connected to a Logic unit, and the Logic unit is connected to a Logic unit driver, so that the FPGA can realize the Logic function or the Logic function of a Logic unit connected with the FPGA, and the FPGA can realize the Logic function of the FPGA by using the Logic unit driver, and the FPGA can realize the Logic function by using the Logic unit driver or the Logic unit connected to the FPGA through the Logic unit driver, thereby the FPGA can realize the Logic function of the Logic unit driver or the Logic unit connected to the FPGA through the Logic unit driver, and the FPGA can realize the Logic function of the Logic unit driver by using the small lookup table (16 x 1) to realize the combined Logic function of the combined Logic and the Logic unit connected to the FPGA, the FPGA allows infinite programming, the CPLD adopts programming technologies such as CMOS EPROM, EEPROM, flash memory, SRAM and the like, thereby forming the programmable logic device 3 with high density, high speed and low power consumption, the power failure is not lost, the equal length of the wiring among the internal circuit module groups and elements of the programmable logic device 3 can be realized, the equal length of the wiring among the internal circuit module groups and the elements of the FPGA can be realized, but the single price of the FPGA is higher than that of the CPLD, therefore, the CPLD is preferably used as the programmable logic device 3.
Preferably, the communication connection comprises:
a differential transmission connection line 7 for transmitting a differential trigger synchronization signal;
the communication protocol connection line 8 is used for transmitting the configuration signal of the trigger selection circuit module 5 corresponding to the service board 2.
Specifically, the differential transmission connection line 7 includes:
a sending signal connection line 72, configured to transmit a signal sent by the service board 2 to the trigger selection circuit module 5 for fan-out;
and a receiving signal connection line 71 for transmitting the trigger signal generated by the logic or circuit module 6 to the service board 2.
Preferably, the communication protocol connection line 8 is any one of a UART protocol connection line, an IIC protocol connection line, and an SPI protocol connection line.
The UART is a Universal Asynchronous Receiver/Transmitter (Universal Asynchronous Receiver/Transmitter), can convert data to be transmitted between serial communication and parallel communication, and is used as a chip for converting parallel input signals into serial output signals, the UART is usually integrated on the connection of other communication interfaces for Asynchronous communication, the bus is bidirectional communication, full duplex transmission and reception can be realized, and in an embedded design, the UART is used for communication between a host and an auxiliary device, such as communication between a programmable logic device 3 and a service board 2; the IIC is an integrated circuit bus, which is a serial communication bus, the IIC serial bus generally has two signal lines, one is a bidirectional data line SDA, the other is a clock line SCL, all serial data SDAs connected to IIC bus devices are connected to the bus SDA, the clock line SCL of each device is connected to the bus SCL, the operation (data transmission) of the bus is controlled by the service board 2, the host refers to a device which starts data transmission (sends a trigger signal), sends a clock signal, and sends a stop signal when the transmission is finished, the host, and a microprocessor. The devices visited by the master are called slaves, and each device connected to the I and C buses has a unique address for communication so as to be visited by the master. The data transmission of the host and the slave can be realized by transmitting data from the host to the slave or from the slave to the host, wherein the device for transmitting data to the bus is called a transmitter, and the device for receiving data from the bus is called a receiver; the SPI is a Serial Peripheral Interface (Serial Peripheral Interface), is a high-speed, full-duplex, synchronous communication bus, supports full-duplex communication, and is simple in communication and high in data transmission rate.
Specifically, the service board 2 can be a semiconductor test board, a wafer test board or a package test board. According to the actual test requirement, setting specific business logic in the business board.
Referring to fig. 2, for a specific example, 16 service boards are connected to 1 backplane to implement synchronous testing. The editable logic device 3 adopts a CPLD, and the communication protocol connecting line 8 adopts an IIC protocol connecting line.
As shown in fig. 2, each service board 2 is connected to the backplane 1, and includes a transmission signal connection line TRIG _ TX and a reception signal connection line TRIG _ RX, and an IIC line.
In the backplane, the CPLD is wired, and has circuit module groups of which the number corresponds to that of each service board, and the circuit module groups are connected one by one, that is, 16 service boards correspond to 16 circuit module groups in the CPLD one by one and are in communication connection.
Each circuit module set includes a trigger selection circuit module 5 and a logic or circuit module 6. Wherein, each logic or circuit module 6 is connected with all the trigger selection circuit modules 5, so as to realize the selective fan-out of one or more or all the trigger signals. Therefore, pairwise interconnection between any trigger selection circuit module 5 and any logic or circuit module 6 in the CPLD is realized.
For example, the second service board (i.e., "service board 2" in fig. 2) sends a trigger signal to the CPLD, and specifically, the trigger signal is sent to the trigger selection circuit module 5 in the corresponding circuit module group. The trigger selection circuit module 5 fans out the trigger signal to the corresponding selected service board logic or circuit module 6 according to a preset instruction rule, and according to the preset instruction rule, the trigger signal can be fanned out to 1 or more logic or circuit modules 6, for example, to the logic or circuit module 6 corresponding to the service board No. 1, or to the logic or circuit modules 6 corresponding to all the service boards. And the logic or circuit module 6 receiving the trigger signal will send the service board trigger signal to the corresponding service board after performing logic or processing. The logic or circuit module comprises a logic or circuit and an output synchronous trigger, wherein the input end of the output synchronous trigger is connected with the output end of the logic or circuit, and the output end of the output synchronous trigger is connected with the output signal delay unit.
And the communication protocol is connected with the circuit IIC circuit, so that the transmission of the configuration signals of the trigger selection circuit module 5 corresponding to the service board and the backboard can be realized.
In particular, in this embodiment, the method further includes calibrating the service board and the backplane by using the calibration board. Because the distance between the service boards and the chip can have a difference in physical distance, it is difficult to achieve the same distance between each service board and the backplane on the wiring, the difference in distance can cause delay in the signal transmission process, and the arrival sequence of the trigger signals is not favorable for the test requirements of the semiconductor test equipment. The calibration board is connected with the plurality of service boards, so that the time difference of receiving the trigger signals between the service boards can be acquired with high precision according to the change of the waveform signals, and the calibration board can also be connected with the programmable logic device to detect the time difference of receiving the trigger signals from the service boards by the plurality of power modules. The corresponding delay processing is performed by the input signal delay unit 41 and the output signal delay unit 42 based on the time difference.
The embodiment provides a multi-service board trigger signal synchronization system in ATE test equipment. The programmable logic device is used for communication between the back plate and the service board, and complex wiring design between the back plate and the service board is greatly reduced. The signal synchronization triggering between the backplane and the service board is realized by the input signal delay unit 41 and the output signal delay unit 42.
Example 2
The embodiment also provides a method for synchronizing the trigger signals of the multiple service boards in the ATE test equipment, which is used for synchronously selecting the trigger signals between the fan-out service boards 2, is suitable for a system comprising a back board and a plurality of service boards, and adopts a programmable logic device 3 to be in communication connection with each service board 2. The back board is provided with a programmable logic device, a plurality of circuit module groups are arranged in the programmable logic device, and each circuit module group corresponds to each service board one by one and is in communication connection with each service board. The specific steps are shown as the attached figure 9 in the specification, and the scheme is as follows:
101. establishing communication connection between the back board and each service board through the programmable logic device;
102. the time for receiving the trigger signals by the multiple circuit module groups is adjusted through the input signal delay unit 41, so that the multiple circuit module groups receive the trigger signals at the same time and the establishment and retention time of the input trigger signal latch is met;
103. receiving a trigger signal sent by a service board through a trigger selection circuit module 5, and fanning out the trigger signal to a correspondingly selected logic or circuit module 6;
104. receiving all trigger signals through a logic or circuit module 6, carrying out logic or processing, and sending the processed trigger signals to corresponding service boards;
105. the time for sending the trigger signal by the logic or circuit module 6 is adjusted by the output signal delay unit 42, so that a plurality of service boards receive the trigger signal at the same time and the establishment and retention time of the trigger signal latches on each service board is met.
The input signal delay unit 41 includes an input delay subunit (IDELAY) and an input delay carry chain, and the output signal delay unit 42 includes an output delay subunit (ODELAY) and an output delay carry chain. 102 specifically comprises:
an input delay subunit (IDELAY) carries out first time delay processing on the trigger signal according to a preset reference clock and a preset delay configuration;
the input delay carry chain carries out second time delay processing on the trigger signal according to the preset carry chain delay configuration;
after two time delay processes, the trigger signals are received by the multiple circuit module groups at the same time.
Step 105 specifically includes:
the output delay carry chain carries out first time delay processing on the trigger signal according to the preset carry chain delay configuration;
the output delay subunit (ODELAY) carries out second time delay processing on the trigger signal according to the preset reference clock and the preset delay configuration;
after two time delay processes, a plurality of service boards receive the trigger signals simultaneously and the establishment and retention time of the trigger signal latch on each service board is met.
In particular, in this embodiment, the method further includes calibrating, by the calibration board, a signal transmission time between the backplane and the service board. The method specifically comprises the following steps:
acquiring a first time difference of a plurality of circuit module groups receiving trigger signals and a second time difference of each service board receiving the trigger signals through a calibration board;
the input delay unit adjusts the time for receiving the trigger signal by the trigger selection circuit module 5 according to the first time difference, so that the trigger signal can be received by a plurality of circuit module groups at the same time. The method specifically comprises the following steps: and each input delay unit respectively adjusts the delay time according to the first time difference, so that the time for each input synchronous trigger to receive each trigger signal is the same, the establishment and the holding time of each input trigger are met, and the multiple circuit module groups can simultaneously receive the trigger signals.
The output delay unit adjusts the time for the logic or circuit module 6 to send the trigger signal according to the second time difference, so that the plurality of service boards receive the trigger signal at the same time and the establishment and retention time of the trigger signal latches on each service board is met.
Example 3
The present embodiment further provides a semiconductor test device, based on the method for synchronizing trigger signals based on a delay chain in an ATE semiconductor test device, as shown in fig. 3, including:
the test backboard 9 is characterized in that a programmable logic device is arranged on the test backboard 9;
a plurality of semiconductor test boards 10, wherein the semiconductor test boards 10 are in communication connection with the programmable logic devices;
the programmable logic device is used for receiving, processing and distributing trigger signals with the semiconductor test board 10.
According to the trigger signal synchronization system based on the delay chain in the ATE semiconductor test equipment, the programmable logic device is arranged on the backboard, all wiring in communication connection with the backboard is realized on the programmable logic device, the wiring on the traditional backboard is equivalently replaced, the problem that the backboard is complicated in wiring is solved, the isometric precision is high, and meanwhile, the trigger signal is easy to synchronize.
According to the trigger signal synchronization method based on the delay chain in the ATE semiconductor test equipment, the trigger signal transmitted by the service board is processed through the programmable logic device, and the problem that the trigger signal is synchronized to the service board is solved.
According to the chip test equipment provided by the invention, the test backboard is provided with the programmable logic device through the matching of the test backboard and the semiconductor test board, so that the equal-length layout and wiring can be carried out in the programmable logic device, and the test backboard is in communication connection with the test board, the problem of numerous and complicated wiring is solved, and the wiring on the test backboard is greatly reduced. Meanwhile, the synchronous test of the trigger signals becomes more optimized, whether the signals are synchronous can be detected only at the output end of the programmable logic device, the complex detection caused by the fact that the trigger signals of all lines need to be detected synchronously on the traditional back board wiring is avoided, the detection time is greatly reduced, and the efficiency is higher. Aiming at the problem of signal synchronization, the time difference of receiving the trigger signal is detected by using the calibration board, and corresponding signal delay is carried out through the delay unit based on the signal difference, so that the service boards can simultaneously send and receive the trigger signal, the signal synchronization precision can be controlled at the picosecond level, and the test requirement is completely met.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. The present invention is not to be limited by the specific embodiments disclosed herein, and other embodiments that fall within the scope of the claims of the present application are intended to be within the scope of the present invention.
Claims (10)
1. A trigger signal synchronization system based on a delay chain is characterized by comprising a backboard and a plurality of service boards;
the back plate is provided with a programmable logic device which is in communication connection with the service plate and is used for receiving, processing and distributing a trigger signal with the service plate;
a plurality of circuit module groups are arranged in the programmable logic device, and each circuit module group is used for corresponding to each service board one by one and carrying out communication connection;
each circuit module group comprises an input signal delay unit, an output signal delay unit, a trigger selection circuit module and a logic OR circuit module, wherein:
the trigger selection circuit module is connected with the corresponding service board signal and used for receiving the trigger signal adjusted by the input signal delay unit and fanning out the trigger signal to the correspondingly selected logic or circuit module;
the logic or circuit module is in signal connection with the service board and is used for receiving all the trigger signals output by the trigger selection circuit module, performing logic or processing on the trigger signals and sending the processed trigger signals to the corresponding service board through the output signal delay unit;
the input signal delay unit is connected with the trigger selection circuit modules and used for adjusting the time for the trigger selection circuit modules to receive the trigger signals so as to realize that the trigger selection circuit modules receive the trigger signals at the same time;
the output signal delay unit is connected with the logic or circuit and is used for adjusting the time for sending the trigger signal by the logic or circuit module so as to realize that a plurality of service boards receive the trigger signal at the same time;
each trigger selection circuit module is in communication connection with any one of the logic or circuit modules.
2. The delay chain based trigger signal synchronization system of claim 1, wherein the input signal delay unit comprises an input delay subunit (IDELAY) and an input delay carry chain, and an output terminal of the input delay subunit (IDELAY) is connected to an input terminal of the input delay carry chain;
the delay adjustable precision of the input delay subunit (IDELAY) is higher than that of the input delay carry chain;
the output signal delay unit comprises an output delay subunit (ODELAY) and an output delay carry chain, and the output end of the output delay carry chain is connected with the input end of the output delay subunit (ODELAY);
the delay adjustable precision of the output delay subunit (ODELAY) is higher than that of the output delay carry chain.
3. The delay chain-based trigger signal synchronization system according to claim 2, wherein the input delay carry chain comprises a delay selector and a plurality of delay units connected in series, output taps of the plurality of delay units are respectively connected to the delay selector, and the delay selector is configured to select an appropriate number of the delay units according to a preset carry chain delay configuration;
the output delay carry chain and the input delay carry chain have the same structure.
4. The delay chain based trigger signal synchronization system of claim 1, wherein the trigger selection circuit module comprises an input synchronization flip-flop, a plurality of logic and circuits, and a plurality of fan-out flip-flops;
the input end of each logic and circuit is respectively connected with the input synchronous trigger and a preset fan-out selection signal source, and the output end of each logic and circuit is connected with one fan-out trigger;
the input signal delay unit is connected with the input synchronous trigger;
the logic or circuit module comprises a logic or circuit and an output synchronous trigger, wherein the input end of the output synchronous trigger is connected with the output end of the logic or circuit, and the output end of the output synchronous trigger is connected with the output signal delay unit.
5. The delay chain based trigger signal synchronization system of claim 1, wherein the communication connection comprises:
a differential transmission connection line for differentially transmitting the trigger signal between the service board and the circuit module group;
the communication protocol connecting circuit is used for transmitting the configuration signal of the trigger selection circuit module corresponding to the service board and comprises a UART protocol connecting circuit, an IIC protocol connecting circuit or an SPI protocol connecting circuit;
wherein the differential transmission connection line comprises:
the sending signal connecting circuit is used for transmitting the triggering signal sent by the service board to the triggering selection circuit module for fan-out;
and the receiving signal connecting line is used for sending the trigger signal processed by the logic or circuit module to the service board.
6. The delay chain based trigger signal synchronization system of claim 1, wherein:
the service board is a semiconductor test board, a wafer test board or a packaging test board;
the programmable logic device is a CPLD or an FPGA.
7. A trigger signal synchronization method based on a delay chain is characterized in that: the system is suitable for a system comprising a backboard and a plurality of service boards, wherein a programmable logic device is arranged on the backboard, a plurality of circuit module groups are arranged in the programmable logic device, and the circuit module groups correspond to the service boards one by one and transmit trigger signals;
the method comprises the following steps:
establishing communication connection between the backboard and each service board through a programmable logic device;
the time for receiving the trigger signal by the circuit module groups is adjusted through the input signal delay unit, so that the circuit module groups can simultaneously receive the trigger signal and meet the establishment and retention time of the input trigger signal latch;
receiving the trigger signal adjusted by the input signal delay unit through a trigger selection circuit module, and fanning out the trigger signal to the correspondingly selected logic or circuit module;
receiving all trigger signals output by the trigger selection circuit module through a logic OR circuit module, carrying out logic OR processing, and sending the processed trigger signals to the corresponding service boards through an output signal delay unit;
the time for the logic or circuit module to send the trigger signal is adjusted through the output signal delay unit, so that the plurality of service boards receive the trigger signal at the same time and the establishment and retention time of the trigger signal latch on each service board is met.
8. The method of claim 7, wherein the trigger signal synchronization method based on the delay chain comprises: the input signal delay unit comprises an input delay subunit (IDELAY) and an input delay carry chain, and the output signal delay unit comprises an output delay subunit (ODELAY) and an output delay carry chain;
the "adjusting, by the input signal delay unit, the time for receiving the trigger signal by the plurality of circuit module groups to achieve that the plurality of circuit module groups receive the trigger signal at the same time" specifically includes:
an input delay subunit (IDELAY) carries out first time delay processing on the trigger signal according to a preset reference clock and a preset delay configuration;
the input delay carry chain carries out second time delay processing on the trigger signal according to the preset carry chain delay configuration;
after two time delay treatments, a plurality of circuit module groups receive the trigger signal at the same time;
the "adjusting, by the output signal delay unit, the time for sending the trigger signal by the logic or circuit module to achieve that a plurality of the service boards receive the trigger signal at the same time" specifically includes:
the output delay carry chain carries out first time delay processing on the trigger signal according to the delay configuration of a preset carry chain;
an output delay subunit (ODELAY) carries out second time delay processing on the trigger signal according to a preset reference clock and a preset delay configuration;
after two time delay processes, the service boards receive the trigger signal at the same time.
9. The method for synchronizing trigger signals based on a delay chain according to claim 7 or 8, further comprising: acquiring a first time difference of a plurality of circuit module groups receiving trigger signals and a second time difference of each service board receiving the trigger signals through a calibration board;
each input delay unit respectively adjusts the delay time according to the first time difference, so that the time for each input synchronous trigger to receive each trigger signal is the same, the establishment and the holding time of each input trigger are met, and the circuit module groups can simultaneously receive the trigger signals;
the output delay unit adjusts the time for the logic or circuit module to send the trigger signal according to the second time difference, and the service boards receive the trigger signals at the same time and meet the establishment and retention time of the trigger signal latches on the service boards.
10. A semiconductor test device, the method for synchronizing the trigger signals based on the delay chain according to any one of claims 7 to 9, comprising:
the test backboard is provided with a programmable logic device;
the semiconductor test boards are in communication connection with the programmable logic devices;
the programmable logic device is used for receiving, processing and distributing trigger signals with the semiconductor test board.
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| CN114024643B (en) * | 2022-01-10 | 2022-05-13 | 杭州加速科技有限公司 | Accurate control method and system for execution time of each function in ATE (automatic test equipment) |
| CN114859218B (en) * | 2022-03-16 | 2023-06-23 | 厦门智多晶科技有限公司 | Detection circuit and detection method for lookup table in FPGA chip |
| CN114355174B (en) * | 2022-03-17 | 2022-06-17 | 杭州加速科技有限公司 | Method and device for measuring and calibrating carry chain delay |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7697570B2 (en) * | 2001-04-30 | 2010-04-13 | Huawei Technologies Co., Ltd. | Method based on backboard transmitting time division multiplexing circuit data and a bridge connector |
| US7302282B2 (en) * | 2003-12-05 | 2007-11-27 | Agilent Technologies, Inc. | Communications system for implementation of synchronous, multichannel, galvanically isolated instrumentation devices |
| US7478256B2 (en) * | 2006-01-24 | 2009-01-13 | National Instruments Corporation | Coordinating data synchronous triggers on multiple devices |
| CN2922300Y (en) * | 2006-06-26 | 2007-07-11 | 华为技术有限公司 | Clock synchronizing system and service plate |
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| CN111385047B (en) * | 2018-12-28 | 2023-05-05 | 中兴通讯股份有限公司 | Time synchronization method and electronic equipment |
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| CN111786768B (en) * | 2020-07-10 | 2022-08-09 | 中国电子科技集团公司第十四研究所 | Multichannel parallel test calibration method |
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