CN110728108A - Parameter configuration method for ultra-high-speed SerDes circuit system - Google Patents
Parameter configuration method for ultra-high-speed SerDes circuit system Download PDFInfo
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Abstract
The invention provides a parameter configuration method of an ultra-high-speed SerDes circuit system, which relates to the technical field of circuit design and comprises the following steps: s1: providing parameters of printed lines and blind buried holes on the package; s2: extracting a printed line S parameter; s3: building a via hole model, and simulating S parameters; s4: acquiring an S parameter model and a SerDes IBIS-AMI model of the high-speed connector; s5: building a transmission channel and SerDes simulation model, and scanning the size of an RX end eye diagram of the transmission channel under different parameters in a simulation manner; s6: recording the optimal parameter combination of the eye pattern, which is the optimal parameter suitable for the transmission channel. The parameter configuration method of the ultra-high-speed SerDes circuit system can solve the problem that the configurable parameter combination of the SerDes circuit is too much, obtains layouts and structures such as packages, PCBs, via holes and the like, builds a transmission channel model, combines simulation of a SerDes IBIS-AMI model, obtains the optimal parameter combination under the corresponding transmission channel through parameter scanning, and supports stable transmission of high-speed signals.
Description
Technical Field
The present invention relates to the field of circuit design technology,
in particular, the present invention relates to a parameter configuration method for an ultra-high speed SerDes circuit system.
Background
With the continuous improvement of the transmission rate of high-speed serial signals, a serial deserializer (SerDes) circuit is increasingly complex, generally comprising a plurality of signal processing modules such as TX FFE, RX CTLE, RX DFE and the like, different modules comprise a plurality of configurable parameters, the combination of the configurable parameters is generally up to thousands, and the optimal parameter combination for a certain transmission channel is selected from the configurable parameters to solve the problem.
Document [ application method of three-dimensional electromagnetic simulation in 25 Gbps serial transceiving channel design, 2018, electronic technology application, 44 (8), 24-27 ] proposes to build a transmission channel model, and simulates channel quality factor (COM) in combination with a SerDes model, but the method has two problems: firstly, the used SerDes structure and algorithm are standard algorithms which can not reflect the real situation of the actual SerDes product, and secondly, the used channel model in which the packaging model is a reference packaging model defined by the standard and is a non-real product model.
Generally, SerDes designers can provide several reference parameter combinations, but since the SerDes designers do not deeply participate in printed board and package design and do not solve the performances of transmission distance, loss, reflection and the like of serial signal interconnection channels, the SerDes parameters provided by the SerDes designers are often not optimal parameters for adapting to different interconnection channels.
Therefore, how to design a reasonable parameter configuration method for an ultra-high-speed SerDes circuit system becomes a problem which needs to be solved urgently at present.
Disclosure of Invention
The invention aims to provide a parameter configuration method of an ultra-high-speed SerDes circuit system, which can solve the problem of excessive configurable parameter combinations of a SerDes circuit, obtain layouts and structures such as packages, PCBs (printed Circuit boards), via holes and the like, build a transmission channel model, combine simulation of a SerDes IBIS-AMI model, obtain an optimal parameter combination under a corresponding transmission channel through parameter scanning and support stable transmission of high-speed signals.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
a method for configuring parameters of an ultra-high speed SerDes circuitry, the method comprising the steps of:
s1: providing parameters of printed lines and blind buried holes on the package;
s2: extracting a printed line S parameter;
s3: building a via hole model, and simulating S parameters;
s4: acquiring an S parameter model and a SerDes IBIS-AMI model of the high-speed connector;
s5: building a transmission channel and SerDes simulation model, and scanning the size of an RX end eye diagram of the transmission channel under different parameters in a simulation manner;
s6: recording the optimal parameter combination of the eye pattern, which is the optimal parameter suitable for the transmission channel.
Preferably, in step S3, a chip package layout file is obtained, and parameters of the printed lines and the blind via holes on the package are extracted by using a parameter extraction software tool.
As a preferred aspect of the present invention, the parameters include loss, crosstalk, reflection, and S-parameters when step S1 is performed.
Preferably, in step S2, the PCB layout file and the overlay data are obtained, and the parameters of the differential tracks are input by using the ADS software tool, so as to extract the track S parameters.
As a preferred aspect of the present invention, when step S2 is performed, the parameters of the differential tracks include differential track line width, pitch, stack thickness, dielectric material dielectric constant, and loss tangent angle.
Preferably, when step S3 is executed, HFSS 3D modeling simulation software is used to build a PCB connector via and package BGA via model, and S parameters are simulated.
Preferably, when step S4 is executed, a high-speed connector S parameter model is obtained from a connector manufacturer; the SerDes IBIS-AMI model was obtained to SerDes designers.
Preferably, when step S5 is executed, a transmission channel and a SerDes simulation model are built in ADS software, SerDes configurable parameters are designed to be adjustable, and RX end eye diagram sizes of the transmission channel under different parameters are obtained through simulation scanning.
The parameter configuration method of the ultra-high-speed SerDes circuit system has the beneficial effects that: the problem that the configurable parameter combination of the SerDes circuit is too much can be solved, layouts and structures such as packages, PCBs and via holes are obtained, a transmission channel model is built, simulation is carried out by combining the SerDes IBIS-AMI model, the optimal parameter combination under the corresponding transmission channel is obtained through parameter scanning, and stable transmission of high-speed signals is supported.
Drawings
FIG. 1 is a schematic flow chart of a parameter configuration method for an ultra-high speed SerDes circuit system according to the present invention;
FIG. 2 is a schematic configuration diagram of a parameter configuration method for an ultra-high speed SerDes circuit system according to the present invention.
Detailed Description
The following are specific examples of the present invention and further describe the technical solutions of the present invention, but the present invention is not limited to these examples.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the modules and steps set forth in these embodiments and steps do not limit the scope of the invention unless specifically stated otherwise.
Meanwhile, it should be understood that the flows in the drawings are not merely performed individually for convenience of description, but a plurality of steps are performed alternately with each other.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and systems known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
Generally, SerDes designers can provide several reference parameter combinations, but since the SerDes designers do not deeply participate in printed board and package design and do not solve the performances of transmission distance, loss, reflection and the like of serial signal interconnection channels, the SerDes parameters provided by the SerDes designers are often not optimal parameters for adapting to different interconnection channels.
Example one
As shown in fig. 1, which is only one embodiment of the present invention, the present invention provides a parameter configuration method for an ultra-high speed SerDes circuit system, the method comprising the steps of:
a method for configuring parameters of an ultra-high speed SerDes circuitry, the method comprising the steps of:
s1: providing parameters of printed lines and blind buried holes on the package;
SerDes is an acronym for SERializer/DESerializer. It is a mainstream Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology. That is, at the transmitting end, the multi-path low-speed parallel signals are converted into high-speed serial signals, and finally, at the receiving end, the high-speed serial signals are converted into low-speed parallel signals again through a transmission medium (an optical cable or a copper wire). The point-to-point serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and improves the transmission speed of signals, thereby greatly reducing the communication cost.
Generally, SerDes designers need to fully acquire printed board and package design parameters to know the performance of transmission distance, loss, reflection and the like of a serial signal interconnection channel, so that the SerDes parameters need to be optimized, and printed line on package and blind buried via (S) parameters need to be extracted in a first step.
Here, a chip package layout file is obtained, and a parameter extraction software tool is used to provide package upper trace and blind via S parameters.
S2: extracting a printed line S parameter;
after the S parameters of the printed lines and the blind buried vias on the package are provided, the S parameters of the printed lines need to be extracted.
The PCB layout file and the lamination data are obtained, the ADS software tool is used for inputting parameters of differential printed lines, and printed line S parameters are extracted.
S3: building a via hole model, and simulating S parameters;
and (3) completing acquisition of printed board and packaging design parameters, building a PCB connector and a through hole model of the packaging BGA, and further simulating through hole S parameters.
S4: acquiring an S parameter model and a SerDes IBIS-AMI model of the high-speed connector;
here, a high-speed connector S parameter model is obtained to the connector manufacturer; and a SerDesIBIS-AMI model is obtained from a SerDes designer, an S parameter model and the SerDes IBIS-AMI model of the high-speed connector are fully known, and the accuracy of the models is ensured.
S5: building a transmission channel and SerDes simulation model, and scanning the size of an RX end eye diagram of the transmission channel under different parameters in a simulation manner;
and after the parameters and the model are obtained, a transmission channel and a SerDes simulation model are set up to carry out SerDes parameter debugging and testing.
Specifically, a transmission channel and a SerDes simulation model are built in ADS software, configurable parameters of the SerDes model are set, and then the RX end eye diagram size of the transmission channel under different parameters is scanned in a simulation mode.
It should be noted that each set of parameters is subjected to at least one simulation scan, that is, all the parameters are subjected to at least one simulation scan, at least one set of RX end eye diagram sizes under each parameter is obtained, and then compared to reduce errors.
S6: recording the optimal parameter combination of the eye pattern, which is the optimal parameter suitable for the transmission channel.
Storing and comparing each group of RX end eye diagrams to obtain the optimal parameter combination of the eye diagrams, wherein the obtained parameter combination is the optimal parameter suitable for the transmission channel,
of course, the optimal parameters applicable to different interconnect channels are different, and the RX end eye diagrams are repeatedly obtained and compared, so that the optimal parameters applicable to each interconnect channel can be obtained.
The parameter configuration method of the ultra-high-speed SerDes circuit system can solve the problem that the configurable parameter combination of the SerDes circuit is too much, obtains layouts and structures such as packages, PCBs and via holes, builds a transmission channel model, combines simulation of the SerDesIBIS-AMI model, obtains the optimal parameter combination under the corresponding transmission channel through parameter scanning, and supports stable transmission of high-speed signals.
Example two
Still referring to fig. 1, still another embodiment of the present invention is one of the embodiments of the present invention, in order to make the parameter configuration method of an ultra-high speed SerDes circuit system of the present invention more convenient in design and more accurate in parameter optimization, the present invention further has the following designs:
first, when step S1 is performed, the parameters include loss, crosstalk, reflection, and S-parameters.
Then, when step S2 is performed, the parameters of the differential tracks include differential track line width, pitch, stack thickness, dielectric material dielectric constant, and loss tangent angle.
And when step S3 is executed, HFSS 3D modeling simulation software is used to build a PCB connector via and package BGA via model, and S parameters are simulated.
Finally, the printed line and blind via S parameters on the package proposed when step S1 is executed, the printed line S parameters extracted when step S2 is executed, the via S parameters simulated when step S3 is executed, and the high-speed connector S parameter model and the SerDes IBIS-AMI model obtained when step S4 is executed are both required to be stored, which facilitates the calling of all parameters when step S5 is executed.
The parameter configuration method of the ultra-high-speed SerDes circuit system can solve the problem that the configurable parameter combination of the SerDes circuit is too much, obtains layouts and structures such as packages, PCBs and via holes, builds a transmission channel model, combines simulation of the SerDesIBIS-AMI model, obtains the optimal parameter combination under the corresponding transmission channel through parameter scanning, and supports stable transmission of high-speed signals.
While certain specific embodiments of the present invention have been described in detail by way of illustration, it will be understood by those skilled in the art that the foregoing is illustrative only and is not limiting of the scope of the invention, as various modifications or additions may be made to the specific embodiments described and substituted in a similar manner by those skilled in the art without departing from the scope of the invention as defined in the appending claims. It should be understood by those skilled in the art that any modifications, equivalents, improvements and the like made to the above embodiments in accordance with the technical spirit of the present invention are included in the scope of the present invention.
Claims (9)
1. A parameter configuration method for an ultra-high-speed SerDes circuit system is characterized by comprising the following steps:
s1: providing parameters of printed lines and blind buried holes on the package;
s2: extracting a printed line S parameter;
s3: building a via hole model, and simulating S parameters;
s4: acquiring an S parameter model and a SerDes IBIS-AMI model of the high-speed connector;
s5: building a transmission channel and SerDes simulation model, and scanning the size of an RX end eye diagram of the transmission channel under different parameters in a simulation manner;
s6: recording the optimal parameter combination of the eye pattern, which is the optimal parameter suitable for the transmission channel.
2. The ultra-high speed SerDes circuit system parameter configuration method of claim 1, wherein:
and step S1 is executed, a chip packaging layout file is obtained, and parameters of a printed line on the package and a blind buried hole S are provided by using a parameter extraction software tool.
3. The ultra-high speed SerDes circuit system parameter configuration method of claim 2, wherein:
in executing step S1, the parameters include loss, crosstalk, reflection, and S parameters.
4. The ultra-high speed SerDes circuit system parameter configuration method of claim 1, wherein:
and step S2 is executed, the PCB layout file and the lamination data are obtained, the ADS software tool is used for inputting the parameters of the differential printed lines, and the printed line S parameters are extracted.
5. The ultra-high speed SerDes circuit system parameter configuration method of claim 4, wherein:
in step S2, the parameters of the differential tracks include differential track line width, pitch, stack thickness, dielectric constant of the dielectric material, and loss tangent angle.
6. The ultra-high speed SerDes circuit system parameter configuration method of claim 1, wherein:
and when the step S3 is executed, HFSS 3D modeling simulation software is used for building a PCB connector via hole and a packaging BGA via hole model, and S parameters are simulated.
7. The ultra-high speed SerDes circuit system parameter configuration method of claim 1, wherein:
when step S4 is executed, an S parameter model of the high-speed connector is obtained from the connector manufacturer; the SerDes IBIS-AMI model was obtained to SerDes designers.
8. The ultra-high speed SerDes circuit system parameter configuration method of claim 1, wherein:
and when the step S5 is executed, a transmission channel and a SerDes simulation model are built in ADS software, SerDes configurable parameters are designed to be adjustable, and the size of an RX end eye diagram of the transmission channel under different parameters is simulated and scanned.
9. The ultra-high speed SerDes circuit system parameter configuration method of claim 1, wherein:
in step S5, each set of parameters is scanned at least once.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112668279A (en) * | 2020-12-30 | 2021-04-16 | 芯和半导体科技(上海)有限公司 | Via hole modeling method |
| CN113221504A (en) * | 2021-04-19 | 2021-08-06 | 山东英信计算机技术有限公司 | High-efficiency Via simulation data acquisition method, system and medium |
| CN113922890A (en) * | 2021-09-16 | 2022-01-11 | 烽火通信科技股份有限公司 | Pre-emphasis parameter adjustment method, device, equipment and readable storage medium |
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| CN101393579A (en) * | 2008-11-10 | 2009-03-25 | 福建星网锐捷网络有限公司 | Emulation design method and system for high speed interconnection system |
| US20160048475A1 (en) * | 2014-08-18 | 2016-02-18 | Huawei Technologies Co., Ltd. | Method, Apparatus, and System for Configuring High-Speed Serial Bus Parameter |
| CN105956230A (en) * | 2016-04-19 | 2016-09-21 | 杭州华三通信技术有限公司 | Electrical parameter compensation method and device |
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| CN101393579A (en) * | 2008-11-10 | 2009-03-25 | 福建星网锐捷网络有限公司 | Emulation design method and system for high speed interconnection system |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112668279A (en) * | 2020-12-30 | 2021-04-16 | 芯和半导体科技(上海)有限公司 | Via hole modeling method |
| CN112668279B (en) * | 2020-12-30 | 2023-12-08 | 芯和半导体科技（上海）股份有限公司 | Via modeling method |
| CN113221504A (en) * | 2021-04-19 | 2021-08-06 | 山东英信计算机技术有限公司 | High-efficiency Via simulation data acquisition method, system and medium |
| CN113922890A (en) * | 2021-09-16 | 2022-01-11 | 烽火通信科技股份有限公司 | Pre-emphasis parameter adjustment method, device, equipment and readable storage medium |
| CN113922890B (en) * | 2021-09-16 | 2023-09-29 | 烽火通信科技股份有限公司 | Pre-emphasis parameter adjustment method, pre-emphasis parameter adjustment device, pre-emphasis parameter adjustment equipment and readable storage medium |
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Application publication date: 20200124 |