CN113113472A - Power semiconductor device and manufacturing method thereof - Google Patents
Power semiconductor device and manufacturing method thereof Download PDFInfo
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- CN113113472A CN113113472A CN202110382782.XA CN202110382782A CN113113472A CN 113113472 A CN113113472 A CN 113113472A CN 202110382782 A CN202110382782 A CN 202110382782A CN 113113472 A CN113113472 A CN 113113472A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 177
- 229920005591 polysilicon Polymers 0.000 claims abstract description 134
- 210000000746 body region Anatomy 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 239000003990 capacitor Substances 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The embodiment of the invention discloses a power semiconductor device and a manufacturing method thereof. The power semiconductor device includes: the epitaxial layer comprises a plurality of deep grooves, and a bottom polycrystalline silicon layer positioned at the bottom of the deep grooves and a top polycrystalline silicon layer positioned at the top of the deep grooves are arranged in the deep grooves; wherein part of the deep trenches are first deep trenches, the bottom polysilicon layer in the first deep trenches is connected to a source electrode, and the top polysilicon layer is connected to a gate electrode; another part of the deep grooves are second deep grooves, the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the second deep grooves are connected to a grid electrode, and/or another part of the deep grooves are third deep grooves, and the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the third deep grooves are connected to a source electrode. Compared with the prior art, the embodiment of the invention realizes flexible adjustment of the reverse transmission capacitor and the input capacitor, and improves the efficiency and the reliability of the power semiconductor device.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a power semiconductor device and a manufacturing method thereof.
Background
Power Semiconductor devices, such as Metal Oxide Semiconductor Field-Effect transistors (MOSFETs), are widely used in electronic products. With the development of semiconductor technology, a high-density deep trench structure of a power semiconductor device is made possible.
Compared with the traditional power semiconductor device, the split-gate type deep-trench power semiconductor device adopting the coupling balance design can simultaneously realize low on-resistance (Rdson) and low reverse transmission capacitance (Crss), thereby reducing the conduction loss and the switching loss of a system and improving the use efficiency of an electronic product. However, in some applications, the conventional deep trench power semiconductor device needs to improve self-oscillation caused by too low reverse transfer capacitance Crss, so as to improve reliability and improve device lifetime. With the demand for lower on-resistance, the increase in cell density results in a high input capacitance Ciss, which affects switching efficiency and performance.
Disclosure of Invention
The embodiment of the invention provides a power semiconductor device and a manufacturing method thereof, which aim to improve the efficiency and reliability of the power semiconductor device.
In a first aspect, an embodiment of the present invention provides a power semiconductor device, including:
the epitaxial layer comprises a plurality of deep grooves, and a bottom polycrystalline silicon layer positioned at the bottom of the deep grooves and a top polycrystalline silicon layer positioned at the top of the deep grooves are arranged in the deep grooves;
wherein part of the deep trenches are first deep trenches, the bottom polysilicon layer in the first deep trenches is connected to a source electrode, and the top polysilicon layer is connected to a gate electrode;
another part of the deep grooves are second deep grooves, the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the second deep grooves are connected to a grid electrode, and/or another part of the deep grooves are third deep grooves, and the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the third deep grooves are connected to a source electrode.
Optionally, the second deep trench or the third deep trench further comprises:
an intermediate oxide layer located between the top polysilicon and the bottom polysilicon.
Optionally, the deep trench further comprises:
a deep trench oxide layer between the bottom polysilicon and the epitaxial layer;
and the gate electrode layer is positioned between the top polycrystalline silicon and the epitaxial layer.
Optionally, the top polysilicon and the bottom polysilicon within the second deep trench or the third deep trench are integrally disposed.
Optionally, the second deep trench or the third deep trench further comprises:
a deep trench oxide layer between the bottom polysilicon and the epitaxial layer and between the top polysilicon and the epitaxial layer.
Optionally, the second deep trench is located at a middle position of the plurality of deep trenches.
Optionally, the third deep trench is located at two ends of the plurality of deep trenches.
Optionally, every other deep trench is provided with a third deep trench.
Optionally, every second deep trench is disposed at a position of at least one deep trench.
Optionally, the power semiconductor device further comprises: a contact hole through which the top polysilicon is connected with the gate or the source;
and the partial region of the bottom polysilicon extends from the bottom of the deep groove to the top of the deep groove and is connected with the gate or the source through the contact hole.
Optionally, the power semiconductor device further comprises:
a body region on top of the semiconductor layer;
a source region located on top of the body region.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a power semiconductor device, including:
providing an epitaxial layer;
forming a plurality of deep grooves on the epitaxial layer, and forming a bottom polycrystalline silicon layer at the bottom of the deep grooves and a top polycrystalline silicon layer at the top of the deep grooves;
forming a body region and a source region on the epitaxial layer;
forming a grid electrode and a source electrode; wherein part of the deep trenches are first deep trenches, the bottom polysilicon layer in the first deep trenches is connected to a source electrode, and the top polysilicon layer is connected to a gate electrode; another part of the deep grooves are second deep grooves, the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the second deep grooves are connected to a grid electrode, and/or another part of the deep grooves are third deep grooves, and the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the third deep grooves are connected to a source electrode.
The embodiment of the invention arranges the second deep groove in the power semiconductor device, which is equivalent to connecting a part of the bottom polycrystalline silicon layer to the grid. Compared with the prior art that the bottom polycrystalline silicon layer is connected to the source electrode, the gate-drain capacitance CGD can be adjusted, so that the reverse transmission capacitance Crss is adjusted, the switching speed of the power semiconductor device is properly reduced, the self-oscillation of a circuit is reduced, and the efficiency and the reliability of the power semiconductor device are improved. The third deep trench is arranged in the power semiconductor device, which is equivalent to connecting a part of the top polycrystalline silicon layer to the source electrode. Compared with the prior art that the top polysilicon is connected to the grid, the area of the grid is reduced, and the adjustment of grid capacitance can be realized, so that the adjustment of input capacitances Ciss and Qg and the adjustment of device power consumption are realized.
In summary, the main contribution of the bottom polysilicon layer connected to the gate is to increase the reverse transfer capacitance Crss, and the main contribution of the top polysilicon layer connected to the source is to decrease the input capacitance Ciss. According to the embodiment of the invention, the second deep groove and/or the third deep groove are/is arranged in the split-gate type power semiconductor device, so that the reverse transmission capacitor Crss and/or Qg can be flexibly adjusted, and the efficiency and the reliability of the power semiconductor device can be improved.
Drawings
Fig. 1 is a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic layout diagram of a power semiconductor device according to an embodiment of the present invention; corresponding to the figure 1
FIG. 3 is a schematic cross-sectional view taken along line A-A '/E-E' of FIG. 2;
FIG. 4 is a schematic cross-sectional view taken along line B-B '/D-D' of FIG. 2;
FIG. 5 is a schematic cross-sectional view taken along line C-C' of FIG. 2;
fig. 6 is a schematic structural diagram of another power semiconductor device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another power semiconductor device according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another power semiconductor device according to an embodiment of the present invention;
fig. 9 is a schematic flow chart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention;
fig. 10-21 are schematic structural diagrams formed at various steps of a manufacturing method of a power semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Embodiments of the present invention provide a power semiconductor device, which may be, for example, a MOSFET. Fig. 1 is a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention. Referring to fig. 1, the power semiconductor device includes an epitaxial layer 200, the epitaxial layer 200 includes a plurality of deep trenches 210, and a bottom polysilicon layer 220 located at the bottom of the deep trenches 210 and a top polysilicon layer 230 located at the top of the deep trenches 210 are disposed therein. Wherein a portion of the deep trench 210 is the first deep trench 211, the bottom polysilicon layer 220 in the first deep trench 211 is connected to the source 300, and the top polysilicon layer 230 is connected to the gate (not shown in fig. 1). The other part of the deep trench 210 is a second deep trench 212, and both the bottom polysilicon layer 220 and the top polysilicon layer 230 in the second deep trench 212 are connected to the gate; and/or another portion of the deep trench 210 is the third deep trench 213, and the bottom polysilicon layer 220 and the top polysilicon layer 230 within the third deep trench 213 are connected to the source 300. Reference S denotes a connection to the source 300 and reference G denotes a connection to the gate. Illustratively, in fig. 1, the power semiconductor device includes five deep trenches 210, the first and fifth deep trenches 210 from left to right being third deep trenches 213, the second and fourth deep trenches 210 being first deep trenches 211, and the third deep trench 210 being second deep trench 212.
Various capacitances exist in the power semiconductor device, such as a gate-drain capacitance CGD, a gate-source capacitance CGS, a drain-source capacitance CDS, an input capacitance Ciss, an output capacitance Coss, and a reverse transfer capacitance Crss. The following relationship exists between these capacitances: cis ═ CGS + CGD; crss CGD; coss ═ CDS + CGD.
The embodiment of the invention provides the second deep trench 212 in the power semiconductor device, which is equivalent to connecting a part of the bottom polysilicon layer 220 to the gate. Compared with the prior art in which the bottom polysilicon layer 220 is connected to the source 300, the gate-drain capacitance CGD can be adjusted, so that the reverse transmission capacitance Crss can be adjusted, the switching speed of the power semiconductor device can be properly reduced, the self-oscillation of the circuit can be reduced, and the efficiency and the reliability of the power semiconductor device can be improved. In addition, the adjustment of the input capacitance Ciss and the output capacitance Coss is realized.
The third deep trench 213 is provided in the power semiconductor device according to the embodiment of the present invention, which is equivalent to connecting a portion of the top polysilicon layer 230 to the source 300. Compared with the prior art in which the top polysilicon layer 230 is connected to the gate, the area of the gate is reduced, and the input capacitances Ciss and Qg can be adjusted, and the power consumption of the device can be adjusted.
To sum up, the main contribution of the bottom polysilicon layer 220 connected to the gate is to increase the reverse transfer capacitance Crss, and the main contribution of the top polysilicon layer 230 connected to the source is to decrease the input capacitance Ciss. According to the embodiment of the invention, the second deep groove 212 and/or the third deep groove 213 are/is arranged in the split-gate type power semiconductor device, so that the reverse transmission capacitors Crss and Qg can be flexibly adjusted, and the efficiency and the reliability of the power semiconductor device can be improved.
With continued reference to fig. 1, based on the above embodiments, the power semiconductor device further includes a substrate 100, and an epitaxial layer 200 is disposed on the substrate 100.
With continued reference to fig. 1, on the basis of the above embodiments, a body region 240 and a source region 250 are further disposed on the epitaxial layer 200, and the body region 240 is located on top of the semiconductor layer; source region 250 is located on top of body region 240.
Fig. 2 is a layout schematic diagram of a power semiconductor device according to an embodiment of the present invention, fig. 3 is a schematic diagram of a cross-sectional structure of fig. 2 along a line a-a '/E-E ', fig. 4 is a schematic diagram of a cross-sectional structure of fig. 2 along a line B-B '/D-D ', and fig. 5 is a schematic diagram of a cross-sectional structure of fig. 2 along a line C-C '. Referring to fig. 2 to 5, on the basis of the above embodiments, the power semiconductor device optionally includes an active region 500, a gate runner 600 and a source runner 700. The power semiconductor devices are symmetrical patterns, and the number of the deep trenches 210 is five, and the deep trenches are sequentially arranged from top to bottom. The first and fifth deep trenches 210 are the third deep trench 213, and the top polysilicon layer 230 and the bottom polysilicon layer 220 in the third deep trench 213 are both connected to the source 300. The second and fourth deep trenches 210 are the first deep trench 211, the top polysilicon layer 230 in the first deep trench 211 is connected to the gate, and the bottom polysilicon layer 220 is connected to the source 300. The third deep trench 210 is the second deep trench 212, and the top polysilicon layer 230 and the bottom polysilicon layer 220 in the second deep trench 212 are both connected to the gate.
The power semiconductor device further includes a contact hole 400, and the source region 250 is connected to the source electrode 300 through the contact hole 400. Illustratively, the contact holes 400 located in the active region 500 are arranged in sequence from top to bottom, and the first, third, fourth, fifth, sixth, and eighth contact holes 400 connect the source region 250 and the source electrode 300.
With continued reference to fig. 2-5, optionally, the top polysilicon layer 230 is connected to the gate or source 300 through a contact hole 400. Illustratively, the second and seventh contact holes 400 located in the active region 500 connect the top polysilicon layer 230 of the third deep trench 213 and the source 300. The contact holes 400 in the gate runner 600 are divided into two rows, namely a first row of contact holes 400 near the source runner 700 and a second row of contact holes 400 near the active region 500. Wherein the second column of contact holes 400 connects the top polysilicon layer 230 of the deep trench 210. The first contact hole 400 and the third contact hole 400 of the second column connect the top polysilicon layer 230 and the gate of the first deep trench 211, and the second contact hole 400 of the second column connects the top polysilicon layer 230 and the gate of the second deep trench 212.
A partial region of the bottom polysilicon layer 220 extends from the bottom of the deep trench 210 to the top of the deep trench 210 and is connected to the gate or source 300 through the contact hole 400. Illustratively, the first column of contact holes 400 located in the gate runner 600 connects the bottom polysilicon layer 220 of the second deep trench 212 with the gate. The contact holes 400 located in the source runner 700 are sequentially arranged from top to bottom, and the first and fourth contact holes 400 connect the bottom polysilicon layer 220 of the third deep trench 213 with the source 300; the second and third contact holes 400 connect the bottom polysilicon layer 220 of the first deep trench 211 with the source 300.
The embodiment of the invention connects the top polysilicon layer 230 to the gate 800 or the source 300 through the contact hole 400, and connects the bottom polysilicon layer 220 to the gate 800 or the source 300, thereby reducing the process difficulty.
In the above embodiments, the second deep trench 212 and the third deep trench 213 of the power semiconductor device are disposed in various ways, for example, the power semiconductor device is disposed only in the second deep trench 212, or the power semiconductor device is disposed only in the third deep trench 213, or the power semiconductor device includes both the second deep trench 212 and the third deep trench 213. And the bottom polysilicon layer 220 and the top polysilicon layer 230 in the second deep trench 212 (or the third deep trench 213) may be disposed in various ways, and several of them will be described below without limiting the present invention.
With continued reference to fig. 1, in one embodiment of the present invention, optionally, the second deep trench 212 or the third deep trench 213 further includes an intermediate oxide layer 260, the intermediate oxide layer 260 being located between the top polysilicon layer 230 and the bottom polysilicon layer 220. Fig. 1 exemplarily shows that the second deep trench 212 and the third deep trench 213 each include an intermediate oxide layer 260, that is, the intermediate oxide layer 260 divides the bottom polysilicon layer 220 and the top polysilicon layer 230 in the second deep trench 212 into an upper portion and a lower portion, and the intermediate oxide layer 260 divides the bottom polysilicon layer 220 and the top polysilicon layer 230 in the third deep trench 213 into an upper portion and a lower portion. One skilled in the art will appreciate that an intermediate oxide layer 260 is also disposed between the top polysilicon layer 230 and the bottom polysilicon layer 220 of the first deep trench 211. Therefore, the embodiment of the present invention is configured such that the manufacturing method of the second deep trench 212 and the third deep trench 213 is the same as the manufacturing method of the first deep trench 211.
With continued reference to fig. 1, optionally, the deep trench 210 further includes a deep trench oxide layer 270 and a gate oxide layer 280, that is, the first deep trench 211, the second deep trench 212 and the third deep trench 213 have the deep trench oxide layer 270 and the gate oxide layer 280 disposed therein. Specifically, the deep trench oxide layer 270 is located between the bottom polysilicon layer 220 and the epitaxial layer 200, and is used for isolating the bottom polysilicon layer 220 from the epitaxial layer 200; the gate layer is located between the top polysilicon layer 230 and the epitaxial layer 200 for isolating the top polysilicon layer 230 from the epitaxial layer 200.
With continued reference to fig. 1, optionally, the power semiconductor device includes a first deep trench 211, a second deep trench 212, and a third deep trench 213, and the top polysilicon layer 230 and the bottom polysilicon layer 220 in each deep trench 210 are separated by an intermediate oxide layer 260.
In one embodiment of the present invention, optionally, the top polysilicon layer 230 and the bottom polysilicon layer 220 within the second deep trench 212 or the third deep trench 213 are integrally disposed. With the arrangement, the top polysilicon layer 230 and the bottom polysilicon layer 220 do not need to be manufactured in steps, which is beneficial to simplifying the manufacturing method of the second deep trench 212 or the third deep trench 213; in addition, the connection between the bottom polysilicon layer 220 and the gate/source 300 is simple and easy to implement. Exemplarily, fig. 6 is a schematic structural diagram of another power semiconductor device provided in an embodiment of the present invention. Referring to fig. 6, in one embodiment of the present invention, optionally, the top polysilicon layer 230 and the bottom polysilicon layer 220 within the third deep trench 213 are integrally disposed.
With continued reference to fig. 6, optionally, the second deep trench 212 or the third deep trench 213 further includes a deep trench oxide layer 270, the deep trench oxide layer 270 being located between the bottom polysilicon layer 220 and the epitaxial layer 200, and between the top polysilicon layer 230 and the epitaxial layer 200. By such an arrangement, the deep trench oxide layer 270 in the second deep trench 212 or the third deep trench 213 does not need to be manufactured in steps, which is beneficial to simplifying the manufacturing method of the second deep trench 212 or the third deep trench 213.
With continued reference to fig. 6, optionally, the power semiconductor device includes a first deep trench 211, a second deep trench 212, and a third deep trench 213. Wherein the top polysilicon layer 230 and the bottom polysilicon layer 220 in the first deep trench 211 and the second deep trench 212 are both separated by the inter-oxide layer 260; the top polysilicon layer 230 and the bottom polysilicon layer 220 in the third deep trench 213 are integrally disposed.
In one embodiment of the present invention, in conjunction with fig. 1 and 6, the second deep trench 212 is optionally located at an intermediate position of the plurality of deep trenches 210. Illustratively, the power semiconductor device includes five deep trenches 210, and the third deep trench 210 from left to right is a second deep trench 212. Optionally, the third deep trench 213 is located at two ends of the plurality of deep trenches 210. Illustratively, the power semiconductor device includes five deep trenches 210, and the first and fifth deep trenches 210 from left to right are the third deep trenches 213. Accordingly, the second and fourth deep trenches 210, as counted from left to right, are the first deep trench 211. The power semiconductor device is arranged in such a way, so that the structure of the power semiconductor device is symmetrical, and the stability of the device is improved.
Fig. 7 is a schematic structural diagram of another power semiconductor device according to an embodiment of the present invention. Referring to fig. 7, in one embodiment of the present invention, the power semiconductor device optionally includes a first deep trench 211 and a third deep trench 213. Wherein the first deep trench 211 is located in the middle, and the third deep trench 213 is located at both ends. The top polysilicon layer 230 and the bottom polysilicon layer 220 in the first deep trench 211 are both separated by an intermediate oxide layer 260; the top polysilicon layer 230 and the bottom polysilicon layer 220 in the third deep trench 213 are integrally disposed.
Fig. 8 is a schematic structural diagram of another power semiconductor device according to an embodiment of the present invention. Referring to fig. 8, in one embodiment of the present invention, the power semiconductor device optionally includes a first deep trench 211, a second deep trench 212, and a third deep trench 213. The first deep trench 211 is located in the middle, and the second deep trench 212 and the third deep trench 213 are located at two ends, respectively. The top polysilicon layer 230 and the bottom polysilicon layer 220 in the first deep trench 211 and the third deep trench 213 are both separated by an intermediate oxide layer 260; the top polysilicon layer 230 and the bottom polysilicon layer 220 in the second deep trench 212 are integrally disposed.
It should be noted that fig. 1-8 only exemplarily show several arrangements of the first deep trench 211, the second deep trench 212, and the third deep trench 213, and do not limit the present invention. In other embodiments, the number of the deep grooves can be set to other numbers; the arrangement of the first deep trench 211, the second deep trench 212, and the third deep trench 213 can be set to other arrangements, for example, every other third deep trench 213 and/or every other second deep trench 212 are cyclically provided in the active region, and the arrangement can be set according to actual needs in practical applications.
In summary, the embodiment of the present invention may provide the second deep trench 212 in which the top polysilicon layer 230 and the bottom polysilicon layer 220 are both connected to the gate 800, and may also provide the third deep trench 213 in which the top polysilicon layer 230 and the bottom polysilicon layer 220 are both connected to the source 300 in the power semiconductor device. And the second deep trench 212 and the third deep trench 213 are flexibly arranged, so that the reverse transmission capacitor Crss and the input capacitor ciss (qg) are flexibly adjusted, and the efficiency and the reliability of the power semiconductor device are improved.
The embodiment of the invention also provides a manufacturing method of the power semiconductor device, which is suitable for the power semiconductor device provided by any embodiment of the invention. Fig. 9 is a schematic flowchart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention. Referring to fig. 9, the method of manufacturing the power semiconductor device includes the steps of:
and S110, providing an epitaxial layer.
The material of the epitaxial layer may be, for example, an N-type semiconductor or a P-type semiconductor, and may be set as needed in practical applications.
And S120, forming a plurality of deep grooves on the epitaxial layer, and forming a bottom polycrystalline silicon layer at the bottom of the deep grooves and a top polycrystalline silicon layer at the top of the deep grooves.
The process of forming the deep trench may be, for example, an etching process such as dry etching, wet etching, or laser etching, and the process of forming the bottom polysilicon layer and the top polysilicon layer in the deep trench may be, for example, a deposition process.
Optionally, the top polysilicon layer and the bottom polysilicon layer are separately disposed, and before depositing the bottom polysilicon layer, forming a deep trench oxide layer at the bottom of the deep trench; and before depositing the top polysilicon layer, forming an intermediate oxide layer on the bottom polysilicon layer, and forming a gate oxide layer on the side wall of the deep trench.
Optionally, the top polysilicon layer and the bottom polysilicon layer are integrally disposed, and before depositing the polysilicon layers (the integral top polysilicon layer and the bottom polysilicon layer), forming a deep trench oxide layer at the bottom of the deep trench is further included.
And S130, forming a body region and a source region on the epitaxial layer.
S140, forming a grid electrode and a source electrode; wherein, part of the deep grooves are first deep grooves, the bottom polycrystalline silicon layer in the first deep grooves is connected to the source electrode, and the top polycrystalline silicon layer is connected to the grid electrode; and the other part of the deep groove is a second deep groove, the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the second deep groove are both connected to the grid, and/or the other part of the deep groove is a third deep groove, and the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the third deep groove are connected to the source.
Through the steps, the second deep trench, in which the top polysilicon layer and the bottom polysilicon layer are both connected to the gate, can be arranged in the power semiconductor device, and the third deep trench, in which the top polysilicon layer and the bottom polysilicon layer are both connected to the source, can also be arranged. And the second deep groove and the third deep groove are flexibly arranged, so that the reverse transmission capacitor Crss and the input capacitor Ciss (Qg) are flexibly adjusted, and the efficiency and the reliability of the power semiconductor device are improved.
On the basis of the above embodiments, the embodiments of the present invention provide a specific method for manufacturing a power semiconductor device. Fig. 10-21 are schematic structural diagrams formed at various steps of a manufacturing method of a power semiconductor device according to an embodiment of the present invention.
S210, referring to fig. 10, a silicon epitaxial wafer is provided, the epitaxial wafer including a substrate 100 and an epitaxial layer 200.
S220, referring to fig. 11, a plurality of deep trenches 210 are formed on the epitaxial layer 200.
S230, referring to fig. 12, a deep trench oxide material 271 is grown within the deep trench 210.
S240, referring to fig. 13, the polysilicon material 221 is filled such that the polysilicon material 221 covers the deep trench oxide layer material.
S250, referring to fig. 14, the excess polysilicon material is removed, and only the polysilicon material at the bottom is remained, thereby forming the bottom polysilicon layer 220.
S260, referring to fig. 15, an intermediate oxide layer material 261 is grown such that the intermediate oxide layer material 261 covers the bottom polysilicon layer 220 and the deep trench oxide layer material 271.
S270, referring to fig. 16, the excess intermediate oxide layer material and the deep trench oxide layer material are etched to form an intermediate oxide layer 260 and a deep trench oxide layer 270.
S280, referring to fig. 17, a gate oxide layer 280 is grown such that the gate oxide layer 280 covers the middle oxide layer 260 and the upper surface of the epitaxial layer 200.
S290, referring to fig. 18, the top polysilicon layer 230 is filled and etched back (etch back).
S2a0, see fig. 19, body regions 240 and source regions 250 are formed atop epitaxial layer 200.
S2B0, see fig. 20, a Glass layer 900, for example, Boron-doped phosphosilicate Glass (BPSG) or similar material is deposited.
S2C0, see fig. 21, contact holes 400 are formed and a metal layer is deposited to form the gate 800 and the source 300.
Wherein, part of the deep trenches 210 are the first deep trenches 211, the bottom polysilicon layer 220 in the first deep trenches 211 is connected to the source 300, and the top polysilicon layer 230 is connected to the gate; the other part of the deep trench 210 is a second deep trench 212, the bottom polysilicon layer 220 and the top polysilicon layer 230 in the second deep trench 212 are both connected to the gate, the other part of the deep trench 210 is a third deep trench 213, and the bottom polysilicon layer 220 and the top polysilicon layer 230 in the third deep trench 213 are connected to the source 300.
Through S210-S2C0, the power semiconductor device formed includes a first deep trench 211, a second deep trench 212, and a third deep trench 213, and the top polysilicon layer 230 and the bottom polysilicon layer 220 in each deep trench 210 are separated by an intermediate oxide layer 260.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A power semiconductor device, comprising:
the epitaxial layer comprises a plurality of deep grooves, and a bottom polycrystalline silicon layer positioned at the bottom of the deep grooves and a top polycrystalline silicon layer positioned at the top of the deep grooves are arranged in the deep grooves;
wherein part of the deep trenches are first deep trenches, the bottom polysilicon layer in the first deep trenches is connected to a source electrode, and the top polysilicon layer is connected to a gate electrode;
another part of the deep grooves are second deep grooves, the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the second deep grooves are connected to a grid electrode, and/or another part of the deep grooves are third deep grooves, and the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the third deep grooves are connected to a source electrode.
2. The power semiconductor device of claim 1, wherein the second deep trench or the third deep trench further comprises:
an intermediate oxide layer located between the top polysilicon and the bottom polysilicon.
3. The power semiconductor device of claim 2, wherein the deep trench further comprises:
a deep trench oxide layer between the bottom polysilicon and the epitaxial layer;
and the gate electrode layer is positioned between the top polycrystalline silicon and the epitaxial layer.
4. The power semiconductor device of claim 1, wherein the top polysilicon and the bottom polysilicon within the second deep trench or the third deep trench are integrally disposed.
5. The power semiconductor device of claim 4, wherein the second deep trench or the third deep trench further comprises:
a deep trench oxide layer between the bottom polysilicon and the epitaxial layer and between the top polysilicon and the epitaxial layer.
6. The power semiconductor device of claim 1, wherein the second deep trench is located at a middle position of the plurality of deep trenches;
and/or the third deep trench is positioned at two ends of the plurality of deep trenches.
7. The power semiconductor device as claimed in any one of claims 1-6, wherein a third deep trench is provided at every other location of at least one of said deep trenches;
and/or every two deep grooves are provided with a second deep groove at the position of at least one deep groove.
8. The power semiconductor device according to any one of claims 1 to 6, further comprising: a contact hole through which the top polysilicon is connected with the gate or the source;
and the partial region of the bottom polysilicon extends from the bottom of the deep groove to the top of the deep groove and is connected with the gate or the source through the contact hole.
9. The power semiconductor device according to any one of claims 1 to 6, further comprising:
a body region on top of the semiconductor layer;
a source region located on top of the body region.
10. A method of manufacturing a power semiconductor device, comprising:
providing an epitaxial layer;
forming a plurality of deep grooves on the epitaxial layer, and forming a bottom polycrystalline silicon layer at the bottom of the deep grooves and a top polycrystalline silicon layer at the top of the deep grooves;
forming a body region and a source region on the epitaxial layer;
forming a grid electrode and a source electrode; wherein part of the deep trenches are first deep trenches, the bottom polysilicon layer in the first deep trenches is connected to a source electrode, and the top polysilicon layer is connected to a gate electrode; another part of the deep grooves are second deep grooves, the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the second deep grooves are connected to a grid electrode, and/or another part of the deep grooves are third deep grooves, and the bottom polycrystalline silicon layer and the top polycrystalline silicon layer in the third deep grooves are connected to a source electrode.
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| CN202110382782.XA CN113113472A (en) | 2021-04-09 | 2021-04-09 | Power semiconductor device and manufacturing method thereof |
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| US20160315053A1 (en) * | 2011-04-28 | 2016-10-27 | Ji Pan | Flexible crss adjustment in a sgt mosfet to smooth waveforms and to avoid emi in dc-dc application |
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| US20170162689A1 (en) * | 2015-12-02 | 2017-06-08 | Jun Hu | Sgt mosfet with adjustable crss and ciss |
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Application publication date: 20210713 |