CN113497120B - Split gate device structure - Google Patents

Split gate device structure Download PDF

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Publication number
CN113497120B
CN113497120B CN202010192099.5A CN202010192099A CN113497120B CN 113497120 B CN113497120 B CN 113497120B CN 202010192099 A CN202010192099 A CN 202010192099A CN 113497120 B CN113497120 B CN 113497120B
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layer
gate
split gate
substrate
side wall
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CN113497120A (en
Inventor
刘聪慧
季明华
张汝京
徐怀花
杨龙康
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a split gate device structure, comprising: a substrate; a control gate structure in the substrate; a split gate structure located below the control gate structure; the separation grid structure comprises a core area and an isolation structure wrapping the core area; the core region includes an air gap layer or a dielectric layer. The invention provides the split gate structure without connecting to the emitter or the source of the device by arranging the split gate structure with the core region and the isolation structure below the control gate structure of the power device, thereby not only reducing the miller capacitance from the grid electrode to the drain electrode in the device, but also reducing the on-resistance of the device and simplifying the process flow. In addition, the influence on the performance of devices such as switching loss is avoided, the breakdown voltage of the devices is improved, and the market competitiveness of products is enhanced.

Description

Split gate device structure
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and in particular, to a split gate device structure.
Background
In power devices such as IGBTs, the miller capacitance (MILLER CAPACITANCE) generated from the gate-to-drain (gate-to-drain) of the device can severely affect the switching speed and power consumption of the device, resulting in reduced product performance.
Currently, the miller capacitance formed from the gate to the drain of the device is typically reduced by providing a thicker silicon dioxide layer or split-gate structure under the control gate of the device. However, for devices using thicker silicon dioxide layers, the doped regions are formed under the silicon dioxide layers by ion implantation, which is complicated and inefficient. In order to effectively perform the function of the MOSFET or IGBT device with the split gate structure, an additional interconnection structure is designed for the split gate structure so as to connect the split gate structure to the source or emitter of the device, the additional resistance value introduced by the connection structure increases the switching loss of the device, and the topography requirement for the split gate trench is also higher, which is difficult and complex in process.
Therefore, there is a need to propose a new split gate device structure that solves the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a split gate device structure, which is used for solving the problem that the miller capacitance and the conduction voltage drop of the device cannot be effectively reduced in the prior art.
To achieve the above and other related objects, the present invention provides a split gate device structure, comprising:
A substrate;
A control gate structure in the substrate;
a split gate structure located below the control gate structure;
The separation grid structure comprises a core area and an isolation structure wrapping the core area; the core region includes an air gap layer or a core region dielectric layer.
As an alternative of the present invention, the isolation structure includes an isolation structure dielectric layer.
As an alternative of the invention, the core region comprises an air gap layer.
As an alternative of the present invention, the isolation structure further includes a sidewall layer located on an inner sidewall of the dielectric layer of the isolation structure.
As an alternative of the invention, the core region comprises an air gap layer.
As an alternative of the present invention, the core region includes a core region dielectric layer.
As an alternative of the present invention, the core region includes a core region dielectric layer and an air gap layer wrapped in the core region dielectric layer.
As an alternative scheme of the invention, the side wall layer is a floating structure.
As an alternative of the present invention, the sidewall layer is connected to the source or emitter of the device.
As an alternative of the present invention, the control gate structure includes a gate material layer and a gate oxide layer surrounding the gate material layer.
As described above, the present invention provides a split gate device structure having the following beneficial effects:
According to the invention, a novel split gate device structure is introduced, and a split gate structure with a core region and an isolation structure is arranged below a control gate structure of a power device, so that the split gate structure which is not connected to a source electrode or an emitter electrode of the device is provided, the miller capacitance from a gate electrode to a drain electrode in the device is reduced, the on-resistance of the device is also reduced, and meanwhile, the process flow is simplified. In addition, the influence on the performance of devices such as switching loss and the like is avoided, and the breakdown voltage of the devices is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a prior art power device having a thick oxide gate trench structure.
Fig. 2 is a schematic cross-sectional view of a prior art power device having a split gate trench structure.
Fig. 3 is a schematic cross-sectional view of a split gate device structure according to a first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a split gate device structure according to a second embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a split gate device structure according to a second embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a split gate device structure according to a third embodiment of the present invention.
Description of element reference numerals
100. Substrate and method for manufacturing the same
101. Groove structure
102. Dielectric layer
103. Control grid
104 P-type doped region
105 P-type well region
106 N+ source region
107 P+ doped region
108. Source electrode
109 N+ doped region
110. Drain electrode
200. Substrate and method for manufacturing the same
201. Groove structure
202. Dielectric layer
203. Control grid
204. Separation grid
205 P-type well region
206 N+ source region
207 P+ doped region
208. Source electrode
209 N+ doped region
210. Drain electrode
300. Substrate and method for manufacturing the same
301. Grid material layer
301A gate oxide
302. Isolation structure dielectric layer
303. Air gap layer
304 P-type well region
305 N+ type emitter region
306 P+ doped region
307. Emitter electrode
308 N+ doped region
309 P+ doped region
400. Substrate and method for manufacturing the same
401. Grid material layer
401A gate oxide
402. Isolation structure dielectric layer
403. Air gap layer
404 P-type well region
405 N+ type emitter region
406 P+ doped region
407. Emitter electrode
408 N+ doped region
409 P+ doped region
410. Side wall layer
500. Substrate and method for manufacturing the same
501. Grid material layer
501A gate oxide
502. Isolation structure dielectric layer
503. Air gap layer
504 P-type well region
505 N+ type emitter region
506 P+ doped region
507. Emitter electrode
508 N+ doped region
509 P+ doped region
510. Side wall layer
511. Core region dielectric layer
600. Substrate and method for manufacturing the same
601. Grid material layer
601A gate oxide
602. Isolation structure dielectric layer
604 P-type well region
605 N+ type emitter region
606 P+ doped region
607. Emitter electrode
608 N+ doped region
609 P+ doped region
610. Side wall layer
611. Core region dielectric layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 1, a schematic cross-sectional view of a power device employing a thick oxygen layer trench structure in the prior art is shown.
In fig. 1, a trench structure 101 filling a dielectric layer 102 is formed in an N-type epitaxial substrate 100, and a control gate 103 is also formed in the dielectric layer 102. The dielectric layer 102 is a silicon dioxide layer, and the bottom portion thereof below the control gate 103 is thicker, forming a thick oxygen layer, and a P-type doped region 104 is formed below the thick oxygen layer by implantation. A P-type well region 105, an n+ type source region 106, a p+ type doped region 107 and a source 108 are also formed on the front surface of the substrate 100; an n+ type doped region 109 and a drain electrode 110 are also formed on the back surface of the substrate 101. For the device shown in fig. 1, the process flow is complicated and the effect of reducing miller capacitance is not ideal because of the need to form a thick oxygen layer and P-type doped region 104.
As shown in fig. 2, a schematic cross-sectional view of a prior art power device having a split gate trench structure is shown.
In fig. 2, a trench structure 201 is formed in an N-type epitaxial substrate 200, which is filled with a dielectric layer 202, and a control gate 203 located at the upper part and a separation gate 204 located at the lower part are also formed in the dielectric layer 202. A P-type well region 205, an n+ type source region 206, a p+ type doped region 207 and a source electrode 208 are also formed on the front surface of the substrate 200; an n+ type doped region 209 and a drain 210 are also formed on the back side of the substrate 200. As can be seen in fig. 2, in order for the split gate 204 to effectively function in the device structure to reduce the miller capacitance of the control gate 203 to the drain 210, the split gate 204 needs to be electrically connected to the source 208. The additional resistance introduced by the connection structure can increase the device loss, and the requirement on the morphology of the separation gate trench is higher, so that the process is difficult and complex.
In addition, other improved structures exist for improving the miller capacitance of the power device, such as schemes for improving the bottom morphology of the control gate and assisting in thickening the bottom gate oxide layer. However, these prior art improved structures are not only complex in process flow, but also suffer from more or less drawbacks associated with the structures provided in fig. 1 or 2 and are not effective in reducing miller capacitance without affecting other device performance.
Referring to fig. 3, the present invention provides a split gate device structure, which is characterized by comprising:
A substrate 300;
a control gate structure located in the substrate 300;
a split gate structure located below the control gate structure;
The separation grid structure comprises a core area and an isolation structure wrapping the core area; the core region includes an air gap layer 303.
As an example, the substrate 300 may be a wafer having an N-type doped epitaxial layer grown on a surface thereof, and the epitaxial layer may be formed of a semiconductor material such as silicon (Si), silicon germanium (SiGe), gallium nitride (GaN), or silicon carbide (SiC) by epitaxial (epi) growth.
As an example, in the case of preparing the split gate device structure in this embodiment, the control gate structure and the split gate structure are formed in the same trench, which is formed by performing an anisotropic dry etching process on the substrate 300. After the groove etching is completed, the separation gate structure at the bottom is formed, and then the control gate structure is formed above the separation gate structure. And the control gate structure and the separation gate structure are isolated by a dielectric layer.
As an example, as shown in fig. 3, the isolation structure includes an isolation structure dielectric layer 302; the isolation structure dielectric layer 302 comprises a silicon dioxide layer. Optionally, the silicon dioxide layer is deposited by a Non-conformal chemical vapor deposition (Non-uniform PLASMA CVD) process, and because the Non-conformal chemical vapor deposition process has weak hole filling capability, the top of the silicon dioxide layer is sealed when the structures such as grooves or holes are not filled, and a void structure is easy to form. After the isolation structure dielectric layer 302 is formed, an air gap layer 303 is also formed inside the isolation structure dielectric layer.
As an example, as shown in fig. 3, the control gate structure includes a gate material layer 301 and a gate oxide layer 301a. The gate oxide layer 301a wraps the gate material layer 301, and the gate material layer 301 is led out through a connection structure such as a contact structure. Alternatively, the gate material layer 301 is made of a polysilicon material, and the gate oxide layer 301a is made of a silicon dioxide material.
It should be noted that the separation gate structure provided by the present invention is not limited to be obtained by the forming method provided by the embodiment of the present invention, and in other embodiments of the present invention, the separation gate structure may be obtained by any other feasible preparation method.
As an example, as shown in fig. 3, as an IGBT device, a P-type well region 304, an n+ -type emitter region 305, a p+ -type doped region 306, and an emitter 307 are further formed on the front surface of the substrate 300 by conventional means; an n+ type doped region 308 and a p+ type doped region 309 are also formed on the back surface of the substrate 300. The P + doped region 309 further connects the collector of the device to form an IGBT device structure. In addition, when the invention is used for other power devices such as power MOSFETs, the parts can be correspondingly adjusted according to the device structure. Specifically, in the device structure described above, if the p+ type doped region 309 is not present, i.e., corresponds to the MOSFET structure, the corresponding names in the structure may be modified accordingly. For example, the emitter may also be referred to as a source, and the n+ emitter region may also be referred to as an n+ source region.
The embodiment provides a split gate device structure, which is formed below a control gate structure and has an air gap wrapped by a silicon dioxide dielectric layer, wherein the structure is a floating structure (floating), the effect of reducing the gate-to-drain miller capacitance can be exerted without connecting a device source electrode or an emitter electrode, and the on-resistance of the device is effectively reduced. The chip area occupied by the power device with the split gate trench structure is greatly reduced, the product performance is improved, and the market competitiveness is further enhanced.
Example two
Referring to fig. 4, the present embodiment provides a split gate device structure, which is different from the first embodiment at least in that: the isolation structure further includes a sidewall layer 410 formed on the inner sidewall of the isolation structure dielectric layer 402.
As in the first embodiment, in the case of preparing the split gate device structure in the present embodiment, the control gate structure and the split gate structure are formed in the same trench formed by performing an anisotropic dry etching process on the substrate 400. After the isolation structure dielectric layer 402 is formed on the sidewall of the trench, a step of forming a sidewall layer 410 on the sidewall inside the isolation structure dielectric layer 402 is further included. Optionally, the sidewall layer 410 includes a polysilicon layer, and the core region includes an air gap layer 403; the forming process of the sidewall layer 410 includes conformally depositing a polysilicon material layer, and etching back the sidewall layer 410 by anisotropic dry etching. After forming the sidewall layer 410, the air gap layer 403 is formed by non-conformal pecvd silicon dioxide layer.
As an example, the sidewall layer is a floating structure, or may be connected to a source or an emitter of the device.
As an example, as shown in fig. 4, the control gate structure includes a gate material layer 401 and a gate oxide layer 401a. The gate oxide layer 401a wraps the gate material layer 401, and the gate material layer 401 is led out through a connection structure such as a contact structure. Alternatively, the gate material layer 401 is made of a polysilicon material, and the gate oxide layer 401a is made of a silicon dioxide material.
As an example, as shown in fig. 4, as in the first embodiment, a P-type well region 404, an n+ type emitter region 405, a p+ type doped region 406, and an emitter 407 may be further formed on the front surface of the substrate 400; an n+ type doped region 408 and a p+ type doped region 409 are also formed on the back surface of the substrate 400. The p+ doped region 409 is further connected to the collector of the device to form an IGBT device structure. It should be noted that, in the above device structure, if the p+ type doped region 409 is not present, that is, corresponds to the MOSFET structure, the corresponding name in the structure may be modified accordingly. For example, the emitter may also be referred to as a source, and the n+ emitter region may also be referred to as an n+ source region.
It is to be noted that, as shown in fig. 4, a device structure obtained when the width of the trench formed during the process is small, and when the trench width is large, a device structure as shown in fig. 5 may also be formed.
As shown in fig. 5, in addition to the air gap layer 503, a core dielectric layer 511 made of silicon dioxide may be formed in the core region. I.e. the air gap layer 503 and the sidewall layer 510 are separated by the core dielectric layer 511.
Similar to the other structures of fig. 4, in fig. 5, a gate material layer 501, a gate oxide layer 501a, and the isolation structure dielectric layer 502 are formed in the substrate 500; a P-type well region 504, an n+ type emitting region 505, a p+ type doped region 506 and an emitter 507 are also formed on the front surface of the substrate 500; an n+ type doped region 508 and a p+ type doped region 509 are also formed on the back surface of the substrate 500. The P + type doped region 509 is further connected to the collector of the device, which has formed the IGBT device structure. It should be noted that, in the above device structure, if the p+ type doped region 509 is not provided, that is, it corresponds to a MOSFET structure, the corresponding name in the structure may be modified accordingly.
Other embodiments of this embodiment are the same as those of embodiment one, and will not be described here again.
Compared with the first embodiment, the embodiment forms the polysilicon side wall layer on the inner side wall of the dielectric layer of the isolation structure by introducing polysilicon deposition and anisotropic etching. The floating structures such as the polysilicon side wall layer in the separation gate form a capacitor, so that the miller capacitance from the gate to the drain of the power device with the separation gate structure can be reduced, the polysilicon side wall layer can also maintain certain charge balance, the charge accumulation of the epitaxial layer is reduced, the breakdown voltage of the device is increased, and the stability of the device is improved. The split gate structure of the present embodiment also does not introduce additional capacitance between gate to source or drain to source. In addition, when the polysilicon side wall layer is in a floating structure, the polysilicon side wall layer does not need to be connected with a source electrode or grounded, so that the on-resistance of the device is effectively reduced, the occupied chip area of the device is greatly reduced, and the product performance and the market competitiveness are improved.
Example III
Referring to fig. 6, the present embodiment provides a split gate device structure, which is different from the embodiment at least in that: the air gap layer is not arranged in the core region of the formed split gate structure, and only the core region dielectric layer 611 is included.
As in the embodiment, in preparing the split gate device structure in the present embodiment, the control gate structure and the split gate structure are formed in the same trench formed by performing an anisotropic dry etching process on the substrate 600. After the isolation structure dielectric layer 602 is formed on the sidewall of the trench, a step of forming a sidewall layer 610 on the sidewall of the inner side of the isolation structure dielectric layer 602 is further included. Optionally, the sidewall layer 610 includes a polysilicon layer, and the core region includes an air gap layer 603; the forming process of the sidewall layer 610 includes conformally depositing a polysilicon material layer, and etching back the sidewall layer 610 by anisotropic dry etching.
The difference from the second embodiment is that after the sidewall layer 610 is formed, a core dielectric layer 611 is formed between the sidewall layers 610 at both sides by a conformal film forming process such as high density plasma chemical vapor deposition (HDP-CVD). HDP-CVD has good hole filling capability to ensure that the deposited dielectric layer fills the regions between the sidewall layers 610 without forming voids. Optionally, the core dielectric layer 611 includes a silicon dioxide layer, or is made of the same material as the sidewall layer 610.
As an example, as shown in fig. 6, as in the embodiment, a P-type well region 604, an n+ type emitter region 605, a p+ type doped region 606, and an emitter 607 are also formed on the front surface of the substrate 600; an n+ type doped region 608 and a p+ type doped region 609 are also formed on the back surface of the substrate 600. The P + doped region 609 is further connected to the collector of the device to form an IGBT device structure. It should be noted that, in the above device structure, if the p+ type doped region 609 is not present, that is, corresponds to the MOSFET structure, the corresponding name in the structure may be modified accordingly.
Compared with the second embodiment, the embodiment provides various schemes for the implementation of the invention by adopting the dielectric material layer to replace the air gap layer, thereby not only having the technical effect of the second embodiment, but also simplifying the process flow.
In summary, the present invention provides a split gate device structure, including: a substrate; a control gate structure in the substrate; a split gate structure located below the control gate structure; the separation grid structure comprises a core area and an isolation structure wrapping the core area; the core region includes an air gap layer or a dielectric layer. The invention provides the split gate structure without connecting to the source or the emitter of the device by arranging the split gate structure with the core region and the isolation structure below the control gate structure of the power device, thereby not only reducing the miller capacitance from the grid electrode to the drain electrode in the device, but also reducing the on-resistance of the device, and simplifying the process flow. In addition, the influence on the performance of devices such as switching loss is avoided, the breakdown voltage of the devices is improved, and the market competitiveness of products is enhanced.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (5)

1. A split gate device structure comprising:
A substrate;
A control gate structure in the substrate;
a split gate structure located below the control gate structure;
The separation grid structure comprises a core area and an isolation structure wrapping the core area; the core region comprises an air gap layer, the isolation structure comprises an isolation structure medium layer and a side wall layer positioned on the inner side wall of the isolation structure medium layer, the air gap layer is formed between the opposite side wall layers, the forming process of the side wall layer comprises conformal deposition of a polysilicon material layer, the side wall layer is formed by anisotropic dry etching back, and after the side wall layer is formed, the air gap layer is formed by non-conformal plasma chemical vapor deposition of a silicon dioxide layer.
2. The split gate device structure of claim 1, wherein the core region further comprises a core region dielectric layer, and the air gap layer is wrapped in the core region dielectric layer.
3. The split gate device structure of claim 1, wherein the sidewall layer is a floating structure.
4. The split gate device structure of claim 1, wherein the sidewall layer connects to a device source or emitter.
5. The split gate device structure of claim 1, wherein the control gate structure comprises a layer of gate material and a gate oxide layer surrounding the layer of gate material.
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JP2019176104A (en) * 2018-03-29 2019-10-10 トヨタ自動車株式会社 Switching element
CN110400843A (en) * 2018-04-24 2019-11-01 半导体元件工业有限责任公司 Transistor and the method for preparing the transistor
EP3621116A1 (en) * 2018-09-06 2020-03-11 Infineon Technologies Austria AG Semiconductor device and manufacturing method thereof

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US8319278B1 (en) * 2009-03-31 2012-11-27 Maxpower Semiconductor, Inc. Power device structures and methods using empty space zones
JP2019176104A (en) * 2018-03-29 2019-10-10 トヨタ自動車株式会社 Switching element
CN110400843A (en) * 2018-04-24 2019-11-01 半导体元件工业有限责任公司 Transistor and the method for preparing the transistor
EP3621116A1 (en) * 2018-09-06 2020-03-11 Infineon Technologies Austria AG Semiconductor device and manufacturing method thereof

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