CN113497120A - Split gate device structure - Google Patents

Split gate device structure Download PDF

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Publication number
CN113497120A
CN113497120A CN202010192099.5A CN202010192099A CN113497120A CN 113497120 A CN113497120 A CN 113497120A CN 202010192099 A CN202010192099 A CN 202010192099A CN 113497120 A CN113497120 A CN 113497120A
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layer
gate
split
dielectric layer
gate structure
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CN113497120B (en
Inventor
刘聪慧
季明华
张汝京
徐怀花
杨龙康
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a separation grid device structure, comprising: a substrate; a control gate structure in the substrate; a split gate structure located below the control gate structure; the separation gate structure comprises a core area and an isolation structure wrapping the core area; the core region includes an air gap layer or a dielectric layer. According to the invention, the separation gate structure with the core region and the isolation structure is arranged below the control gate structure of the power device, so that the separation gate structure which is not required to be connected to the emitter or the source of the device is provided, not only is the Miller capacitance from the gate to the drain in the device reduced, but also the on-resistance of the device is reduced, and meanwhile, the process flow is simplified. In addition, the influence on the device performances such as switching loss and the like is avoided, the breakdown voltage of the device is improved, and the market competitiveness of the product is enhanced.

Description

Split gate device structure
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a split gate device structure.
Background
In power devices such as IGBTs, Miller capacitance (Miller capacitance) generated from a gate-to-drain (gate-to-drain) of the device can seriously affect the switching speed and power consumption of the device, resulting in reduced product performance.
Currently, the miller capacitance formed from the gate to the drain of the device is typically reduced by providing a thicker silicon dioxide layer or split-gate structure under the control gate of the device. However, for the device using the thicker silicon dioxide layer, the doped region is additionally formed under the silicon dioxide layer by ion implantation, which is complex in process flow and poor in effect. In the MOSFET or IGBT device with the split-gate structure, in order to effectively exert its function, an additional interconnection structure is designed for the split-gate structure to connect the split-gate structure to the source or emitter of the device, and the extra resistance introduced by the connection structure increases the switching loss of the device, and has a high requirement on the shape of the split-gate trench, which is difficult and complicated in process.
Therefore, there is a need to provide a new split gate device structure to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a split gate device structure, which is used to solve the problem that the miller capacitance and the on-state voltage drop of the device cannot be effectively reduced in the prior art.
To achieve the above and other related objects, the present invention provides a split gate device structure, comprising:
a substrate;
a control gate structure in the substrate;
a split gate structure located below the control gate structure;
the separation gate structure comprises a core area and an isolation structure wrapping the core area; the core region comprises an air gap layer or a core region dielectric layer.
As an alternative of the invention, the isolation structure comprises an isolation structure dielectric layer.
As an alternative of the invention, the core region comprises an air gap layer.
As an alternative of the invention, the isolation structure further comprises a side wall layer positioned on the inner side wall of the isolation structure dielectric layer.
As an alternative of the invention, the core region comprises an air gap layer.
As an alternative of the invention, the core region comprises a core region dielectric layer.
As an alternative of the present invention, the core region comprises a core region dielectric layer and an air gap layer wrapped in the core region dielectric layer.
As an alternative of the present invention, the sidewall layer is a floating structure.
As an alternative of the invention, the spacer layer is connected to the device source or emitter.
As an alternative of the present invention, the control gate structure includes a gate material layer and a gate oxide layer wrapping the gate material layer.
As described above, the present invention provides a split gate device structure, which has the following beneficial effects:
according to the invention, a new split gate device structure is introduced, and the split gate structure with the core region and the isolation structure is arranged below the control gate structure of the power device, so that the split gate structure which is not required to be connected to a source electrode or an emitter electrode of the device is provided, not only is the Miller capacitance from the gate electrode to the drain electrode in the device reduced, but also the on-resistance of the device is reduced, and meanwhile, the process flow is simplified. In addition, the influence on the device performances such as switching loss and the like is avoided, and the breakdown voltage of the device is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a prior art power device having a thick oxygen layer gate trench structure.
Fig. 2 is a schematic cross-sectional view of a prior art power device having a split-gate trench structure.
Fig. 3 is a schematic cross-sectional view illustrating a structure of a split-gate device according to a first embodiment of the invention.
Fig. 4 is a schematic cross-sectional view illustrating a structure of a split-gate device according to a second embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view illustrating a structure of a split-gate device according to a second embodiment of the invention.
Fig. 6 is a schematic cross-sectional view illustrating a structure of a split-gate device according to a third embodiment of the present invention.
Description of the element reference numerals
100 substrate
101 trench structure
102 dielectric layer
103 control gate
104P type doped region
105P type well region
106N + type source region
107P + type doped region
108 source electrode
109N + type doped region
110 drain electrode
200 substrate
201 trench structure
202 dielectric layer
203 control gate
204 separation grid
205P type well region
206N + type source region
207P + type doped region
208 source electrode
209N + type doped region
210 drain electrode
300 substrate
301 layer of gate material
301a gate oxide layer
302 isolation structure dielectric layer
303 air gap layer
304P type well region
305N + type emitter region
306P + type doped region
307 emitter electrode
308N + type doped region
309P + type doped region
400 substrate
401 layer of gate material
401a gate oxide layer
402 isolation structure dielectric layer
403 air gap layer
404P-type well region
405N + type emitter region
406P + type doped region
407 emitter
408N + type doped region
409P + type doped region
410 side wall layer
500 substrate
501 layer of gate material
501a gate oxide layer
502 isolation structure dielectric layer
503 air gap layer
504P type well region
505N + type emitter region
506P + type doped region
507 emitter
508N + type doped region
509P + type doped region
510 side wall layer
511 core region dielectric layer
600 substrate
601 layer of gate material
601a gate oxide layer
602 isolation structure dielectric layer
604P type well region
605N + type emitter region
606P + type doped region
607 emitter
608N + type doped region
609P + type doped region
610 side wall layer
611 core area dielectric layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Fig. 1 is a schematic cross-sectional view of a power device employing a thick oxygen layer trench structure in the prior art.
In fig. 1, a trench structure 101 filled with a dielectric layer 102 is formed in an N-type epitaxial substrate 100, and a control gate 103 is also formed in the dielectric layer 102. The dielectric layer 102 is a silicon dioxide layer, and the bottom portion thereof located below the control gate 103 is thicker, so as to form a thick oxygen layer, and a P-type doped region 104 is formed below the thick oxygen layer by implantation. A P-type well region 105, an N + type source region 106, a P + type doped region 107 and a source 108 are further formed on the front surface of the substrate 100; an N + type doped region 109 and a drain 110 are also formed on the back surface of the substrate 101. For the device shown in fig. 1, the process flow is complicated and the effect of reducing the miller capacitance is not ideal because it requires the formation of a thick oxygen layer and the P-type doped region 104.
Fig. 2 is a schematic cross-sectional view of a power device having a split-gate trench structure in the prior art.
In fig. 2, a trench structure 201 filled with a dielectric layer 202 is formed in an N-type epitaxial substrate 200, and a control gate 203 located at the upper portion and a separation gate 204 located at the lower portion are also formed in the dielectric layer 202. A P-type well region 205, an N + type source region 206, a P + type doped region 207 and a source 208 are further formed on the front surface of the substrate 200; an N + type doped region 209 and a drain 210 are also formed on the back side of the substrate 200. As can be seen from fig. 2, in order to effectively exert the effect of the split gate 204 in the device structure in reducing the miller capacitance from the control gate 203 to the drain 210, the split gate 204 needs to be electrically connected to the source 208. The extra resistance introduced by the connecting structure can increase the loss of the device, and the requirement on the shape of the separation gate groove is higher, so that the process is difficult and complicated.
In addition, for improving the miller capacitance of the power device, other improved structures exist, such as a scheme of improving the bottom topography of the control gate and assisting in thickening the bottom gate oxide layer. However, these existing improved structures not only have a complicated process flow, but also have more or less of the defects of the structures provided in fig. 1 or fig. 2, and cannot effectively reduce the miller capacitance without affecting other properties of the device.
Referring to fig. 3, the present invention provides a split gate device structure, comprising:
a substrate 300;
a control gate structure in the substrate 300;
a split gate structure located below the control gate structure;
the separation gate structure comprises a core area and an isolation structure wrapping the core area; the core region includes an air gap layer 303.
As an example, the substrate 300 may be a wafer with an N-type doped epitaxial layer grown on the surface, and the epitaxial layer may be formed by epitaxial (epi) growth of a semiconductor material such as silicon (Si), silicon germanium (SiGe), gallium nitride (GaN), or silicon carbide (SiC).
For example, in the present embodiment, when the split-gate device structure is prepared, the control gate structure and the split-gate structure are formed in the same trench, and the trench is formed by performing an anisotropic dry etching process on the substrate 300. After the groove is etched, the separation gate structure at the bottom is formed, and then the control gate structure is formed above the separation gate structure. And the control gate structure and the separation gate structure are isolated by a dielectric layer.
As an example, as shown in fig. 3, the isolation structure includes an isolation structure dielectric layer 302; the isolation structure dielectric layer 302 includes a silicon dioxide layer. Optionally, the silicon dioxide layer is deposited by a Non-conformal plasma chemical vapor deposition (Non-conformal CVD) process, and since the Non-conformal CVD process has a weak hole filling capability, the top of the silicon dioxide layer is already sealed when the structure such as the trench or the hole is not filled, so that a void structure is easily formed. After the isolation structure dielectric layer 302 is formed, an air gap layer 303 is also formed inside the isolation structure dielectric layer.
As an example, as shown in fig. 3, the control gate structure includes a gate material layer 301 and a gate oxide layer 301 a. The gate oxide layer 301a wraps the gate material layer 301, and the gate material layer 301 is led out through a connection structure such as a contact structure. Optionally, the gate material layer 301 is made of a polysilicon material, and the gate oxide layer 301a is made of a silicon dioxide material.
It should be noted that the split gate structure provided by the present invention is not limited to be obtained by the formation method provided by the embodiment of the present invention, and in other embodiments of the present invention, the split gate structure can be obtained by any other feasible preparation method.
As an example, as shown in fig. 3, as an IGBT device, a P-type well region 304, an N + -type emitter region 305, a P + -type doped region 306, and an emitter 307 are further formed on the front surface of the substrate 300 by conventional technical means; an N + type doped region 308 and a P + type doped region 309 are also formed on the back surface of the substrate 300. The P + type doped region 309 is further connected to the collector of the device to form an IGBT device structure. In addition, when the invention is used for other power devices such as power MOSFETs and the like, the parts can be adjusted correspondingly according to the device structure. In particular, in the device structure described above, if the P + -type doped region 309 is not present, i.e., corresponding to a MOSFET structure, the corresponding name in the structure may be changed accordingly. For example, the emitter may also be referred to as the source, and the N + -type emitter region may also be referred to as the N + -type source region.
The embodiment provides a split gate device structure, wherein a split gate structure with an air gap wrapped by a silicon dioxide dielectric layer is formed below a control gate structure, the structure is a floating structure (floating), the effect of reducing the miller capacitance from a gate to a drain can be exerted without connecting a source or an emitter of the device, and the on-resistance of the device is effectively reduced. The chip area occupied by the power device with the split gate groove structure is greatly reduced, the product performance is improved, and further the market competitiveness is enhanced.
Example two
Referring to fig. 4, the present embodiment provides a split gate device structure, and compared with the first embodiment, the main differences of the present embodiment are at least: the isolation structure further includes a sidewall layer 410 formed on the inner sidewall of the isolation structure dielectric layer 402.
As in the first embodiment, when the split-gate device structure is prepared in this embodiment, the control gate structure and the split-gate structure are formed in the same trench, and the trench is formed by performing an anisotropic dry etching process on the substrate 400. After the isolation structure dielectric layer 402 is formed on the sidewall of the trench, a step of forming a sidewall layer 410 on the inner sidewall of the isolation structure dielectric layer 402 is further included. Optionally, the sidewall layer 410 comprises a polysilicon layer, and the core region comprises an air gap layer 403; the formation of the sidewall layer 410 includes conformally depositing a polysilicon material layer, and etching back to form the sidewall layer 410 by anisotropic dry etching. After the sidewall layer 410 is formed, the air gap layer 403 is formed by non-conformal plasma chemical vapor deposition of silicon dioxide layer.
The sidewall layer is a floating structure, or may be connected to the source or emitter of the device, as an example.
As an example, as shown in fig. 4, the control gate structure includes a gate material layer 401 and a gate oxide layer 401 a. The gate oxide layer 401a wraps the gate material layer 401, and the gate material layer 401 is led out through a connection structure such as a contact structure. Optionally, the gate material layer 401 is made of a polysilicon material, and the gate oxide layer 401a is made of a silicon dioxide material.
As an example, as shown in fig. 4, as in the first embodiment, a P-well region 404, an N + -type emitter region 405, a P + -type doped region 406, and an emitter 407 may be further formed on the front surface of the substrate 400; an N + type doped region 408 and a P + type doped region 409 are also formed on the back side of the substrate 400. The P + type doped region 409 is further connected to the collector of the device to form an IGBT device structure. It should be noted that, in the device structure, if the P + -type doped region 409 is not provided, that is, corresponding to the MOSFET structure, the corresponding name in the structure may be changed accordingly. For example, the emitter may also be referred to as the source, and the N + -type emitter region may also be referred to as the N + -type source region.
It is noted that fig. 4 shows a device structure obtained when the width of the trench formed during the process is small, and when the width of the trench is large, a device structure as shown in fig. 5 may also be formed.
As shown in fig. 5, a core dielectric layer 511 of silicon dioxide may be formed in the core region in addition to the air gap layer 503. I.e., the air gap layer 503 and the sidewall layer 510 are separated by the core dielectric layer 511.
Similar to the other structures in fig. 4, in fig. 5, a gate material layer 501, a gate oxide layer 501a and the isolation structure dielectric layer 502 are formed in the substrate 500; a P-type well region 504, an N + -type emitter region 505, a P + -type doped region 506 and an emitter 507 are further formed on the front surface of the substrate 500; an N + type doped region 508 and a P + type doped region 509 are also formed on the back surface of the substrate 500. The P + type doped region 509 is further connected to the collector of the device to form an IGBT device structure. It should be noted that, in the above device structure, if the P + -type doped region 509 is not provided, that is, corresponding to the MOSFET structure, the corresponding name in the structure can be changed accordingly.
Other embodiments of this embodiment are the same as the first embodiment, and are not described herein again.
Compared with the first embodiment, in the embodiment, by introducing polysilicon deposition and anisotropic etching, a polysilicon sidewall layer is formed on the inner sidewall of the isolation structure dielectric layer. Floating structures such as a polysilicon side wall layer in the separation gate form a capacitor, so that the Miller capacitance from the gate to the drain of the power device with the separation gate structure can be reduced, the polysilicon side wall layer can maintain certain charge balance, the charge accumulation of an epitaxial layer is reduced, the breakdown voltage of the device is increased, and the stability of the device is improved. The split-gate structure in this embodiment also does not introduce additional capacitance between the gate to the source or the drain to the source. In addition, when the polycrystalline silicon side wall layer is of a floating structure, the polycrystalline silicon side wall layer does not need to be connected with a source electrode or grounded, the on-resistance of a device is effectively reduced, the chip area occupied by the device is greatly reduced, and the product performance and the market competitiveness are improved.
EXAMPLE III
Referring to fig. 6, the present embodiment provides a split gate device structure, and compared with the first embodiment, the main differences of the present embodiment are at least: the core region of the formed separation gate structure has no air gap layer and only includes a core region dielectric layer 611.
As in the embodiment, when the split-gate device structure is prepared in this embodiment, the control gate structure and the split-gate structure are formed in the same trench, and the trench is formed by performing an anisotropic dry etching process on the substrate 600. After the isolation structure dielectric layer 602 is formed on the sidewall of the trench, a step of forming a sidewall layer 610 on the sidewall inside the isolation structure dielectric layer 602 is further included. Optionally, the sidewall layer 610 comprises a polysilicon layer, and the core region comprises an air gap layer 603; the formation of the sidewall layer 610 includes conformally depositing a polysilicon material layer, and forming the sidewall layer 610 by anisotropic dry etching back.
The difference from the second embodiment is that after the sidewall layers 610 are formed, a core dielectric layer 611 between the sidewall layers 610 on both sides is formed by a conformal film forming process such as high density plasma chemical vapor deposition (HDP-CVD). HDP-CVD has good hole-filling capability, which ensures that the deposited dielectric layer fills the regions between the sidewall layers 610 without forming voids. Optionally, the core region dielectric layer 611 includes a silicon dioxide layer, or is made of the same material as the sidewall layer 610.
As an example, as shown in fig. 6, as in the embodiment, a P-type well region 604, an N + -type emitter region 605, a P + -type doped region 606, and an emitter 607 are further formed on the front surface of the substrate 600; an N + type doped region 608 and a P + type doped region 609 are also formed on the back surface of the substrate 600. The P + type doped region 609 is further connected to the collector of the device to form an IGBT device structure. It should be noted that, in the device structure, if the P + -type doped region 609 is not provided, that is, corresponding to the MOSFET structure, the corresponding name in the structure may be changed accordingly.
Compared with the second embodiment, the second embodiment provides various schemes for implementing the invention by adopting the dielectric material layer to replace the air gap layer, thereby having the technical effects of the second embodiment and simplifying the process flow.
In summary, the present invention provides a split gate device structure, including: a substrate; a control gate structure in the substrate; a split gate structure located below the control gate structure; the separation gate structure comprises a core area and an isolation structure wrapping the core area; the core region includes an air gap layer or a dielectric layer. According to the invention, the separation gate structure with the core region and the isolation structure is arranged below the control gate structure of the power device, so that the separation gate structure which is not required to be connected to a device source or an emitter is provided, not only is the Miller capacitance from the gate to the drain in the device reduced, but also the on-resistance of the device is reduced, and meanwhile, the process flow is simplified. In addition, the influence on the device performances such as switching loss and the like is avoided, the breakdown voltage of the device is improved, and the market competitiveness of the product is enhanced.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A split gate device structure, comprising:
a substrate;
a control gate structure in the substrate;
a split gate structure located below the control gate structure;
the separation gate structure comprises a core area and an isolation structure wrapping the core area; the core region comprises an air gap layer or a core region dielectric layer.
2. The split-gate device structure of claim 1, wherein the isolation structure comprises an isolation structure dielectric layer.
3. The split gate device structure of claim 2, wherein the core region comprises an air gap layer.
4. The split-gate device structure of claim 2, wherein the isolation structure further comprises a sidewall layer on an inner sidewall of the isolation structure dielectric layer.
5. The split gate device structure of claim 4, wherein the core region comprises an air gap layer.
6. The split-gate device structure of claim 4, wherein the core region comprises a core region dielectric layer.
7. The split-gate device structure of claim 4, wherein the core region comprises a core region dielectric layer and an air gap layer wrapped in the core region dielectric layer.
8. The split-gate device structure of claim 4, wherein the sidewall layer is a floating structure.
9. The split-gate device structure of claim 4, wherein the sidewall spacer layer connects a device source or emitter.
10. The split-gate device structure of claim 1, wherein the control gate structure comprises a layer of gate material and a gate oxide layer surrounding the layer of gate material.
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US8319278B1 (en) * 2009-03-31 2012-11-27 Maxpower Semiconductor, Inc. Power device structures and methods using empty space zones
JP2019176104A (en) * 2018-03-29 2019-10-10 トヨタ自動車株式会社 Switching element
CN110400843A (en) * 2018-04-24 2019-11-01 半导体元件工业有限责任公司 Transistor and the method for preparing the transistor
EP3621116A1 (en) * 2018-09-06 2020-03-11 Infineon Technologies Austria AG Semiconductor device and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
US8319278B1 (en) * 2009-03-31 2012-11-27 Maxpower Semiconductor, Inc. Power device structures and methods using empty space zones
JP2019176104A (en) * 2018-03-29 2019-10-10 トヨタ自動車株式会社 Switching element
CN110400843A (en) * 2018-04-24 2019-11-01 半导体元件工业有限责任公司 Transistor and the method for preparing the transistor
EP3621116A1 (en) * 2018-09-06 2020-03-11 Infineon Technologies Austria AG Semiconductor device and manufacturing method thereof

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