CN113051208A - Clock control circuit and terminal equipment - Google Patents
Clock control circuit and terminal equipment Download PDFInfo
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- CN113051208A CN113051208A CN202011593804.9A CN202011593804A CN113051208A CN 113051208 A CN113051208 A CN 113051208A CN 202011593804 A CN202011593804 A CN 202011593804A CN 113051208 A CN113051208 A CN 113051208A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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Abstract
The invention discloses a clock control circuit and terminal equipment, wherein the clock control circuit comprises a processor of a server and a desktop platform controller, wherein the BCLK0 of the processor of the server is connected with the CLK-PEGA _ P/N of the desktop platform controller, and the BCLK1 of the processor of the server is connected with the CLK-DMI _ P/N of the desktop platform controller; the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot; the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot; the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN; the LPC-CLK of the desktop platform controller is connected with the SIO chip, and the desktop platform controller can operate without an external clock chip, so that the cost is saved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a clock control circuit and terminal equipment.
Background
The CPU clock circuit of the server is a core part of the system work, and if the clock circuit is not designed reasonably or has defects, the CPU cannot run normally. At present, a clock circuit is designed by schemes such as an external clock, a local clock, a built-in clock and the like. Server platforms typically employ both external clock and local clock schemes. However, in both of the two schemes, a clock chip is required to be added, the price of the clock chip is not low, and the cost is additionally increased, so that the product price is high.
Disclosure of Invention
In view of the above technical problems, the present invention provides a clock control circuit and a terminal device.
The invention provides a clock control circuit, which comprises a processor of a server and a desktop platform controller, wherein the BCLK0 of the processor of the server is connected with the CLK-PEGA _ P/N of the desktop platform controller, and the BCLK1 of the processor of the server is connected with the CLK-DMI _ P/N of the desktop platform controller;
the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot;
the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot;
the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN;
and the LPC-CLK of the desktop platform controller is connected with the SIO chip.
Optionally, the processor of the server is connected to the desktop platform controller through a DMI.
Optionally, the first sending interface of the processor of the server is connected to the second receiving interface of the desktop platform controller, and the first receiving interface of the processor of the server is connected to the second sending interface of the desktop platform controller.
Optionally, the processor of the server further includes a memory channel interface and an expansion bus interface, and the timing interface, the reset interface, and the status indication interface of the processor of the server are connected to the desktop platform controller.
Optionally, the processor of the server is a processor of an Intel E5-16xx v3/v4 or Intel E5-26xx v3/v4 series server.
Optionally, the desktop platform controller is an Intel 8 series chipset, including H81, Q87, Q85, B85, Z87, H87 desktop platform series.
Optionally, the number of the memory channel interfaces of the processor of the server is 1 to 4.
Optionally, the expansion bus interface is a PCIE slot, and the number of the PCIE slots is less than 40.
Optionally, the desktop platform controller includes a SATA interface, a PCIE interface, a LAN interface, a USB interface, and an Audio interface.
The second aspect of the present invention also provides a terminal device, including the clock control circuit of the first aspect.
The embodiment of the invention provides a clock control circuit and terminal equipment, which comprise a processor of a server and a desktop platform controller, wherein the BCLK0 of the processor of the server is connected with the CLK-PEGA _ P/N of the desktop platform controller, and the BCLK1 of the processor of the server is connected with the CLK-DMI _ P/N of the desktop platform controller; the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot; the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot; the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN; the LPC-CLK of the desktop platform controller is connected with the SIO chip, and the desktop platform controller can operate without an external clock chip, so that the cost is saved.
Drawings
FIG. 1 is a schematic diagram of a clock circuit according to an embodiment of the present invention;
FIG. 2 is a diagram of another clock circuit according to an embodiment of the present invention;
FIG. 3 is a diagram of another clock circuit according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the connection of control circuits of a server according to an embodiment of the present invention;
FIG. 5 is a circuit diagram illustrating data communication according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another server control circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the embodiment of the present invention includes: a server control circuit comprises a processor of a server and a desktop platform controller, wherein BCLK0 of the processor of the server is connected with CLK-PEGA _ P/N of the desktop platform controller, and BCLK1 of the processor of the server is connected with CLK-DMI _ P/N of the desktop platform controller;
the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot;
the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot;
the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN;
and the LPC-CLK of the desktop platform controller is connected with the SIO chip.
Specifically, the processor of the server is connected with the desktop platform controller through a direct media interface, the processor of the server further comprises a memory channel interface and an expansion bus interface, and a time sequence interface, a reset interface and a state indication interface of the processor of the server are connected with the desktop platform controller.
Specifically, the controllers of the servers are Intel E5-16xx V3/V4 and E5-26xx V3/V4 series server CPUs, such as LGA2011-R3, which are connected with a 12.5V power supply voltage and connected with the desktop platform controller through a Direct Media Interface (DMI), which is a Direct Media interface (Direct Media interface). DMI is a bus used to connect the north-south bridge of the motherboard, replacing the previous Hub-Link bus. DMI uses point-to-point connection mode, the clock frequency is 100MHz, and the DMI is based on PCI-Express bus, so the DMI has the advantages of PCI-E bus. DMI realizes the data transmission rate of 1GB/s of uplink and downlink, the total bandwidth reaches 2GB/s, and the high-speed interface integrates high-level priority service, and allows concurrent communication and real synchronous transmission capability. The DMI is a2 x 4 interface.
The embodiment of the invention flexibly reserves the DMI data channels of the CPU and the PCH, adopts the DMI AC coupling communication connection mode of the CPU of the server on the scheme, reserves the communication stability between the CPU and the PCH, and is beneficial to the compatibility of the data communication modes between the CPU and the PCH of different platforms.
The method is characterized in that a processing mode of combining PCH collocation and an external circuit is adopted in combination with the characteristics of the CPU of the server, the requirements of the CPU on key signals such as reset and the like during starting and normal work are met, the processor of the server in the embodiment of the invention further comprises a memory channel interface DDR4 and an expansion bus interface PCIe, and a time sequence interface, a reset interface and a state indication interface of the processor of the server are connected with the desktop platform controller.
The embodiment of the invention provides a clock control circuit, which comprises a processor of a server and a desktop platform controller, wherein the BCLK0 of the processor of the server is connected with the CLK-PEGA _ P/N of the desktop platform controller, and the BCLK1 of the processor of the server is connected with the CLK-DMI _ P/N of the desktop platform controller; the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot; the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot; the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN; the LPC-CLK of the desktop platform controller is connected with the SIO chip, and the desktop platform controller can operate without an external clock chip, so that the cost is saved.
The embodiment of the invention also provides a clock control circuit, which comprises a processor of a server and a desktop platform controller, wherein the BCLK0 of the processor of the server is connected with the CLK-PEGA _ P/N of the desktop platform controller, and the BCLK1 of the processor of the server is connected with the CLK-DMI _ P/N of the desktop platform controller;
the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot;
the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot;
the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN;
and the LPC-CLK of the desktop platform controller is connected with the SIO chip.
Specifically, the circuit connection diagram is shown in fig. 2 and 3.
Specifically, the controllers of the servers are Intel E5-16xx V3/V4 and E5-26xx V3/V4 series server CPUs, such as LGA2011-R3, which are connected with a 12.5V power supply voltage and connected with the desktop platform controller through a Direct Media Interface (DMI), which is a Direct Media interface (Direct Media interface). DMI is a bus used to connect the north-south bridge of the motherboard, replacing the previous Hub-Link bus. DMI uses point-to-point connection mode, the clock frequency is 100MHz, and the DMI is based on PCI-Express bus, so the DMI has the advantages of PCI-E bus. DMI realizes the data transmission rate of 1GB/s of uplink and downlink, the total bandwidth reaches 2GB/s, and the high-speed interface integrates high-level priority service, and allows concurrent communication and real synchronous transmission capability. Its basic functionality is completely transparent to the software, so that earlier software can also operate normally.
The DMI is a2 x 4 interface.
As shown in FIG. 4, the processors of the servers are processors of Intel E5-16xx v3/v4 and E5-26xx v3/v4 series servers.
Optionally, the desktop platform controller is an Intel 8 series chipset, including H81, Q87, Q85, B85, Z87, H87 desktop platform series.
Optionally, the processor of the server is connected to the desktop platform controller through a DMI.
Optionally, as shown in fig. 5, a first sending interface of the processor of the server is connected to a second receiving interface of the desktop platform controller, and a first receiving interface of the processor of the server is connected to a second sending interface of the desktop platform controller.
Optionally, as shown in fig. 6, the processor of the server further includes a memory channel interface and an expansion bus interface, and the timing interface, the reset interface, and the status indication interface of the processor of the server are connected to the desktop platform controller.
Optionally, the number of the memory channel interfaces of the processor of the server is 1 to 4.
Optionally, the expansion bus interface is a PCIE slot, and the number of the PCIE slots is less than 40.
Optionally, the desktop platform controller includes a SATA interface, a PCIE interface, a LAN interface, a USB interface, and an Audio interface.
In particular, SATA is an abbreviation for Serial ATA, Serial ATA. It is a computer bus that functions primarily as a data transfer between a motherboard and a large number of storage devices, such as hard disks and optical disk drives. The interface is a novel hard disk interface type completely different from the parallel PATA, and is named after the data is transmitted in a serial mode. The SATA bus uses an embedded clock signal, has stronger error correction capability, and has the biggest difference compared with the prior art that the SATA bus can check transmission instructions (not only data) and automatically correct errors if the errors are found, thereby improving the reliability of data transmission to a great extent. The serial interface also has the advantages of simple structure and hot plug support.
PCI-express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard intended to replace the older PCI, PCI-X and AGP bus standards.
PCIe belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, connected devices distribute independent channel bandwidth and do not share bus bandwidth, and the PCIe mainly supports functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS) and the like.
LAN: local Area Network, which connects various computers, external devices and databases in a certain Area to form a computer communication Network, and is connected with Local Area networks or databases in other places through a special data line to form a wider information processing system. The local area network connects network interconnection equipment such as a network server, a network workstation, a printer and the like through a network transmission medium, and communication services such as system management files, shared application software, office equipment, work schedule sending and the like are realized. The local area network is a closed network, can prevent information leakage and external network virus attack to a certain extent, and has higher safety.
USB: the abbreviation Universal Serial Bus (usb) is an external Bus standard used to standardize the connection and communication between computers and external devices. Is an interface technology applied in the field of PC. Universal Serial Bus (USB) is an emerging data communication approach that is gradually replacing other interface standards. The USB bus is taken as a high-speed serial bus, the application environment requirement of high-speed data transmission can be met by the extremely high transmission speed of the USB bus, the USB bus also has the advantages of simple power supply (bus power supply), convenient installation and configuration (supporting plug and play and hot plug), simple expansion ports (127 peripheral devices can be expanded at most through a concentrator), diversified transmission modes (4 transmission modes), good compatibility (downward compatibility after product upgrading), and the like, the USB bus has the advantages of high transmission speed, convenience in use, hot plug support, flexible connection, independent power supply and the like, a keyboard, a mouse, various peripheral devices such as a large-capacity storage device and the like can be connected, and the interface is also widely used in smart phones. The interaction between the intelligent devices such as the computer and the external data is mainly based on a network and a USB interface.
Audio: an audio interface.
The embodiment of the invention flexibly reserves the DMI data channels of the CPU and the PCH, adopts the DMI AC coupling communication connection mode of the CPU of the server on the scheme, reserves the communication stability between the CPU and the PCH, and is beneficial to the compatibility of the data communication modes between the CPU and the PCH of different platforms.
Specifically, as shown in fig. 2, a first sending interface TX of the processor of the server is connected to a second receiving interface RX of the desktop platform controller, and the first receiving interface RX of the processor of the server is connected to the second sending interface TX of the desktop platform controller.
As shown in fig. 3, in combination with the characteristics of the CPU operation of the server, a processing mode combining PCH collocation and an external circuit is adopted, so as to meet the requirements of the CPU on key signals such as reset during startup and normal operation.
As shown in fig. 4-6, BCLK0 of the server's processor is coupled to CLK-PEGA _ P/N of the desktop platform controller, BCLK1 of the server's processor is coupled to CLK-DMI _ P/N of the desktop platform controller.
Specifically, the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot;
the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot;
the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN;
and the LPC-CLK of the desktop platform controller is connected with the SIO chip. The super input/output chip (SIO) is generally located at the lower left or upper left of the motherboard. The chips mainly used are Winbond and ITE, and the chips provide control processing functions for standard I/O interfaces on a mainboard.
The embodiment of the invention provides a clock control circuit, which comprises a processor of a server and a desktop platform controller, wherein the BCLK0 of the processor of the server is connected with the CLK-PEGA _ P/N of the desktop platform controller, and the BCLK1 of the processor of the server is connected with the CLK-DMI _ P/N of the desktop platform controller; the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot; the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot; the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN; the LPC-CLK of the desktop platform controller is connected with the SIO chip, and the desktop platform controller can operate without an external clock chip, so that the cost is saved.
The invention also provides terminal equipment comprising the server control circuit.
The embodiment of the invention provides terminal equipment, which comprises a processor of a server and a desktop platform controller, wherein the BCLK0 of the processor of the server is connected with the CLK-PEGA _ P/N of the desktop platform controller, and the BCLK1 of the processor of the server is connected with the CLK-DMI _ P/N of the desktop platform controller; the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot; the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot; the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN; the LPC-CLK of the desktop platform controller is connected with the SIO chip, and the desktop platform controller can operate without an external clock chip, so that the cost is saved.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A clock control circuit, comprising a processor of a server and a desktop platform controller, wherein BCLK0 of the processor of the server is connected with CLK-PEGA _ P/N of the desktop platform controller, and BCLK1 of the processor of the server is connected with CLK-DMI _ P/N of the desktop platform controller;
the CLK-PEGA _ P/N of the desktop platform controller is connected with the PCIE-X16 slot;
the CLK-PE1_ P/N of the desktop platform controller is connected with the PCIE-X1 slot;
the CLK-PE2_ P/N of the desktop platform controller is connected with the PCIE-LAN;
and the LPC-CLK of the desktop platform controller is connected with the SIO chip.
2. The clock control circuit of claim 1, wherein the server processor is coupled to the desktop platform controller via a DMI.
3. The clock control circuit of claim 2, wherein the first sending interface of the processor of the server is connected to the second receiving interface of the desktop platform controller, and the first receiving interface of the processor of the server is connected to the second sending interface of the desktop platform controller.
4. The clock control circuit of claim 1, wherein the processor of the server further comprises a memory channel interface and an expansion bus interface, and the timing interface, the reset interface and the status indication interface of the processor of the server are connected to the desktop platform controller.
5. The clock control circuit of claim 1, wherein the processor of the server is a processor of an Intel E5-16xx v3/v4 or an Intel E5-26xx v3/v4 family server.
6. The clock control circuit of claim 1, wherein the desktop platform controller is an Intel 8 family chipset comprising a family of H81, Q87, Q85, B85, Z87, H87 desktop platforms.
7. The clock control circuit of claim 1, wherein the number of memory channel interfaces of the processor of the server is 1-4.
8. The clock control circuit of claim 1, wherein the expansion bus interface is a PCIE slot, and the number of PCIE slots is less than 40.
9. The clock control circuit of claim 1, wherein the desktop platform controller comprises a SATA interface, a PCIE interface, a LAN interface, a USB interface, and an Audio interface.
10. A terminal device, characterized in that it comprises a clock control circuit according to any one of claims 1 to 9.
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