CN112951533A - 一种高压压敏电阻的制备方法及高压压敏电阻 - Google Patents

一种高压压敏电阻的制备方法及高压压敏电阻 Download PDF

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CN112951533A
CN112951533A CN201911256478.XA CN201911256478A CN112951533A CN 112951533 A CN112951533 A CN 112951533A CN 201911256478 A CN201911256478 A CN 201911256478A CN 112951533 A CN112951533 A CN 112951533A
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piezoresistor
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CN112951533B (zh
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罗万先
鲁信勇
吴浩
曹金南
梁树坚
彭高东
王小燕
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Guangzhou Chuangtian Electronic Technology Co ltd
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Abstract

本发明提供一种高压压敏电阻的制备方法，该方法生产的压敏电阻具有高电压梯度为1400V/mm，由于电压梯度越高，所以压敏电阻的体积越小，故该方法生产的压敏电阻体积小，可以实现相同电压下减小压敏电阻重量，减小体积和占地面积，实现轻量化、小型化。同时还具有非线性系数为50；漏电流为5μA；使用寿命大于1000h等特性。尤其是其电压值得到了显著提高，能够满足高电压压敏电阻的使用要求。同时本发明产品的烧结温度可降为900℃～950℃的低温烧结，比现有技术低100℃以上，有利于节能降耗。该高压压敏电阻的制备方法生产的高压压敏电阻综合性能高，电压范围广，性能稳定，易于产业化生产。

Description

一种高压压敏电阻的制备方法及高压压敏电阻
技术领域
本发明属于电子元器件领域，尤其涉及一种高压压敏电阻的制备方法及高压压敏电阻。
背景技术
压敏电阻器具有特殊的非线性电流～电压特性，使用中一旦发生异常状况,比如电源线路遭遇雷击、强电磁场干扰、电源开关频繁动作、电源系统故障,使得线路上电压突增,超过氧化锌压敏电阻器的导通电压，就会进入导通区，此时电流和电压呈非线性关系,一般称之为非线性系数(Nonl inearity Parameter),其值可达数十或上百。此时,压敏电阻器的阻抗会急剧下降,仅有几个欧姆,使过电压形成突波电流流出,泄放过电压的能量,藉以保护所连接的各类高低压配电,变电设备。其作为电路中浪涌保护最佳元件和ESD防护首选的元件的多层片式压敏电阻器也得到了广泛的应用。
传统的压敏电阻，由于其电压梯度较低，大电流特性差，静电容量小,响应速度慢,限制了它的使用，所以在空气中长期使用易发生老化面使性能蜕变,尤其限制了其在高压条件下的使用性能要求。然而高压压敏电阻的电压梯度比普通压敏电阻的高很多，可以实现相同电压下减小压敏电阻重量，减小体积和占地面积，实现轻量化、小型化。所以生产制造一种高压压敏电阻很有必要。
发明内容
本发明目的在于解决传统的压敏电阻电压梯度较低，大电流特性差，达不到高压条件下的使用性能要求等问题，提供了一种在高压条件下性能好，电位梯度高的高压压敏电阻。
为达此目的，本发明提供了一种高压压敏电阻的制备方法，包括配料、球磨、流延、丝印、层压、切割、排胶、烧结、倒角、封端、烧端、电镀、测试工序，所述的配料是将以下小料按下述重量百分比配置：三氧化二铋(Bi2O3)：1％～7％、三氧化锑(Sb2O3)：0.5％～15％、碳酸钴(CoCO3)：0.5％～15％、二氧化锰(MnO2)：0.2％～1％、氧化镧(La2O3)：0.2％～1％、五氧化二铌(Nb2O5)：0.0005％～6％、氧化钇(Y2O3)：0.5％～2％、氧化铬(Cr2O3)：0.6％～1.2％、二氧化硅(SiO2)：0.0005％～5％、氧化铝(Al2O3)：0.0005％～8％、氧化镍(NiO)：0.1％～5％；配置完成后，上述小料进行混合球磨，之后选取主材料氧化锌(ZnO)按70％～95％的重量百分比配比，再将主材料氧化锌(ZnO)与混合球磨后的小料球磨。
优选的，所述的烧结工序中在900℃～950℃温度下，烧结2～3小时。
优选的，所述配料混合均匀后在氧化铝坩埚中于600℃～800℃的温度下融化1～3小时。
一种高压压敏电阻，其包含一叠层烧结体以及分别设置于所述叠层烧结体相对的两个表面上的电极，所述叠层烧结体外表面上设置一第一外部电极以及与所述第一外部电极对称设置的一第二外部电极，所述高压压敏电阻采用上述任意一项所述的高压压敏电阻的制备方法制得。
优选的，所述叠层烧结体包含一上基板、与所述上基板相对的一下基板，设在所述上基板和所述下基板之间的一压敏电阻基片，所述压敏电阻基片包括：叠层设置的至少一个第一分离内部电极、与所述第一分离内部电极对称设置的至少一个第二分离内部电极、至少一个不连接型内部电极以及至少四个压敏电阻单元；所述第一分离内部电极及第二分离内部电极均沿一叠层方向均匀分布，所述第一分离内部电极的一第一端与所述第一外部电极电气连接，所述第二分离内部电极一第一端与所述第二外部电极电气连接，所述第一分离内部电极的一第二端与所述第二分离内部电极的一第二端具有间隙；所述不连接型内部电极沿所述压敏电阻基片的一叠层方向设置，该不连接型内部电极与所述第一分离内部电极、第二分离内部电极之间设置有所述压敏电阻单元，并且所述不连接型内部电极不与所述第一外部电极和所述第二外部电极相连接；所述压敏电阻单元沿所述压敏电阻基片的一叠层方向叠层设置于所述上基板以及所述下基板之间。
进一步的，所述第一分离内部电极、所述第二分离内部电极以及所述不连接型内部电极的材料组分及其重量百分比皆为:银(Ag)：70％～100％，钯(Pd)：0％～30％。
进一步的，所述压敏电阻基片分别叠层设置的所述第一分离内部电极与所述第二分离内部电极为两个，所述不连接型内部电极为一个。
优选的，所述第一外部电极与所述第二外部电极皆包括两层，内部为银层、外部为镍锡层，使得导电性能更好。
与现有技术相比，本发明具有如下有益效果：本发明提供一种高压压敏电阻的制备方法，该方法生产的压敏电阻具有高电压梯度为1400V/mm，由于电压梯度越高，所以压敏电阻的体积越小，故该方法生产的压敏电阻体积小，可以实现相同电压下减小压敏电阻重量，减小体积和占地面积，实现轻量化、小型化。同时还具有非线性系数为50；漏电流为5μA；使用寿命大于1000h等特性。其综合性能高，工作电压范围广，性能稳定，易于产业化生产。尤其是其电压值得到了显著提高，能够满足高电压压敏电阻的使用要求。同时本发明产品的烧结温度可降为900℃～950℃的低温烧结，比现有技术低100℃以上，有利于节能降耗。且本发明中的压敏电阻由于内电极银浆的膨胀系数比ZnO要大，因而两者之间的匹配性较差，通过在银浆体系中添加钯(Pd)：0％～30％，有助于减小银浆的膨胀系数，从而保证两者的收缩率及膨胀系数的一致性，防止银层与压敏电阻基片出现分离现象，实现银层与压敏电阻基片紧密结合，提高产品的整体性能。
附图说明
图1是本发明第一实施例提供的高压压敏电阻的结构剖面示意图。
具体实施方式
下面所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参阅图1，
本发明提供一种高压压敏电阻的制备方法，包括配料、球磨、流延、丝印、层压、切割、排胶、烧结、倒角、封端、烧端、电镀、测试工序。其具体步骤如下：
选取三氧化二铋(Bi2O3)：1％～7％、三氧化锑(Sb2O3)：0.5％～15％、碳酸钴(CoCO3)：0.5％～15％、二氧化锰(MnO2)：0.2％～1％、氧化镧(La2O3)：0.2％～1％、五氧化二铌(Nb2O5)：0.0005％～6％、氧化钇(Y2O3)：0.5％～2％、氧化铬(Cr2O3)：0.6％～1.2％、二氧化硅(SiO2)：0.0005％～5％、氧化铝(Al2O3)：0.0005％～8％、氧化镍(NiO)：0.1％～5％；将上述小料按上述重量百分比配料。配料完成后，再将上述小料混合球磨，之后选取主材料氧化锌(ZnO)按70％～95％的重量百分比配比后，再将主材料氧化锌(ZnO)与混合球磨后的小料球磨。
将压敏电阻膜浆料采用包括流延、印刷方式制作基片下基板的单层压敏电阻膜；两端部将内电极银钯浆料采用印刷方式在下基板上制作设定图案的内电极；将内电极银钯浆料采用包括烘干、晾干方式干燥；
在有设定图案的内电极表面采用包括流延、印刷方式制作中间单层压敏电阻膜；根据压敏电阻基片中内电极图案的个数重复以上步骤继续制作内电极、中间单层压敏电阻膜；
最后将压敏电阻膜浆料采用包括流延、印刷方式在上述叠层的表面制作基片上基板的单层压敏电阻膜；
将层压后的压敏电阻基片切割成符合产品标准外形尺寸，制成单只压敏电阻基片；
将切割后的压敏电阻基片放置在排胶炉内排除其中的有机成分；
将排胶后的压敏电阻基片放置在烧结炉内烧结成瓷体，烧结温度为900℃～950℃温度下，烧结2～3小时；
将烧结后的压敏电阻基片的角落处进行倒角操作；
将倒角后的单只压敏电阻基片两端部位表面采用浸渍沾银方式涂覆电极浆料封端制作封端电极；
将制作的两端电极依次电镀镍、锡，即制得成品；
对制得的成品进行测试工序。
本发明还提供了一种高压压敏电阻，其由上述制备方法制得，其包含一叠层烧结体1、设置在所述叠层烧结体外表面上的一第一外部电极2以及与所述第一外部电极对称设置的一第二外部电极3；所述叠层烧结体包含一上基板11、与所述上基板11相对的一下基板12，设在所述上基板11和所述下基板12之间的一压敏电阻基片13，所述压敏电阻基片13包括：叠层设置的至少一个第一分离内部电极131、与所述第一分离内部电极对称设置的至少一个第二分离内部电极132、至少一个不连接型内部电极133以及至少四个压敏电阻单元134；其中所述压敏电阻单元通过所述第一外部电极2与所述第二外部电极3构成并联形式。
所述第一分离内部电极131及第二分离内部电极132均沿一叠层方向均匀分布，所述第一分离内部电极131的一第一端与所述第一外部电极电气2连接，所述第二分离内部电极132一第一端与所述第二外部电极3电气连接，所述第一分离内部电极131的一第二端与所述第二分离内部电极132的一第二端具有间隙；所述不连接型内部电极133沿所述压敏电阻基片13的一叠层方向设置，该不连接型内部电极133与所述第一分离内部电极131、第二分离内部电极132之间设置有所述压敏电阻单元134，并且所述不连接型内部电极133不与所述第一外部电极131和所述第二外部电极132相连接；所述第一分离内部电极131与所述第二分离内部电极132两者串联后再与所述不连接型内部电极133构成并联形式。所述压敏电阻单元134沿所述压敏电阻基片13的一叠层方向叠层设置于所述上基板11以及所述下基板12之间；
所述第一分离内部电极131、所述第二分离内部电极132以及所述不连接型内部电极133的材料组分及其重量百分比皆为:银(Ag)：70％～100％，钯(Pd)：0％～30％。
所述第一外部电极2与所述第二外部电极3皆包括两层，内部为银层、外部为镍锡层，使得导电性能更好。
所述压敏电阻基片13分别叠层设置所述第一分离内部电极131与所述第二分离内部电极132为两个，所述不连接型内部电极133为一个。
本实施例中，所述高压压敏电阻的尺寸优选为2.0mm乘1.2mm或4.7mm乘3.20mm，由于电压梯度为1400V/mm，所以2.0mm乘1.2mm的最大压敏电压值可到达470V，4.7mm乘3.20mm的耐最大压力值可到达680V，较于市面上的压敏电阻进步明显。当然，高压压敏电阻的尺寸也可根据设计要求进行制作。
本发明提供的高压压敏电阻的制备方法，该方法生产的压敏电阻具有高电压梯度为1400V/mm，由于电压梯度越高，所以压敏电阻的体积越小，故该方法生产的压敏电阻体积小，可以实现相同电压下减小压敏电阻重量，减小体积和占地面积，实现轻量化、小型化。同时还具有非线性系数为50；漏电流为5μA；使用寿命大于1000h等特性。其综合性能高，工作电压范围大，性能稳定，易于产业化生产。尤其是其电压值得到了显著提高，能够满足高电压压敏电阻的使用要求。同时本发明产品的烧结温度可降为900℃～950℃的低温烧结，比现有技术低100℃以上，有利于节能降耗。且本发明中的压敏电阻由于内电极银浆的膨胀系数比ZnO要大，因而两者之间的匹配性较差，通过在银浆体系中添加钯(Pd)：0％～30％，有助于减小银浆的膨胀系数，从而保证两者的收缩率及膨胀系数的一致性，防止银层与压敏电阻基片出现分离现象，实现银层与压敏电阻基片紧密结合，提高产品的整体性能。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明申请专利范围所作的等同变化，仍属本发明所涵盖的范围。

Claims (8)

1.一种高压压敏电阻的制备方法，包括配料、球磨、流延、丝印、层压、切割、排胶、烧结、倒角、封端、烧端、电镀、测试工序，其特征在于：所述的配料是将以下小料按下述重量百分比配置：三氧化二铋(Bi2O3)：1％～7％、三氧化锑(Sb2O3)：0.5％～15％、碳酸钴(CoCO3)：0.5％～15％、二氧化锰(MnO2)：0.2％～1％、氧化镧(La2O3)：0.2％～1％、五氧化二铌(Nb2O5)：0.0005％～6％、氧化钇(Y2O3)：0.5％～2％、氧化铬(Cr2O3)：0.6％～1.2％、二氧化硅(SiO2)：0.0005％～5％、氧化铝(Al2O3)：0.0005％～8％、氧化镍(NiO)：0.1％～5％；配置完成后，上述小料进行混合球磨，之后选取主材料氧化锌(ZnO)按70％～95％的重量百分比配比，再将主材料氧化锌(ZnO)与混合球磨后的小料球磨。
2.如权利要求1所述的高压压敏电阻的制备方法，其特征在于，所述的烧结工序中在900℃～950℃温度下，烧结2～3小时。
3.如权利要求1所述的高压压敏电阻的制备方法，其特征在于，所述配料混合均匀后在氧化铝坩埚中于600℃～800℃的温度下融化1～3小时。
4.一种高压压敏电阻，其包含一叠层烧结体以及分别设置于所述叠层烧结体相对的两个表面上的电极，所述叠层烧结体外表面上设置一第一外部电极以及与所述第一外部电极对称设置的一第二外部电极，其特性在于，所述高压压敏电阻采用权利要求1～3中任意一项所述的高压压敏电阻的制备方法制得。
5.如权利要求4所述的高压压敏电阻，其特征在于，所述叠层烧结体包含一上基板、与所述上基板相对的一下基板，设在所述上基板和所述下基板之间的一压敏电阻基片，所述压敏电阻基片包括：叠层设置的至少一个第一分离内部电极、与所述第一分离内部电极对称设置的至少一个第二分离内部电极、至少一个不连接型内部电极以及至少四个压敏电阻单元；所述第一分离内部电极及第二分离内部电极均沿一叠层方向均匀分布，所述第一分离内部电极的一第一端与所述第一外部电极电气连接，所述第二分离内部电极一第一端与所述第二外部电极电气连接，所述第一分离内部电极的一第二端与所述第二分离内部电极的一第二端具有间隙；所述不连接型内部电极沿所述压敏电阻基片的一叠层方向设置，该不连接型内部电极与所述第一分离内部电极、第二分离内部电极之间设置有所述压敏电阻单元，并且所述不连接型内部电极不与所述第一外部电极和所述第二外部电极相连接；所述压敏电阻单元沿所述压敏电阻基片的一叠层方向叠层设置于所述上基板以及所述下基板之间。
6.如权利要求5所述的高压压敏电阻，其特征在于所述第一分离内部电极、所述第二分离内部电极以及所述不连接型内部电极的材料组分及其重量百分比皆为:银(Ag)：70％～100％，钯(Pd)：0％～30％。
7.如权利要求5所述的高压压敏电阻，其特征在于所述压敏电阻基片分别叠层设置所述第一分离内部电极与所述第二分离内部电极为两个，所述不连接型内部电极为一个。
8.如权利要求4所述的高压压敏电阻，其特征在于所述第一外部电极与所述第二外部电极皆包括两层，内部为银层、外部为镍锡层。
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