CN112908979A - 电子装置封装及其制造方法 - Google Patents

电子装置封装及其制造方法 Download PDF

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Publication number
CN112908979A
CN112908979A CN202010222639.XA CN202010222639A CN112908979A CN 112908979 A CN112908979 A CN 112908979A CN 202010222639 A CN202010222639 A CN 202010222639A CN 112908979 A CN112908979 A CN 112908979A
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semiconductor die
substrate
electronic device
device package
disposed
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CN202010222639.XA
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吕美如
林桎苇
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112908979A publication Critical patent/CN112908979A/zh
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Abstract

一种电子装置封装和其制造方法。电子装置封装包含衬底、第一半导体裸片、第二半导体裸片以及囊封物。所述衬底包含第一表面以及与所述第一表面相对的第二表面。所述衬底限定从所述第一表面凹陷的腔室。所述第一半导体裸片安置在所述腔室中。所述第二半导体裸片安置在所述第一半导体裸片上方并且电连接到所述第一半导体裸片。所述囊封物安置在所述衬底的所述腔室中。所述囊封物囊封所述第一半导体裸片的第一侧壁，并且暴露所述第一半导体裸片的第二侧壁。

Description

电子装置封装及其制造方法
技术领域
本发明涉及用于高速信号传输的电子装置封装及其制造方法。
背景技术
芯片上芯片(chip-on-chip,CoC)封装包含堆叠于彼此之上的两个电子组件。经堆叠的电子组件通过导线结合彼此电连通。然而，接合导线具有高电阻以及长传输路径。因此，CoC封装遭受信号完整性，尤其是在高频应用中。另外，常规的导线结合信号传输的限制在于由冗长传输路径所引起的高阻抗缓慢地防止实现速度数据速率，例如，100Gbit/s、400Gbit/s，或1.6Tbit/s。另外，硅光子和光学引擎通常需要高速数据速率结合至少一个电子IC(EIC)与光子IC(PIC)的集成。
发明内容
在一些实施例中，电子装置封装包含衬底、第一半导体裸片、第二半导体裸片以及囊封物。衬底包含第一表面以及与第一表面相对的第二表面。衬底限定从第一表面凹陷的腔室。第一半导体裸片安置在腔室中。第二半导体裸片安置在第一半导体裸片上方并且电连接到第一半导体裸片。囊封物安置在衬底的腔室中。囊封物囊封第一半导体裸片的第一侧壁，并且暴露第一半导体裸片的第二侧壁。
在一些实施例中，电子装置封装包含衬底、光子IC、电子IC以及导电穿通孔。衬底包含第一顶部表面、低于第一顶部表面的第二顶部表面，以及与第一顶部表面和第二顶部表面相对的底部表面。光子IC安置在衬底的第二顶部表面上，并且光子IC包含至少一个暴露的侧壁。电子IC安置在光子IC上方并且电连接到光子IC。导电穿通孔从衬底的第一顶部表面延伸到衬底的底部表面。
在一些实施例中，一种制造电子装置封装的方法包含以下操作。提供衬底。衬底从第一表面凹陷以形成腔室。第一半导体裸片安置在腔室中。囊封物形成在腔室中以囊封第一半导体裸片的侧壁。第二半导体裸片安置在囊封物上。囊封物和衬底被沿着第一半导体裸片的侧壁切割以暴露第一半导体裸片的侧壁。
附图说明
当结合附图阅读时，从以下详细描述容易理解本发明的一些实施例的方面。各种结构可能未按比例绘制，且各种结构的尺寸可出于论述的清楚起见任意增大或减小。
图1是根据本发明的一些实施例的电子装置封装的示意性俯视图。
图1A是根据本发明的一些实施例沿着图1中的线A-A'截取的电子装置封装的示意性截面图。
图2是根据本发明的一些实施例的电子装置封装的示意性截面图。
图3是根据本发明的一些实施例的电子装置封装的示意性截面图。
图4是根据本发明的一些实施例的电子装置封装的示意性截面图。
图5是根据本发明的一些实施例的电子装置封装的示意性截面图。
图6是根据本发明的一些实施例的电子装置封装的示意性截面图。
图7A、图7B、图7C、图7D、图7E、图7F、图7G、图7H和图7I说明根据本发明的一些实施例的制造电子装置封装的操作。
具体实施方式
以下公开内容提供用于实施所提供的标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例来解释本发明的某些方面。当然，这些仅是实例且并不意图是限制性的。举例来说，在以下描述中，第一特征形成于第二特征上方或上可包含其中第一特征和第二特征形成或安置成直接接触的实施例，且也可包含其中额外特征形成或安置在第一特征与第二特征之间使得第一特征和第二特征并不直接接触的实施例。另外，本发明可能在各种实例中重复参考标号和/或字母。此重复是出于简单和清楚的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
如本文中所使用，空间相对术语，例如，“在……下方”、“下方”、“上方”、“在……上方”、“在……上”、“上部”、“下部”、“左侧”、“右侧”、“垂直”、“水平”、“侧面”及类似者，可以在本文中为易于描述而使用以如图中所说明的描述一个元件或特征与另一个元件或特征的关系。除了图中所描绘的定向之外，空间相对术语意图涵盖在使用或操作中的装置的不同定向。装置可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相对描述词可同样地相应地进行解释。应理解，当一个元件被称作“连接到”或“耦合到”另一元件时，其可直接地连接或耦合到另一元件，或可存在中间元件。
如本文中所使用，术语“有源表面”可以指上面安置有例如接触衬垫的接触端子的电子组件的表面，并且术语“无源表面”可以指上面没有安置接触端子的与有源表面相反的电子组件的另一表面。
本发明的一些实施例提供了实现高速信号传输(例如，大于400Gbit/s)的扇出叠层封装半导体封装结构。首先将电信号中的至少一个发送到电子IC(EIC)以供放大，并且随后到达光子IC(PIC)。举例来说，EIC可包含有源半导体装置和无源电路组件两者，以及以电路关系互连有源半导体装置和无源电路组件以执行所期望的子电路控制功能的导电路径。PIC可在单个衬底上包含电路中的光子装置的组合以实现所期望的功能。举例来说，PIC可在单个衬底上包含激光器、接收器、波导、检测器、半导体光学放大器(semiconductoroptical amplifier,SOA)、格柵，以及其它有源和无源半导体光学装置。信号传输路径在封装中被设计成具有合适的阻抗，允许前述高速信号传输。在一些实施例中，举例来说，高速信号可拥有约100Gbit/s、400Gbit/s或1.6Tbit/s的数据速率。
图1是根据本发明的一些实施例的电子装置封装1的示意性俯视图。图1A是根据本发明的一些实施例沿着图1中的线A-A'截取的电子装置封装1的示意性截面图。出于清楚的目的，一些组件可能并未在图1中示出。如图1和图1A中所示，电子装置封装1包含衬底10、第一半导体裸片30、第二半导体裸片60和囊封物40。衬底10可包含但不限于半导体衬底，例如，硅衬底。衬底10包含第一表面10T和与第一表面10T相对的第二表面10B。借助于实例，第一表面10T可以是顶部表面，并且第二表面10B可以是底部表面。衬底10限定从第一表面10T凹陷的腔室10C。换句话说，衬底10的第一表面10T包含第一顶部表面10T1以及从第一顶部表面10T1凹陷并且低于第一顶部表面10T1的第二顶部表面10T2。腔室10C从第一表面10T凹陷而不穿透衬底10。确切地说，腔室10C的底部受到衬底10的限制，并且腔室10C的顶部从衬底10暴露。在一些实施例中，腔室10C的侧面的一部分受到衬底10的限制，而腔室10C的侧面的另一部分从衬底10暴露。借助于实例，腔室10C的三个侧面受到衬底10的限制，并且腔室10C的一个侧面从衬底10暴露，如图1中所说明。在一些实施例中，例如氧化硅薄膜的绝缘薄膜12可以安置在衬底10的第一表面10T的第一顶部表面10T1和/或第二顶部表面10T2上，并且可以安置在第一半导体裸片30与衬底10之间。
第一半导体裸片30安置在腔室10C中，并且第二半导体裸片60安置在第一半导体裸片30上方并且电连接到第一半导体裸片30。第二半导体裸片60安置在腔室10C外部。第一半导体裸片30和第二半导体裸片60可包含不同类型的裸片或芯片以用于提供不同的功能。借助于实例，第一半导体裸片30可包含光子IC(PIC)，并且第二半导体裸片60可包含电子IC(EIC)。在一些实施例中，第一半导体裸片30通过例如裸片附接薄膜(die attaching film,DAF)的粘合剂层14附接到腔室10C的底部，其中第一无源表面30B面向衬底10，而具有例如第一半导体裸片30的接触衬垫的电端子30P的第一有源表面30A面向上方。在一些实施例中，第一半导体裸片30的厚度T1小于或基本上等于腔室10C的深度D。在一些实施例中，电端子30P的上表面可以基本上与衬底10的第一顶部表面10T1齐平。
在一些实施例中，第一半导体裸片30的第一有源表面30A面向第二有源表面60A，所述第二有源表面具有例如第二半导体裸片60的接触衬垫的电端子60P。
囊封物40安置在衬底10的腔室10C中。囊封物40可包含例如环氧树脂的模制化合物，且例如氧化硅填充物的填充物可填充在模制化合物中。囊封物40囊封第一半导体裸片30的侧壁的一部分，并且暴露第一半导体裸片30的侧壁的另一部分。借助于实例，囊封物40囊封第一半导体裸片的第一侧壁(覆盖的侧壁)301，并且暴露第一半导体裸片30的第二侧壁(暴露的侧壁)302。在一些实施例中，三个第一侧壁301由囊封物40覆盖，并且一个第二侧壁302从囊封物40暴露。暴露的第二侧壁302可经配置以允许第一半导体裸片30电耦合到外部组件。借助于实例，在第一半导体裸片30是光子IC的情况下暴露的第二侧壁302可以光学耦合到光纤。在一些实施例中，囊封物40的边缘40E可以与第一半导体裸片30的第二侧壁302基本上共面。在一些实施例中，囊封物40可以进一步部分地囊封第一半导体裸片30的第一有源表面30A，并且电端子30P可以从囊封物40暴露。在一些实施例中，囊封物40覆盖在腔室10C中的第二顶部表面10T2或绝缘薄膜12(如果存在的话)，并且暴露衬底10的第一顶部表面10T1。在一些实施例中，囊封物40可以基本上与第一顶表面10T1或绝缘薄膜12(如果存在的话)齐平。
在一些实施例中，电子装置封装1可以进一步包含安置在衬底10的第一表面10T与第二半导体裸片之间并且电连接到第一半导体裸片30和第二半导体裸片60的第一再分布层(RDL)50。在一些实施例中，第二半导体裸片60的电端子60P可以通过导电结构62接合到第一RDL 50。导电结构62可包含例如焊料凸块的导电凸块、例如焊料球的导电球或类似者。第一RDL 50可包含堆叠在彼此之上的一或多个绝缘层52以及一或多个导电层54。绝缘层52的材料各自可包含例如环氧树脂、聚酰亚胺、双马来酰亚胺-三嗪(BT)树脂的有机绝缘材料，例如氧化硅、氮化硅的无机绝缘材料，或其组合。导电层54各自可包含导电迹线、导电通孔、导电衬垫或其组合。导电层54的材料各自可包含金属，例如，铜(Cu)、铝(Al)或类似者。在一些实施例中，电子装置封装1可以进一步包含安置在第一RDL 50上且电连接到第一RDL50的无源组件56，例如，电阻器、电容器、电感器或其组合56。在一些实施例中，绝缘层52的热膨胀系数(coefficient of thermal expansion,CTE)不同于囊封物40的热膨胀系数。
在一些实施例中，电子装置封装1可以进一步包含安置在衬底10的第二表面10B上的第二RDL 70。第二RDL 70可包含堆叠在彼此之上的一或多个绝缘层72和一或多个导电层74。绝缘层72的材料各自可包含例如环氧树脂、聚酰亚胺、双马来酰亚胺-三嗪(BT)树脂的有机绝缘材料，例如氧化硅、氮化硅的无机绝缘材料，或其组合。导电层74各自可包含导电迹线、导电通孔、导电衬垫或其组合。导电层74的材料各自可包含金属，例如，铜(Cu)、铝(Al)或类似者。在一些实施例中，电子装置封装1可以进一步包含多个电导体76，所述多个电导体安置在第二RDL 70上且电连接到第二RDL 70并且经配置以电连接例如印刷电路板(PCB)的外部电子组件。电导体可包含例如焊料凸块的导电凸块、例如焊料球的导电球或类似者。在一些实施例中，绝缘层72的CTE不同于囊封物40的CTE。
第一RDL 50和第二RDL 70各自可包含凸块水平RDL或衬底水平RDL。借助于实例，第一RDL 50和/或第二RDL 70的线宽/间距(L/S)可以在约2μm(micrometer)/约2μm与约10μm/约10μm之间或与约10μm/约10μm相比更宽。
在一些实施例中，电子装置封装1可以进一步包含多个导电穿通孔20，所述多个导电穿通孔从衬底10的第一表面10T延伸到衬底10的第二表面10B，并且将第一RDL 50电连接到第二RDL 70。导电穿通孔20可以相应地填充在衬底10的穿孔10H中。在一些实施例中，导电穿通孔20的高度H基本上等于衬底10的厚度T。导电层74的材料可包含金属，例如，铜(Cu)或类似者。导电穿通孔20中的每一个可包含一体形成的结构，或者可以通过多个导电件堆叠。绝缘薄膜12可以延伸到穿孔10H并且可以安置在衬底10与导电穿通孔20之间，并且经配置为粘合剂层或屏障层。在一些实施例中，晶种层(未示出)可以安置在导电穿通孔20与衬底10之间。
在本发明的一些实施例中，第一半导体裸片30裸片到裸片接合到第二半导体裸片60，并且第一RDL 50可经配置为在第一半导体裸片30与第二半导体裸片60之间的扇出结构。因此，电连接路径P可以穿过第一RDL 50建立在第一半导体裸片30与第二半导体裸片60之间。第一RDL 50与接合导线相比在电阻上较低，并且使用第一RDL 50的裸片到裸片接合可以缩短在第一半导体裸片30与第二半导体裸片60之间的传输路径。相应地，可以缓解感应作用和信号完整性问题，尤其是在高频应用中。第一半导体裸片30安置在衬底10的腔室10C中，并且因此可以减小电子装置封装1的整体厚度。此外，囊封物40安置在腔室10C中以囊封第一半导体裸片30，并且囊封物40定位在腔室10C的侧面与半导体裸片30的第一侧壁301之间的微小备用空间中。相应地，可以极大地减少囊封物40的量。囊封物40的量减少可以极大地缓解由于囊封物40与第一RDL 50的绝缘层52之间的CTE不匹配造成的弯曲问题，并且因此可以改进电子装置封装1的可靠性。导电穿通孔20可包含例如硅穿孔的高密度穿通孔以满足高I/O需求。并且，导电穿通孔20在电阻上较低并且可以在第一RDL 50与第二RDL 70之间形成短电气路径以满足高速信号传输需求。
本发明的电子装置封装和制造方法不限于上文所描述的实施例，且可根据其它实施例来实施。为了简化描述且出于方便在本发明的各种实施例之间进行比较，以下实施例中的类似组件标记有相同标号，且可能并不过多地加以描述。
图2是根据本发明的一些实施例的电子装置封装2的示意性截面图。如图2中所示，电子装置封装2的第一半导体裸片30可以是具有波导层32的光子IC。波导层32可以安置成接近于第一有源表面30A。在一些实施例中，波导层32可拥有与围绕波导层32的包覆层(未示出)的折射率相比更大的折射率。举例来说，波导层32可包含多个波导或光学信道。光学信道中的每一个具有中心波长(例如，1.48μm、1.52μm、1.55μm等)，并且每个光学信道通常被指派最小信道间距或带宽以避免与其它光学信道串扰。电子装置封装2可以进一步包含耦合器34和光纤36。耦合器34可以基本上与波导层32齐平。光纤36连接到暴露的第二侧壁302，并且在横向方向上通过耦合器34光学耦合到第一半导体裸片30的波导层32。
图3是根据本发明的一些实施例的电子装置封装3的示意性截面图。如图3中所示，与图2中的电子装置封装2相比，第一半导体裸片30的第一有源表面30A的一部分从囊封物40和第一RDL 50暴露。光纤36通过第一有源表面30A的暴露部分光学耦合到第一半导体裸片30。在一些实施例中，光纤36可以通过例如一对反射器38A、38B和耦合器34光学耦合到波导层32。反射器38A可以通过MEMS过程在第一半导体裸片30的主体中机器加工以便例如将光学路径从水平方向改变为垂直方向。随后在耦合器34中机器加工的反射器38B处再次将光学路径从垂直方向改变为水平方向，且随后传播到光纤36中。为了减少光学损耗，第一半导体裸片30的第一有源表面30A与耦合器34之间的边界可进一步包含一层抗反射涂层(anti-reflective coating,ARC)(未示出)。
图4是根据本发明的一些实施例的电子装置封装4的示意性截面图。如图4中所绘示，电子装置封装4可以进一步包含安置在第二半导体裸片60上的热耗散结构82，以及安置在第二半导体裸片60的第二无源表面60B与热耗散结构82之间的热界面材料84。热耗散结构82经配置以改进第二半导体裸片60的散热效率。热耗散结构82的实例可包含散热器、水冷却结构、风扇或其它合适的有源和/或无源类型热耗散结构。
图5是根据本发明的一些实施例的电子装置封装5的示意性截面图。如图5中所示，与图1和图1A中的电子装置封装1相比，电子装置封装5可以进一步包含相应地插入在穿孔10H中并且由导电穿通孔20围绕的绝缘填充物21。导电穿通孔20可包含基本上符合穿孔10H的轮廓的衬里导电穿通孔。绝缘填充物21可经配置以改进电子装置封装5的稳固性和/或补偿电子装置封装5的CTE不匹配。
图6是根据本发明的一些实施例的电子装置封装6的示意性截面图。如图6中所示，与图1和图1A中的电子装置封装1相比，第一半导体裸片30的厚度T1大于腔室10C的深度D。第一半导体裸片30的一部分高于衬底10的第一顶部表面10T1。电子装置封装6可进一步包含相应地安置在导电穿通孔20上的多个互连器22以补偿在导电穿通孔20与第一RDL 50之间的高度间隙。囊封物40的一部分可进一步覆盖衬底10的第一顶部表面10T，并且横向地围绕互连器22。在一些实施例中，互连器22可包含例如铜柱的导电柱、例如铜杆的导电杆或类似者。电子装置封装6可以经修改以并入如在图2到5的实施例中所公开的特征。
图7A、图7B、图7C、图7D、图7E、图7F、图7G、图7H和图7I说明根据本发明的一些实施例的制造电子装置封装的操作。如图7A中所示，提供衬底10。衬底10从第一表面10T凹陷以形成多个腔室10C。衬底10可以通过例如光刻和蚀刻技术凹陷。在一些实施例中，多个穿孔10H可以形成在衬底中并且邻近于腔室10C。在一些实施例中，穿孔10H可以通过光刻和蚀刻技术形成，并且并且可以与腔室10C通过相同过程同时形成。在一些实施例中，例如氧化硅薄膜的绝缘薄膜12可以形成在衬底10上。
如图7B中所示，多个导电穿通孔20形成在穿孔10H中。导电穿通孔20可以通过电镀、沉积或其它合适的过程形成。如图7C中所示，多个第一半导体裸片30安置在腔室10C中。在一些实施例中，每个腔室10C安置有至少一个第一半导体裸片30。在一些实施例中，第一半导体裸片30的厚度T1小于或基本上等于腔室10C的深度D。在一些其它实施例中，第一半导体裸片30的厚度T1大于腔室10C的深度D。
如图7D中所示，囊封物40形成在衬底10上并且在腔室10C中以囊封第一半导体裸片30的第一侧壁301和第二侧壁302。在第一半导体裸片30的厚度T1大于腔室10C的深度D的情况下，在囊封物40的形成之前互连器22(在图6中示出)可以形成在导电穿通孔20上。如图7E中所示，腔室10C外部的囊封物40通过研磨被移除，例如，以暴露第一半导体裸片30的接触衬垫30P。
如图7F中所示，第一RDL 50形成在衬底10的第一表面10T上。如图7G中所示，衬底10可以翻转过来，并且第一RDL 50可以通过释放层82附接到载体80。如图7H中所示，第二RDL 70可以形成在衬底10的第二表面10B上。多个电导体76可以形成在第二RDL 70上并且电连接到第二RDL 70。载体80和释放层82随后被从第一RDL 50移除。衬底10翻转，并且多个第二半导体裸片60安置在囊封物40上并且通过第一RDL 50电连接到第一半导体裸片30。囊封物40和衬底10沿着划痕线SL被切割。划痕线SL至少沿着第一半导体裸片30的第二侧壁302以暴露第一半导体裸片30的第二侧壁302以形成电子装置封装，如图1到6中所说明。
在本发明的一些实施例中，PIC裸片到裸片接合到EIC，并且扇出结构安置在PIC与EIC之间。因此，可以通过扇出结构在PIC与EIC之间建立的电连接路径。扇出结构与接合导线相比在电阻上较低，并且使用扇出结构的裸片到裸片接合可以缩短在PIC与EIC之间的传输路径。相应地，可以缓解感应作用和信号完整性问题，尤其是在高频应用中。PIC安置在衬底的腔室中，并且因此可以减小电子装置封装的整体厚度。此外，囊封物安置在腔室中以囊封PIC，并且囊封物定位在腔室的侧面与PIC的侧壁的一部分之间的微小备用空间中。相应地，可以极大地减少囊封物的量。囊封物的量减少可以极大地缓解由于囊封物与扇出结构之间的CTE不匹配造成的弯曲问题，并且因此可以改进电子装置封装的可靠性。导电穿通孔可包含例如硅穿孔的高密度穿通孔以满足高I/O需求。
如本文中所使用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包含多个指代物。
如本文中所使用，术语“近似地”、“基本上”、“基本”和“约”用于描述和解释小的变化。当与事件或情况结合使用时，所述术语可指事件或情况精确地发生的例子以及事件或情况极近似地发生的例子。举例来说，当结合数值使用时，术语可指小于或等于所述数值的±10％的变化范围，如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么可认为所述两个数值“基本上”相同或相等。举例来说，“基本上”平行可以指相对于0°的小于或等于±10°的角度变化范围，例如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°。举例来说，“基本上”垂直可以指相对于90°的小于或等于±10°的角度变化范围，例如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
另外，有时在本文中以范围格式呈现量、比率和其它数值。应理解，此范围格式是为了便利和简洁而使用，且应灵活地理解，不仅包含明确地规定为范围极限的数值，而且包含涵盖于那个范围内的所有个体数值或子范围，如同明确地规定每个数值和子范围一般。
虽然已参考本发明的特定实施例描述并说明本发明，但是这些描述和说明并不限制本发明。所属领域的技术人员应理解，在不脱离如由所附权利要求书定义的本发明的真实精神和范围的情况下，可作出各种改变并且可取代等效物。图示可能未必按比例绘制。归因于制造过程和公差，本发明中的艺术再现与实际设备之间可能存在区别。可能存在未特别说明的本发明的其它实施例。应将本说明书和图式视为说明性而非限制性的。可进行修改，以使特定情形、材料、物质组成、方法或过程适应于本发明的目标、精神和范围。所有此类修改都意图在所附权利要求书的范围内。虽然本文中所公开的方法是参考按特定次序执行的特定操作描述的，但是应理解，这些操作可组合、细分或重新排序以形成等效方法而不脱离本发明的教示内容。相应地，除非本文中特别指示，否则操作的次序和分组并非本发明的限制。

Claims (20)

1.一种电子装置封装，其包括：
衬底，其包含第一表面，以及与所述第一表面相对的第二表面，其中所述衬底限定从所述第一表面凹陷的腔室；
第一半导体裸片，其安置在所述腔室中；
第二半导体裸片，其安置在所述第一半导体裸片上方并且电连接到所述第一半导体裸片；以及
囊封物，其安置在所述衬底的所述腔室中，其中所述囊封物囊封所述第一半导体裸片的第一侧壁，并且暴露所述第一半导体裸片的第二侧壁。
2.根据权利要求1所述的电子装置封装，其中所述第一半导体裸片包括光子IC，并且所述第二半导体裸片包括电子IC。
3.根据权利要求1所述的电子装置封装，其中所述囊封物进一步部分地囊封所述第一半导体裸片的第一有源表面。
4.根据权利要求3所述的电子装置封装，其中所述囊封物的边缘与所述第一半导体裸片的所述第二侧壁基本上共面。
5.根据权利要求1所述的电子装置封装，其中所述第一半导体裸片的第一有源表面面向所述第二半导体裸片的第二有源表面。
6.根据权利要求1所述的电子装置封装，其进一步包括第一再分布层，所述第一再分布层安置在所述衬底的所述第一表面与所述第二半导体裸片之间，并且电连接到所述第一半导体裸片以及所述第二半导体裸片。
7.根据权利要求6所述的电子装置封装，其进一步包括安置在所述衬底的所述第二表面上的第二再分布层。
8.根据权利要求7所述的电子装置封装，其进一步包括多个导电穿通孔，所述多个导电穿通孔从所述衬底的所述第一表面延伸到所述衬底的所述第二表面，并且将所述第一再分布层电连接到所述第二再分布层。
9.根据权利要求8所述的电子装置封装，其进一步包括多个互连器，所述多个互连器相应地安置在所述导电穿通孔上、由所述囊封物围绕，并且将所述导电穿通孔电连接到所述第一再分布层。
10.根据权利要求1所述的电子装置封装，其中所述第一半导体裸片的厚度小于或基本上等于所述腔室的深度。
11.根据权利要求1所述的电子装置封装，其中所述第一半导体裸片的厚度大于所述腔室的深度。
12.根据权利要求8所述的电子装置封装，其中所述囊封物进一步覆盖所述衬底的所述第一表面。
13.根据权利要求1所述的电子装置封装，其进一步包括光学耦合到所述第一半导体裸片的光纤。
14.根据权利要求1所述的电子装置封装，其进一步包括：
热耗散结构，其安置在所述第二半导体裸片上；以及
热界面材料，其安置在所述第二半导体裸片与所述热耗散结构之间。
15.一种电子装置封装，其包括：
衬底，其包含第一顶部表面、低于所述第一顶部表面的第二顶部表面，以及与所述第一顶部表面以及所述第二顶部表面相对的底部表面；
光子IC，其安置在所述衬底的所述第二顶部表面上，其中所述光子IC包含至少一个暴露的侧壁；
电子IC，其安置在所述光子IC上方并且电连接到所述光子IC；以及
导电穿通孔，其从所述衬底的所述第一顶部表面延伸到所述衬底的所述底部表面。
16.根据权利要求15所述的电子装置封装，其进一步包括：
第一再分布层，其安置在所述衬底的所述第一顶部表面上并且电连接到所述导电穿通孔、所述光子IC以及所述电子IC；以及
第二再分布层，其安置在所述衬底的所述底部表面上并且电连接到所述导电穿通孔。
17.根据权利要求15所述的电子装置封装，其进一步包括囊封物，所述囊封物安置在所述衬底的所述第二顶部表面上、部分地囊封所述光子IC并且暴露所述光子IC的所述暴露的侧壁。
18.根据权利要求17所述的电子装置封装，其进一步包括导电柱，所述导电柱安置在所述导电穿通孔上且电连接到所述导电穿通孔，并且由所述囊封物围绕。
19.一种制造电子装置封装的方法，其包括：
提供衬底；
使所述衬底从第一表面凹陷以形成腔室；
将第一半导体裸片安置在所述腔室中；
在所述腔室中形成囊封物以囊封所述第一半导体裸片的侧壁；
将第二半导体裸片安置在所述囊封物上；以及
沿着所述第一半导体裸片的侧壁切割所述囊封物以及所述衬底以暴露第一半导体裸片的所述侧壁。
20.根据权利要求19所述的方法，其进一步包括：
在所述衬底中邻近于所述腔室形成穿孔；以及
在所述穿孔中形成导电穿通孔。
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