CN112837617A

CN112837617A - Display panel

Info

Publication number: CN112837617A
Application number: CN202110018593.4A
Authority: CN
Inventors: 叶家宏; 黄国有; 陈茂松
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-08-13
Filing date: 2021-01-07
Publication date: 2021-05-25
Also published as: TW202206903A; TWI733557B

Abstract

A display panel is provided, which includes a first substrate, a pixel structure and a first planarization layer. The pixel structure is configured on the first substrate. The first planarization layer is disposed on the pixel structure and includes a planarization portion, a boss portion, and a trench. The groove is provided between the flattening portion and the boss portion along an edge of the boss portion, wherein a height of the boss portion protruding from a bottom of the groove away from the first substrate in a normal direction of the first substrate is larger than a height of the flattening portion protruding from the bottom of the groove away from the first substrate.

Description

Display panel

Technical Field

The present invention relates to an electronic device, and more particularly, to a display panel.

Background

The display panel is electrically connected to the pixel electrode layer by the active device to provide an electric field to control a display medium (e.g., liquid crystal) through the pixel electrode layer, wherein a state (e.g., flatness) of the pixel electrode layer affects a distribution state of the electric field, thereby affecting display quality. In addition, the display medium is sandwiched between the two substrates, and the spacing distance between the two substrates is required to be kept stable, so as to ensure the display quality. Currently, the display panel may be sandwiched between two substrates by a spacer or the like to maintain a spacing distance between the two substrates. However, the spacers are not fixed but may slip during the assembling process or the using process of the display panel, and the slipping process damages the film structure of the display panel, thereby adversely affecting the display quality. Therefore, how to produce a display panel with good display quality while considering the process cost is a problem to be solved.

Disclosure of Invention

The invention provides a display panel with ideal display quality.

The display panel comprises a first substrate, a pixel structure and a planarization layer. The pixel structure is configured on the first substrate. The first planarization layer is disposed on the pixel structure and includes a planarization portion, a boss portion, and a trench. The groove is provided between the flattening portion and the boss portion along an edge of the boss portion, wherein a height of the boss portion protruding from a bottom of the groove away from the first substrate in a normal direction of the first substrate is larger than a height of the flattening portion protruding from the bottom of the groove away from the first substrate.

In view of the above, in the display panel provided in the embodiment of the invention, the first planarization layer includes the planarization portion, the boss portion, and the groove. The planarization part is used for providing a planarization surface for the film layer arranged on the planarization part so as to ensure the display quality. The groove arranged along the edge of the boss part enables the boss part to be complete in shape, and the boss part is used for abutting against a clearance object on the substrate on the other side of the display panel, so that the problem that the film layer of the contact surface falls off chips due to slippage of the clearance object is avoided. Moreover, the planarization part, the boss part and the groove are all arranged on the same planarization layer, so that the integrated manufacturing steps are used for manufacturing, and the manufacturing cost is reduced.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.

Fig. 2A to 2D are plan views of a first substrate and a part of components disposed on the first substrate in a display panel according to an embodiment of the invention.

Fig. 2E is a schematic cross-sectional view of the film layer on the second metal layer in fig. 2A to 2D along the line I-I'.

Fig. 3A to 3B illustrate a method for fabricating a planarization layer according to an embodiment of the present invention.

Fig. 4 is a partial cross-sectional view of a display panel according to another embodiment of the present invention.

Fig. 5 is a partial cross-sectional view of a display panel according to still another embodiment of the present invention.

Fig. 6 is a schematic top view of a planarization layer of a display panel according to an embodiment of the invention.

Fig. 7 is a schematic top view of a planarization layer of a display panel according to an embodiment of the invention.

Fig. 8 is a schematic top view of a planarization layer of a display panel according to an embodiment of the invention.

Fig. 9 is a schematic top view of a planarization layer of a display panel according to an embodiment of the invention.

Fig. 10A is a schematic side view illustrating an arrangement of a planarization layer and spacers in a display panel according to an embodiment of the invention.

Fig. 10B is a schematic view illustrating an arrangement of a planarization layer and spacers in a display panel according to an embodiment of the invention.

Wherein, the reference numbers:

10 display panel

101 first substrate

102 second substrate

103 display medium

104. PL1, PL2, PL2A, PL2B, 400, 500, 600, 700, 820 planarizing layer

104A, 121, 221, 321, 421521, 621, 721, 821: flattened portion

104B, 122, 222, 322, 422, 522, 622, 722, 822a boss part

104C, 123, 223, 323, 423, 523, 623, 723, 823 grooves

105. 830 spacer

111 semiconductor layer

112 first metal layer

113 second metal layer

4231. 4232, 5231, 5232, 5233, 5234, 8231, 8232 groove segmentation

324 metal layer

822A first major axis

830A second major axis

900 mask

901 opaque region

902 semi-transparent region

903 transparent region

BP0, BP1 insulating layer

CE connecting electrode

D1 first direction

D2 second direction

D3 third Direction

DL data line

ILD-Via

ITO1, ITO2 conductive layer

H1, H2 height

SM shielding metal layer

SL scanning line

TFT-active element

T1, T2 thickness

T324 top surface of metal layer

PL 2' layer of planar material

PX pixel structure

V1, V2, V3, V4 through hole

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention. The display panel 10 may include a first substrate 101, a second substrate 102, a display medium 103, a planarization layer 104 and a spacer 105. The first substrate 101 is, for example, a pixel array substrate, on which a plurality of pixel structures are disposed, but for simplicity of the drawing, the pixel structures are not specifically shown in fig. 1. The second substrate 102 is disposed opposite to the first substrate 101. The display medium 103 is disposed between the first substrate 101 and the second substrate 102, and the display medium 103 is, for example, a liquid crystal layer, but not limited thereto. A planarization layer 104 is disposed on the first substrate 101 and can be disposed on the pixel structure. The planarization layer 104 has a planarized portion 104A, a land portion 104B, and a trench 104C between the planarized portion 104A and the land portion 104B. The boss portion 104B protrudes farther from the first substrate 101 relative to the flattening portion 104A. The spacers 105 are disposed on the second substrate 102 and protrude toward the first substrate 101, and the end surfaces of the spacers 105 abut against the top surface of the boss portion 104B to maintain the distance between the first substrate 101 and the second substrate 102. In the present embodiment, the land 104B is surrounded by a groove 104C, which helps to form the land 104B of a desired size and shape. The mesa 104B of the planarization layer 104 is more convex than the planarization portion 104A, so as to avoid the material on the surface of the spacer 105 from being scraped and/or peeled off to contaminate the display medium 103 and cause poor display when the spacer 105 is displaced relative to the mesa 104B. Therefore, the planarization layer 104 can be used to resist the spacers 105 in addition to providing planarization, and can reduce the adverse effects caused by the displacement of the spacers 105.

The following will illustrate the design of the planarization layer 104 in various embodiments, but the planarization layer 104 of the present invention is not limited to the following embodiments. In fig. 1, the first direction D1 is a normal direction of the first substrate 101, and the second direction D2 and the third direction D3 constitute a plate plane of the first substrate 101. For the sake of convenience, in the following description, the correspondence relationship between the first direction D1, the second direction D2 and the third direction D3 is shown in fig. 1.

Fig. 2A to 2D are plan views of a first substrate and a part of components disposed on the first substrate in a display panel according to an embodiment of the invention. It is understood that the components and/or the film layers presented herein in plan view or top view can be regarded as the outline of the projection (i.e. vertical projection) of the individual components and/or the film layers in the normal direction of the substrate (i.e. the first direction D1). Fig. 2E is a schematic cross-sectional view of the film layer on the second metal layer in fig. 2A to 2D along the line I-I'. For ease of understanding, the partial film structures shown in fig. 2A to 2D are not shown in fig. 2E.

Referring to fig. 2A, a semiconductor layer 111, a first metal layer 112, and a second metal layer 113 are disposed on a first substrate 101, wherein an insulating layer (not shown) is further disposed between two adjacent layers of the semiconductor layer 111, the first metal layer 112, and the second metal layer 113. The semiconductor layer 111, the first metal layer 112, and the second metal layer 113 are patterned to define necessary components, such as an active element TFT, a scan line SL, a data line DL, and a connection electrode CE. Since an insulating layer (not shown) is disposed between the second metal layer 113 and the semiconductor layer 111, the second metal layer 113 may be connected to the semiconductor layer 111 through a via ILD penetrating the insulating layer in order to achieve a desired electrical connection relationship. In addition, a shielding metal layer SM may be further disposed on the first substrate 101 and disposed between the semiconductor layer 111 and the first substrate 101 to prevent the semiconductor layer 111 from being irradiated by a backlight (not shown) and affecting the characteristics of the semiconductor layer 111.

Referring next to fig. 2B and 2E, a planarization layer PL1, an insulating layer BP0, and a planarization layer PL2 are further provided on the first substrate 101 to cover the active elements TFT, the scan lines SL, the data lines DL, and the like. As shown in fig. 2E, a planarization layer PL1 is formed on the second metal layer 113, an insulation layer BP0 is deposited on the planarization layer PL1, and a planarization layer PL2 is formed on the insulation layer BP 0. Although not shown in fig. 2E, as can be understood from fig. 2B in conjunction with fig. 2E, the active device TFT is disposed between the planarization layer PL1 and the first substrate 101. Planarization layer PL1 and planarization layer PL2 may be formed by coating (coating) and may be made of organic insulating material, and insulating layer BP0 is disposed to increase adhesion (adhesion) between planarization layer PL2 and planarization layer PL1 and prevent planarization layer PL1 from outgassing (outweighting) and affecting other layers. According to some embodiments, insulating layer BP0 may be, for example, SiO_xOr SiN_xBut not limited thereto.

In the present embodiment, in order to realize electrical connection between different conductive film layers, the planarization layer PL1 may be patterned to have a via hole V1, the insulation layer BP0 may be patterned to have a via hole V2, and the planarization layer PL2 may be patterned to have a via hole V3, so that the connection electrode CE of the second metal layer 113 is exposed without being covered by the planarization layer PL1, the insulation layer BP0, and the planarization layer PL 2. In addition, referring also to fig. 2B and 2E, the planarizing layer PL2 includes a planarizing portion 121, a land portion 122, and a groove 123, the groove 123 being provided along an edge of the land portion 122 and being provided between the planarizing portion 121 and the land portion 122, wherein a through hole V3 is provided in the planarizing portion 121, for example. Specifically, in fig. 2B, the flattened section 121 substantially covers all regions except the through hole V3, the groove 123, and the boss section 122. Since the planarization layer PL1, the insulation layer BP0, and the planarization portion 121 of the planarization layer PL2 cover most of the area of the first substrate 101, the outlines of these elements in fig. 2B are not clearly defined, and therefore, the outlines of the via V1, the via V2, and the via V3 are shown.

Referring next to fig. 2C and 2E, a conductive layer ITO1 is disposed on the planarization layer PL2, covering at least a portion of the planarization portion 121, the mesa portion 122, and the trench 123, and not covering the via V1, the via V2, and the via V3. The material of the conductive layer ITO1 includes, but is not limited to, Indium Tin Oxide (ITO). Specifically, the material of the conductive layer ITO1 may be an oxide conductive material including at least one of a transparent metal oxide material such as Indium Zinc Oxide (IZO), Aluminum Zinc Oxide (AZO), Aluminum Indium Oxide (AIO), indium oxide (InO), gallium oxide (GaO), and Indium Gallium Zinc Oxide (IGZO), or other transparent conductive materials such as carbon nanotubes, silver nanoparticles, a metal or alloy having a thickness of less than 60 nanometers (nm), an organic transparent conductive material, or a combination of at least two of the foregoing materials. In addition, an insulating layer BP1 is further disposed on the conductive layer ITO1 and covers most of the area of the first substrate 101 as with the insulating layer BP 0. The insulating layer BP1 may have a via hole V4, and a via hole V4 is disposed corresponding to the via hole V1, the via hole V2, and the via hole V3, so that the second metal layer 113 is exposed in the via hole V1, the via hole V2, the via hole V3, and the via hole V4.

Referring next to fig. 2D and 2E, a conductive layer ITO2 is disposed on the insulating layer BP1 and connected to the connection electrode CE exposed by the via hole V1 of the planarization layer PL1, the via hole V2 of the insulating layer BP0, the via hole V3 of the planarization layer PL2, and the via hole V4 of the insulating layer BP 1. Specifically, the conductive layer ITO2 may be used as a pixel electrode layer, and the connection electrode CE of the second metal layer 113 is electrically connected between the conductive layer ITO2 and the active element TFT; that is, the active element TFT supplies the conductive layer ITO2 voltage through the connection electrode CE. The conductive layer ITO1 may then serve as a common electrode and be connected to a common voltage. In this way, the active element TFT, the conductive layer ITO1 and the conductive layer ITO2 may form a pixel structure PX to be applied to the display panel 10 in fig. 1, wherein when the pixel structure PX is driven, an electric field generated by a voltage difference between the conductive layer ITO1 and the conductive layer ITO2 may be used to control the display medium 103 of the display panel 10. Here, the conductive layer ITO2 is farther from the first substrate 101 than the conductive layer ITO1, and may be patterned to have a plurality of slits, but not limited thereto. The conductive layer ITO2 and the conductive layer ITO1 may be made of the same material, or different transparent conductive materials. In the embodiment, the conductive layer ITO2 is disposed on the planarization layer PL2, so that the conductive layer ITO2 has good planarization, and thus the electric field provided by the conductive layer ITO2 to the display medium has uniform electric lines of force instead of disordered electric lines of force, thereby improving the display quality of the display panel.

In order to clearly present the cross-sectional structure of the film layer above the second metal layer 113, fig. 2E shows the conductive layer ITO1 and the conductive layer ITO2 of the connection electrode CE and the pixel structure PX, and other film layers and members of the pixel structure PX are omitted. As shown in fig. 2E, a second metal layer 113, a planarization layer PL1, an insulating layer BP0, a planarization layer PL2, a conductive layer IOT1, an insulating layer BP1, and a conductive layer ITO2 are sequentially stacked. The insulating layer BP0 is disposed between the planarization layer PL1 and the planarization layer PL2, so as to improve the adhesion between the planarization layer PL1 and the planarization layer PL 2. The insulation layer BP1 is disposed between the conductive layer ITO1 and the conductive layer ITO2 to prevent the two conductive layers from being electrically shorted. The planarization layer PL2 is disposed between the second metal layer 113 and the conductive layer ITO 1. The planarization layer PL2 includes a via V3 to allow the second metal layer 113 to be electrically connected with the conductive layer ITO 1.

Planarization layer PL2 includes a planarization portion 121, a land portion 122, and a groove 123. The groove 123 is provided along the edge of the boss portion 122, and at least a portion of the groove 123 is interposed between the boss portion 122 and the through-hole V3, so that the boss portion 122 is sharp in profile, and the size of the boss portion 122 can be easily controlled in a manufacturing process. A height H1 of the mesa 122 protruding from the bottom of the groove 123 in a first direction D1 is greater than a height H2 of the planarized section 121 protruding from the bottom of the groove 123, where the first direction D1 refers to a normal direction of the first substrate 101 (refer to fig. 2D and fig. 1), and as shown in fig. 2D, a vertical projection of the mesa 122 on the first substrate 101 does not overlap a vertical projection of the planarized section 121 on the first substrate 101. The planarization layer PL2 shown in fig. 2D and 2E can be applied to the display panel 10 of fig. 1 as an embodiment of the planarization layer 104, and the pixel structure PX shown in fig. 2D and 2E can be applied to the display panel 10. In addition, the planarization layer 121, the mesa portion 122 and the trench 123 belong to the planarization layer PL2, and may be formed by the same photolithography process.

Referring to fig. 3A and 3B, a method for forming the planarization portion 121, the boss portion 122 and the trench 123 in the same photolithography process is described. As shown in fig. 3A, a planarization material layer PL2 'is formed on the insulating layer BP0 by coating, wherein the planarization material layer PL 2' may have a uniform height relative to the top surface of the insulating layer BP 0. Next, the above-mentioned planarization material layer PL2 'with uniform height is exposed and developed by using the mask 900 as shown in fig. 3B, so that the planarization material layer PL 2' is patterned into a planarization layer PL 2. As shown in fig. 3B, the mask 900 includes an opaque region 901, a semi-opaque region 902 and a transparent region 903, wherein the transparency of the transparent region 903 is greater than that of the semi-opaque region 902, and the transparency of the semi-opaque region 902 is greater than that of the opaque region 901. When the mask 900 is used to expose a planar material layer PL2 'with a uniform height, different portions of the planar material layer PL 2' may be exposed to different degrees. In the present embodiment, the planarization material layer PL2 ' may have a positive photosensitive property, and therefore, in the planarization material layer PL2 ', the region corresponding to the opaque region 901 is formed as the mesa 122, the region corresponding to the semi-opaque region 902 is formed as the planarization portion 121, and the region corresponding to the transparent region 903 is formed as the trench 123, so that the planarization material layer PL2 ' is patterned into the planarization layer PL2 having the planarization portion 121, the mesa 122 and the trench 123 as shown in fig. 2E.

In some embodiments, during the process of fabricating the planarization layer PL2 of fig. 2E, the via V3 may be formed together. For example, in fabricating the planarization layer PL2, the portion of the mask 900 where the trench 123 and the via V3 are expected to be formed may correspond to the region with the same transmittance, and the planarization material is removed to form the trench 123 and the via V3, but not limited thereto. Since the planarization 121, the mesa 122 and the trench 123, even the via V3 can be formed in the same photolithography process without requiring separate process steps, the integrated process steps reduce the cost and time of the process. In addition, the land 122 and the groove 123, which are adjacent to each other in structure, correspond to two regions of the mask 900 with the minimum transmittance and the maximum transmittance, respectively, so that the boundary of the land 122 can be clearly defined to have a desired size and pattern.

In the present embodiment, the trench 123 penetrates the entire planarization layer PL2 such that the bottom of the trench 123 is coplanar with the bottom surface of the planarization part 122, but not limited thereto. The following embodiments will illustrate different arrangements of the grooves. The following embodiments follow the element numbering logic and part of the content of the previous embodiments, wherein the same or similar elements are denoted by the same logical numbering, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Referring to fig. 4, a partial cross-sectional view of a display panel according to another embodiment of the present invention is shown. The embodiment of fig. 4 is substantially similar to the embodiment of fig. 2E, and fig. 4 only shows the second metal layer 113 (which may be considered as part of the active elements in the pixel structure PX), the planarization layer PL1, the insulating layer BP0, the planarization layer PL2A, the conductive layer ITO1, the insulating layer BP1, and the conductive layer ITO 2. In fig. 4, the difference from fig. 2E mainly lies in the structure of the planarization layer PL 2A. Specifically, the planarization layer PL2A of the present embodiment includes the planarization part 221, the mesa part 222 and the trench 223, and a portion of the planarization material may extend to the bottom of the trench 223. That is, there is a portion of the planarization material between the trench 223 and the insulating layer BP0 such that the trench 223 does not penetrate the entire planarization layer PL 2A. However, the thickness T1 of planarization layer PL2A in trench 223 is less than the thickness T2 of planarization layer PL2A in planarized portion 222. In addition, the top surface of the planarization layer PL2A at the trench 223 is lower, i.e., closer to the first substrate (not shown in fig. 4), than the top surface at the planarization part 221. Thus, the groove 223 between the flattened portion 221 and the land portion 222 still constitutes a relatively concave structure.

Like the method of fabricating the planarization layer PL2 of the previous embodiment, the planarization layer 221, the boss 222 and the trench 223 of the planarization layer PL2A can be formed by the same photolithography process. The method of fabricating the planarization layer PL2A of the present embodiment is substantially similar to the method described in fig. 3A and 3B. However, the transmittance of the mask may be adjusted during the formation of the planarization layer PL2A of the present embodiment, so that a portion of the planarization material intended to form the trench 223 is not completely removed. For example, the mask used in the present embodiment may include an opaque region, a first semi-opaque region and a second semi-opaque region, and the transmittance of the first semi-opaque region is lower than that of the second semi-opaque region, wherein the region corresponding to the opaque region is formed as a mesa 222, the region corresponding to the first semi-opaque region is formed as a planarization portion 221, and the region corresponding to the second semi-opaque region is formed as a trench 223, so as to form a planarization layer PL2A having the planarization portion 221, the mesa 222 and the trench 223 as shown in fig. 4.

Referring to fig. 5, a partial cross-sectional view of a display panel according to still another embodiment of the invention is shown. The embodiment of fig. 5 is substantially similar to the embodiment of fig. 2E, and fig. 5 only shows the second metal layer 113 (which is part of the pixel structure PX), the planarization layer PL1, the insulating layer BP0, the planarization layer PL2B, the conductive layer ITO1, the insulating layer BP1, and the conductive layer ITO 2. In addition, unlike fig. 2E, the planarization layer PL2B of fig. 5 includes a planarization portion 321, a boss portion 322 and a trench 323, and the display panel further includes a metal layer 324, wherein the metal layer 324 is disposed under the boss portion 322. When the structure of fig. 5 is applied to the display panel 10 of fig. 1, the vertical projection of the mesa portion 322 on the first substrate 101 shown in fig. 1 may overlap the vertical projection of the metal layer 324, and the vertical projection of the trench 323 overlaps the vertical projection of the metal layer 324. Thus, the top surface T324 of the metal layer 324 defines the bottom of the trench 323. In an embodiment of the invention, the metal layer 324 may be a touch electrode of a touch panel, but is not limited thereto.

Referring to fig. 6, a schematic top view of a planarization layer of a display panel according to an embodiment of the invention is shown. The planarization layer 400 includes a planarization portion 421, a mesa portion 422, and a trench 423, which can be regarded as one possible implementation of the planarization layer 104, the planarization layer PL2, the planarization layer PL2A, or the planarization layer PL2B of the foregoing embodiments in the top view (i.e., the plane formed by the second direction D2 and the third direction D3). Specifically, similar to the previous embodiments, the planarization layer 400 may be disposed on a substrate (e.g., the first substrate 101 of fig. 1), for example. In fig. 6, only a portion of the flattened section 421 adjacent to the boss section 422 is shown for illustrative purposes.

In the present embodiment, the perpendicular projection of the boss 422 on the substrate (not labeled) has a long axis in the third direction D3, the groove 423 includes two

groove segments

4231 and 4232 located at two opposite sides of the boss 422 in the second direction D2, and the two

groove segments

4231 and 4232 are both arranged along the third direction D3, but the invention is not limited thereto. For example, the groove 423 may, for example, comprise two groove segments on opposite sides of the boss 422 in the third direction D3, and both groove segments are arranged along the second direction D2. As described in the foregoing embodiment, in the cross-sectional structure, the height of the boss portion 422 projected from the bottom of the groove 423 in the normal direction of the substrate is larger than the height of the flattened portion 421 projected from the bottom of the groove 423, and the

groove segments

4231 and 4232 interposed between the boss portion 422 and the flattened portion 421 constitute a relatively concave structure (not shown), so that the boss portion 422 is easier to control the size and shape in the manufacturing process.

Referring to fig. 7, a schematic top view of a planarization layer of a display panel according to an embodiment of the invention is shown. The planarization layer 500 includes a planarization portion 521, a land portion 522, and a groove 523. Similar to the planarization layer 400 shown in fig. 6, the planarization layer 500 may be an implementation of the planarization layer in the embodiments of fig. 1, 2E, 4, and 5 in an upper view (a plan view on a plane formed by the second direction D2 and the third direction D3). Similar to the previous embodiments, the planarization layer 500 may be disposed on a substrate (similar to the first substrate 101 of fig. 1), for example. In fig. 7, only a portion of the flattened section 521 adjacent to the boss portion 522 is shown.

In the present embodiment, the projection of the boss portion 522 on the substrate has a long axis in the third direction D3, the groove 523 includes four

discontinuous groove segments

5231, 5232, 5233, 5234 along the outer sides of the four corners of the edge of the boss portion 522, and a portion of the flattened portion 521 is located between adjacent ones of the

groove segments

5231, 5232, 5233, 5234. Specifically, as shown in fig. 7, a part of the planarization portion 521 is provided between the trench segment 5231 and the trench segment 5232, a part of the planarization portion 521 is provided between the trench segment 5232 and the trench segment 5233, a part of the planarization portion 521 is provided between the trench segment 5233 and the trench segment 5234, and a part of the planarization portion 521 is provided between the trench segment 5234 and the trench segment 5231, but the present invention is not limited thereto.

In another embodiment of the present invention, the trench 523 may include only two of the

trench segments

5231, 5232, 5233, 5234, such as

only trench segments

5231 and 5233, or only

trench segments

5232 and 5234. In yet another embodiment of the present invention, the groove 523 may include four discontinuous groove segments disposed along four sides of the boss portion 522, respectively, and not disposed outside four corners along the edge of the boss portion 522, but the present invention is not limited thereto. In fig. 7, as described in the foregoing embodiment, in the cross-sectional structure, the height of the boss portion 522 protruding from the bottom of the groove 523 in the normal direction of the substrate is greater than the height of the flattening portion 521 protruding from the bottom of the groove 523, and the

groove segments

5231, 5232, 5233, 5234 interposed between the boss portion 522 and the flattening portion 521 constitute a relatively recessed structure (not shown), so that the size of the boss portion 522 is easily controlled in the manufacturing process.

Referring to fig. 8, a schematic top view of a planarization layer of a display panel according to an embodiment of the invention is shown. The planarization layer 600 includes a planarization portion 621, a land portion 622, and a trench 623. Similarly, the planarization layer 600 may be implemented in an upper view (a plan view on a plane formed by the second direction D2 and the third direction D3) of the planarization layer in the embodiments of fig. 1, 2E, 4, and 5. Specifically, similar to the previous embodiments, the planarization layer 600 may be disposed on a substrate (similar to the first substrate 101 of fig. 1), for example. In fig. 8, only a portion of the flattened section 621 adjacent to the boss portion 622 is shown.

The vertical projection of the boss portion 622 on the substrate is an ellipse with its major axis disposed along the third direction D3 and the groove 623 completely surrounding the edge of the boss portion 622, but the present invention is not limited thereto. In another embodiment of the present invention, the groove 623 may be formed by a plurality of groove segments, such as two groove segments, three groove segments or four groove segments, and a portion of the flattened portion 621 is disposed between two adjacent groove segments of the plurality of groove segments, that is, the groove 623 is disposed partially around the edge of the boss portion 622. In the present embodiment, as described in the foregoing embodiments, in the cross-sectional structure, the height of the land portion 622 protruding from the bottom of the groove 623 in the normal direction of the substrate is larger than the height of the planarized portion 621 protruding from the bottom of the groove 623, and the groove 623 interposed between the land portion 622 and the planarized portion 621 constitutes a relatively concave structure (not shown), so that the land portion 622 can be easily controlled in size in the manufacturing process.

Referring to fig. 9, a schematic top view of a planarization layer is shown according to an embodiment of the invention. The planarization layer 700 includes a planarization portion 721, a land portion 722, and a trench 723. Similarly, the planarization layer 700 may be implemented in an upper view (a plan view on a plane formed by the second direction D2 and the third direction D3) of the planarization layer in the embodiments of fig. 1, 2E, 4, and 5. In fig. 9, only a portion of the flattened portion 721 adjacent to the boss portion 722 is shown.

The mesa 722 of the planarization layer 700 is a shorter oval than the planarization layer 600 shown in fig. 8. Similar to the planarization layer 600, the long axis of the projection of the mesa 722 of the planarization layer 700 on the substrate is disposed along the third direction D3, and the groove 723 is disposed completely around the edge of the mesa 722, but the present invention is not limited thereto. In another embodiment of the present invention, the groove 723 may be formed by a plurality of groove segments, such as two groove segments, three groove segments, or four groove segments, and a portion of the flattened portion 721 is disposed between two adjacent groove segments of the plurality of groove segments, i.e., the groove 723 is disposed partially around the edge of the boss portion 722. In the present embodiment, as described in the foregoing embodiments, in the cross-sectional structure, the height of the boss portion 722 protruding from the bottom of the groove 723 in the normal direction of the substrate is larger than the height of the flattening portion 721 protruding from the bottom of the groove 723, and the groove 723 interposed between the boss portion 722 and the flattening portion 721 constitutes a relatively concave structure (not shown), so that the boss portion 722 is easily controlled in size in the manufacturing process.

Referring to fig. 10A and 10B, a side view and a top view of a planarization layer and a spacer in a display panel according to an embodiment of the invention are shown. Specifically, fig. 10A may be a cross-sectional view taken along a dashed line a-a' in fig. 10B. Referring to fig. 10A, the planarization layer 820 is disposed on the insulating layer BP0 and includes a planarization portion 821, a mesa portion 822 and a trench 823, wherein the trench 823 includes two

trench segments

8231 and 8232, and a height of the mesa portion 822 protruding from a bottom of the trench 823 in the first direction D1 is greater than a height of the planarization portion 821 protruding from a bottom of the trench 823. The planarization layer 820 is directly disposed on the insulation layer BP0 similar to the planarization layer PL2 of the embodiment shown in fig. 2E, the insulation layer BP0 may be disposed on a substrate (similar to the first substrate 101 of fig. 1), for example, and the bottom surface of the trench 823 is coplanar with the top surface of the insulation layer BP 0. The spacer 830 may be provided, for example, on another substrate (not shown) and protrude toward the boss portion 822. Specifically, the spacers 830 protrude toward the planarization layer 820, and the end surfaces of the spacers 830 abut against the top surfaces of the boss portions 822.

In another embodiment, the planarization layer 820 may be directly disposed on the insulation layer BP0, similar to the planarization layer PL2A of the embodiment shown in fig. 4, and the bottom of the trench 823 is disposed with a portion of the planarization 821. In yet another embodiment, the planarization layer 820 may be similar to the planarization layer PL2B of the embodiment shown in fig. 5, with a metal layer disposed between the mesa portion 822 and the insulating layer BP0, the metal layer extending further to the bottom of the trench 823, and the bottom surface of the trench 823 being coplanar with the top surface of the metal layer. However, in order to clearly understand the arrangement relationship between the spacers 830 and the mesa portions 822 and avoid confusion, the embodiment only exemplifies the case where the planarization layer 820 is directly disposed on the insulation layer BP0 and the trench 823 penetrates through the planarization layer 820.

Referring to fig. 10B, an upper view of the layout of the planarization layer 820 and the spacers 830 is shown, and fig. 10B can also be regarded as a vertical projection of the planarization layer 820 and the spacers 830 on the substrate (e.g., the first substrate 101 of fig. 1) on which the planarization layer 820 is disposed. As can be seen in fig. 10B, the vertical projection of the land 822 on the substrate has a first long axis 822A arranged along a third direction D3, and both

groove segments

8231 and 8232 are arranged along the third direction D3. The perpendicular projection of the spacer 830 on the substrate has a second long axis 830A disposed along the second direction D2, and the second long axis 830A is orthogonal to the first long axis 822A, but the invention is not limited thereto. In other embodiments of the present invention, the first long axis 822A and the second long axis 830A may intersect at an angle greater than 0 degree and equal to or less than 90 degrees to form an X-shape.

As shown in fig. 10A and 10B, the spacer 830 abuts the middle section of the top surface of the boss 822 with the middle section of the end surface thereof, rather than abutting the sections close to the ends of the long shaft, which helps to avoid the problem of film chipping of the contact surface caused by the end grinding of the spacer 830 and the boss 822 due to the slippage of the spacer 830. Specifically, if the spacer 830 or the boss 822 abuts against the spacer 830 and the boss 822 at a portion close to the end of the long axis, when the spacer 830 slides, the peripheral corner of the spacer 830 or the peripheral corner of the boss 822 rubs against the spacer 830, which may cause the film layers (such as the conductive layer ITO1, the insulating layer BP1, or the alignment layer not shown in the foregoing embodiment) disposed on the spacer 830 and the boss 822 to be damaged or chipped, thereby affecting the display quality. Therefore, in the present embodiment, the middle section of the end surface of the spacer 830 abuts against the middle section of the top surface of the boss portion 822, so as to improve or avoid the above-mentioned problem of film chip falling. In addition, the planarization layer 820 of the present embodiment may have a similar structure to the planarization layer 400 shown in fig. 6, but the present invention is not limited thereto. For example, the planarization layer 820 may be replaced by the planarization layer 500, the planarization layer 600, or the planarization layer 700 shown in fig. 7-9, and the above-mentioned advantages can be obtained.

In summary, the display panel provided in the embodiments of the invention includes the planarization layer, and the planarization layer includes the planarization portion, the boss portion, and the trench. The flattening part provides a flattening surface for each layer film arranged on the flattening part, so that, for example, the pixel electrode layer can have a flat structure, and uniform electric lines are provided, thereby avoiding the influence of disordered electric field distribution on the display quality. The grooves provided along the edges of the boss portion ensure the integrity of the shape of the boss portion and make it easier to control the size of the boss portion during the manufacturing step. The middle section of the top surface of the boss part abuts against the middle section of the end surface of the clearance object, so that the problem of chip falling of the layer film caused by slippage of the clearance object is avoided. Moreover, the planarization part, the boss part and the groove can be integrally manufactured by adopting the same yellow light processing step and are arranged on the same planarization layer, wherein the planarization part and the boss part are made of the same material, so that the integrated processing step reduces the processing cost and shortens the processing time.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A display panel, comprising:

a first substrate;

a pixel structure disposed on the first substrate; and

a first planarization layer disposed on the pixel structure, comprising:

a planarization portion;

a boss portion; and

a groove disposed between the planarization portion and the boss portion along an edge of the boss portion, wherein a height of the boss portion protruding from a bottom of the groove away from the first substrate in a normal direction of the first substrate is greater than a height of the planarization portion protruding from the bottom of the groove away from the first substrate.

2. The display panel of claim 1, further comprising a second substrate and a spacer disposed on the second substrate and protruding toward the first substrate, wherein an end surface of the spacer abuts against a top surface of the boss portion.

3. The display panel of claim 2, wherein a vertical projection of the top surface of the boss portion on the first substrate has a first long axis, a vertical projection of the end surface of the spacer on the first substrate has a second long axis, and the first long axis intersects the second long axis.

4. The display panel of claim 2, wherein a vertical projection of the top surface of the boss portion and a vertical projection of the end surface of the spacer on the first substrate form an X-shape.

5. The display panel of claim 1, further comprising a second planarizing layer disposed between the first substrate and the first planarizing layer.

6. The display panel of claim 5, wherein the pixel structure includes an active element disposed between the first substrate and the second planarization layer.

7. The display panel of claim 1, wherein the groove completely surrounds the edge of the boss portion.

8. The display panel of claim 1, wherein a thickness of the first planarizing layer in the trench is less than a thickness of the first planarizing layer in the planarizing portion.

9. The display panel of claim 1, wherein the bottom of the trench is coplanar with a bottom surface of the planarization portion.

10. The display panel of claim 1, wherein the pixel structure comprises a metal layer and a conductive layer, the first planarization layer is disposed between the metal layer and the conductive layer, the first planarization layer further comprises a via hole for electrically connecting the metal layer and the conductive layer, and at least a portion of the trench is between the boss portion and the via hole.

11. The display panel of claim 1, further comprising a metal layer disposed under the boss portion, and a vertical projection of the boss portion on the first substrate overlaps a vertical projection of the metal layer.

12. The display panel of claim 11, wherein a top surface of the metal layer defines the bottom of the trench.

13. The display panel of claim 1, wherein the groove comprises a plurality of discontinuous groove segments disposed along the edge of the land portion, and the planarization portion is further between the plurality of groove segments.

14. A display panel as claimed in claim 1 characterized in that the groove comprises two groove segments, which are located at opposite sides of the boss portion.

15. The display panel of claim 1, wherein a vertical projection of the mesa portion on the first substrate does not overlap a vertical projection of the planarization portion.