CN107193167B

CN107193167B - Array substrate and liquid crystal display panel

Info

Publication number: CN107193167B
Application number: CN201710549615.3A
Authority: CN
Inventors: 游礎宽; 叶昭纬
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2017-05-09
Filing date: 2017-07-07
Publication date: 2020-06-23
Anticipated expiration: 2037-07-07
Also published as: TWI647524B; CN107193167A; TW201901267A

Abstract

An array substrate comprises a substrate, and a gate line, a common line, two adjacent data lines and a sub-pixel unit which are arranged on the substrate. The sub-pixel unit comprises a thin film transistor, an insulating layer, a pixel electrode, a transparent common electrode and a projecting electrode. The thin film transistor comprises a source electrode, a drain electrode and a grid electrode. The insulating layer is arranged on the thin film transistor and provided with a contact hole. The pixel electrode is arranged on the substrate and provided with at least one notch. The transparent common electrode is arranged on the insulating layer and partially overlapped with the pixel electrode in a vertical projection direction, the transparent common electrode is connected with the common line through the contact hole, the notch corresponds to the contact hole, and the notch is adjacent to the contact hole. The projection electrode is arranged on the substrate and connected with the pixel electrode, and the projection electrode is adjacent to the gap.

Description

Array substrate and liquid crystal display panel

Technical Field

The present invention relates to a display device, and more particularly, to a display device including a projection electrode connected to a pixel electrode to improve light transmittance of an array substrate and a liquid crystal display panel.

Background

Liquid crystal display panels have been widely used in various electronic products, such as smart phones (smart phones), notebook computers (notebook computers), tablet computers (tablets pcs), flat panel televisions (tvs) and various types of consumer electronics, because of their advantages of being light, thin, short, small, and energy-saving.

In order to overcome the drawback of the narrow viewing angle of the conventional liquid crystal display panel, a Fringe Field Switching (FFS) liquid crystal display panel has been developed, which is characterized in that a common electrode and a pixel electrode are disposed on different planes of an array substrate (also referred to as a tft substrate), and an electric field generated by the common electrode and the pixel electrode is used to achieve a wide viewing angle.

However, with the trend of improving the resolution of the fringe field switching liquid crystal display panel, when the number of elements in the pixel unit, such as the pixel electrode and the common electrode, is reduced, the array substrate of the pixel unit with better light transmittance performance still needs to be provided.

Disclosure of Invention

The invention provides an array substrate, which is used for improving the liquid crystal driving performance of a contact hole adjacent to the joint of a common electrode and a common line.

The invention provides an array substrate, which is used for avoiding the problem of black lines generated at the contact hole of a sub-pixel unit adjacent to the joint of a common electrode and a common line.

The invention provides an array substrate, which is used for improving the integral light transmittance performance of a sub-pixel unit and a liquid crystal display panel comprising the sub-pixel unit.

To achieve the above advantages, an embodiment of the invention provides an array substrate, which includes a substrate, and a gate line, a common line, two adjacent data lines and a sub-pixel unit disposed on the substrate. The common line is substantially parallel to the gate line. The sub-pixel unit comprises a thin film transistor, an insulating layer, a pixel electrode, a transparent common electrode and a projecting electrode. The thin film transistor comprises a source electrode, a drain electrode and a grid electrode, wherein the grid electrode is electrically connected with the grid line. The insulating layer is arranged on the thin film transistor and is provided with a contact hole. The pixel electrode is arranged on the substrate and electrically connected with the drain electrode, and the pixel electrode is provided with at least one notch. The transparent common electrode is arranged on the insulating layer, the transparent common electrode and the pixel electrode are partially overlapped in a vertical projection direction, and the transparent common electrode is connected with the common line through the contact hole, wherein the gap corresponds to the contact hole and is adjacent to the contact hole. And the projecting electrode is arranged on the substrate, is connected with the pixel electrode, is adjacent to the notch and extends along the first direction.

In an embodiment of the invention, in the array substrate, the first direction is substantially parallel to the extending direction of the gate line.

In an embodiment of the invention, in the array substrate, the first direction is substantially parallel to an extending direction of two adjacent data lines.

In an embodiment of the invention, in the array substrate, the protruding electrodes further extend along a second direction, the first direction is substantially parallel to the extending direction of the gate lines, and the second direction is substantially parallel to the extending direction of two adjacent data lines.

In an embodiment of the invention, in the array substrate, an included angle is formed between the first direction and the extending direction of the gate line, and the included angle is greater than 0 degree and smaller than 90 degrees.

In an embodiment of the invention, in the array substrate, the notch is located at least one corner of the pixel electrode.

In an embodiment of the invention, in the array substrate, the pixel electrode has a first side and a second side, and the notch has a contour, and the contour connects the first side and the second side respectively.

In an embodiment of the invention, in the array substrate, the protruding electrode extends from the first side.

In an embodiment of the invention, in the array substrate, the protruding electrode extends from a portion of the outline.

In an embodiment of the invention, in the array substrate, the pixel electrode and the two adjacent data lines do not overlap in the vertical projection direction.

In an embodiment of the invention, in the array substrate, a connection portion between the protruding electrode and the pixel electrode has a long side, and the long side is greater than or equal to 2 micrometers (μm) and less than or equal to 10 micrometers (μm).

In an embodiment of the invention, in the array substrate, the transparent common electrode has a plurality of slits, and the pixel electrode does not have a plurality of slits.

In an embodiment of the invention, in the array substrate, the transparent common electrode has an inner side edge parallel to the two adjacent data lines, and a distance between the pixel electrode and the inner side edge is greater than or equal to 0 micrometers (μm) and less than or equal to 4 micrometers (μm).

In an embodiment of the invention, in the array substrate, the gap has a contour, and the contour surrounds at least a portion of the contact hole.

To achieve the above advantages, an embodiment of the invention provides a liquid crystal display panel, which includes the array substrate, an opposite substrate and a liquid crystal layer. The opposite substrate is opposite to the array substrate. The liquid crystal layer is arranged between the array substrate and the opposite substrate.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic top view of a portion of an array substrate according to an embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view taken along line 2-2' of the array substrate of FIG. 1;

FIG. 3 is an enlarged schematic view of area 150 of FIG. 1, in accordance with one embodiment of the present invention;

FIG. 4 is an enlarged schematic view of a region 150 of FIG. 1 according to another embodiment of the present invention;

FIG. 5 is a graph showing the light transmittance of an array substrate according to an embodiment of the invention;

FIG. 6 is an enlarged schematic view of a region 150 of FIG. 1 according to yet another embodiment of the present invention;

FIG. 7 is a graph illustrating light transmittance of an array substrate according to an embodiment of the invention;

FIG. 8 is a schematic top view of an array substrate according to another embodiment of the present invention; and

FIG. 9 is a cross-sectional view of an LCD panel according to an embodiment of the invention.

Wherein, the reference numbers:

100. 100' -array substrate

102 to substrate

104 a-common line

104b gate line

106 insulating layer

107 to semiconductor layer

108-data line

108a to drain electrode

108b source electrode

110 insulating layer

112-contact hole

130-pixel electrode

130 a-notch

130 b-projecting electrode

130c to the first side

130d to the second side edge

140-transparent common electrode

140 a-connecting part

140 b-slit

140 c-slit electrode

140 d-inner side edge

150 to area

200-opposite substrate

250-liquid crystal layer

300-liquid crystal display panel

G-grid

P-sub pixel unit

TFT-thin film transistor

Contour of C-notch

α -included angle

Distance D1-

D2-projected length

D3 Length

T-end point

S-long side

F-junction

X, Y, Z-direction

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present invention.

In the drawings, the thickness of various elements and the like are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" or "overlapping" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physically and/or electrically connected.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

As used herein, "about" or "substantially" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Referring to fig. 1-2, a partial schematic view of an array substrate 100 according to an embodiment of the invention is shown, in which fig. 1 shows a partial top view of a region 150 in the array substrate 100, and fig. 2 shows a cross-sectional view along a line 2-2' of the array substrate 100 in fig. 1.

As shown in fig. 1, the array substrate 100 is illustrated as a partial structure, such as a sub-pixel P, but not limited thereto. The array substrate 100 at least includes a substrate 102, a gate line 104b, a common line 104a, two adjacent data lines 108, a semiconductor layer 107, at least one sub-pixel unit P, and the like. For example, the at least one gate line 104b and the at least one data line 108 correspond to the sub-pixel unit P, and the at least one gate line 104b and the at least one data line 108 are substantially staggered, for example: vertically disposed, but not limited to. In some embodiments, at least one sub-pixel unit P can be selectively disposed between the gate line 104b and two adjacent data lines 108, but is not limited thereto. In other embodiments, at least one sub-pixel unit P may not be disposed between the gate line 104b and two adjacent data lines 108. The at least one sub-pixel unit P has at least one thin film transistor TFT, a pixel electrode 130, an insulating layer 110, a transparent common electrode 140, and at least one protrusion electrode 130 b. The thin film transistor TFT includes a gate electrode G, a semiconductor layer 107, a source electrode 108b, and a drain electrode 108 a. The insulating layer 110 (shown in fig. 2) is located between the pixel electrode 130 and the transparent common electrode 140.

As shown in fig. 2, fig. 2 shows a cross-sectional structure of the array substrate 100 along the line 2-2' in fig. 1. Here, the common line 104a and the gate line 104b are respectively disposed on an inner surface of the substrate 102. The insulating layer 106 covers the common line 104a and the gate line 104 b. The semiconductor layer 107 is disposed on the insulating layer 106, and the insulating layer 106 separates the semiconductor layer 107 from the gate line 104 b. The drain electrode 108a and the source electrode 108b are disposed on the semiconductor layer 107, and the semiconductor layer 107 at least partially contacts the drain electrode 108a and the source electrode 108 b. The pixel electrode 130 partially covers a portion of the drain electrode 108a or the source electrode 108b, and is electrically connected to the drain electrode 108a or the source electrode 108 b. Here, the gate electrode G, the semiconductor layer 107, the drain electrode 108a, and the source electrode 108b shown in fig. 2 form a thin film transistor TFT. The thin film transistor TFT of the present embodiment is described by taking a bottom-gate thin film transistor (bottom-gate TFT) as an example, but the present invention is not limited thereto. In other embodiments, the thin film transistor TFT may also be a top-gate thin film transistor (top-gate TFT), such as: the semiconductor layer 107 is disposed under the gate G, and the semiconductor layer 107 and the gate G are sandwiched by an insulating layer 106, or other suitable type of thin film transistor. Then, another insulating layer 110 is further disposed on the pixel electrode 130, a contact hole 112 is correspondingly formed on a portion of the common line 104a, the contact hole 112 penetrates the insulating

layers

110 and 106, and further exposes a portion of the surface of the common line 104a, i.e., a portion of the surface of the common line 104a not covered by the insulating

layers

110 and 106, and a transparent common electrode 140 is formed on the insulating layer 110 and formed on the exposed surface of the common line 104a (or referred to as a portion of the surface of the common line 104a not covered by the insulating layers 110 and 106) through the contact hole 112, and further electrically connected to the common line 104 a. For example, the transparent common electrode 1410 and the pixel electrode 130 overlap at least partially in a vertical projection direction Z (or vertical projection onto the substrate 102), and the pixel electrode 130 and the transparent common electrode 140 are separated from each other. In the operation mode, when the pixel unit P is turned on, the potentials of the pixel electrode 130 and the transparent common electrode 140 are different.

As shown in fig. 1 and fig. 2, the pixel electrode 130 and the two adjacent data lines 108 do not overlap in the vertical projection direction Z (or vertical projection onto the substrate 102), but are not limited thereto. In other embodiments, the pixel electrode 130 overlaps at least one of the two adjacent data lines 108 in a vertical projection direction Z (or vertical projection onto the substrate 102). The pixel electrode 130 may be a plate electrode, i.e. the pixel electrode 130 has no slit (slit) design, but is not limited thereto. In other embodiments, the pixel electrode 130 may also have a slit (slit) design. The pixel electrode 130 includes a notch 130a, a contact hole 112 is disposed on the common line 104a of the portion exposed by the notch 130a, i.e. the common line 104a is not covered by the pixel electrode 130, and the contact hole 112 is disposed above the uncovered portion of the common line 104a, wherein the contact hole 112 penetrates the insulating

layers

106 and 110. Therefore, the corresponding portion of the common line 104a exposed by the contact hole 112 is electrically connected to the common line 104a through the contact hole 112 by the transparent common electrode 140 formed subsequently. For example, the notch 130a is disposed corresponding to the contact hole 112, and the notch 130a is adjacent to the contact hole 112 and has a contour C surrounding at least a portion of the contact hole 112. Furthermore, the transparent common electrode 140 includes a connection portion 140a, a plurality of slits 140b, and a slit electrode 140c, and the connection portion 140a is connected to at least one end of the plurality of slit electrodes 140 c. Wherein the transparent common electrode 140 is separated from the protruding electrode 130 b. The slits 140b of the transparent common electrode 140 respectively expose corresponding portions of the pixel electrode 130 located therebelow in the vertical projection direction Z (or vertical projection onto the substrate 102). The shape of the slit 140b and the slit electrode 140c are shown as being substantially "doglegged", but the shape of the slit 140b is not limited thereto, and may be, for example, a straight bar shape or other suitable shapes.

Referring to fig. 1 and 3, fig. 3 is an enlarged view of a region 150 of fig. 1 according to an embodiment of the invention. In the present embodiment, the sub-pixel unit P further includes a protruding electrode 130b, and the protruding electrode 130b is directly connected to the pixel electrode 130 and the protruding electrode 130b substantially extends toward the adjacent common line 104a along the first direction X shown in fig. 1. Here, the protruding electrode 130b is correspondingly disposed on the notch 130a of the adjacent pixel electrode 130, and the protruding electrode 130b and the notch 130a at least partially surround the corresponding contact hole 112. For example, the notch of the pixel electrode 130 and the protruding electrode 130b together form a concave profile C. In the present embodiment, the protruding electrode 130b is preferably located at least one corner (e.g., the upper right corner) of the pixel electrode 130, but the invention is not limited thereto. The protruding electrode 130b preferably differs depending on the position where the contact hole 112 is disposed. In other words, the protruding electrode 130b is not necessarily disposed at a corner of the pixel electrode 130.

As shown in fig. 3, the protruding electrode 130b is disposed at the corner of the pixel electrode 130 in the preferred embodiment. In other words, the contour C of the notch 130a of the pixel electrode 130 is respectively connected to the first side 130C and the second side 130d of the pixel electrode 130, wherein the first side 130C extends along the second direction Y, and the second side 130d extends along the first direction X, but in other embodiments, the first side 130C may extend along the second direction Y, and the second side 130d extends along the first direction X, which is not limited by the disclosure. The first side 130c is longer than the second side 130d as shown in fig. 3, but the invention is not limited thereto, and the first side 130c may be shorter than or substantially equal to the second side 130d in other embodiments. The first direction X of the present embodiment is substantially parallel to two adjacent data lines 108 (see fig. 1). For example, the protruding electrode 130b extends from a portion of the contour C, and the protruding electrode 130b extends along a first direction X toward the adjacent common line 104a along an extending direction, wherein the first direction X is substantially parallel to the two adjacent data lines 108, and the first direction X is substantially intersected with the common line 104a by the gate line 104b, for example: vertical, but not limited to.

In a preferred embodiment, the connecting portion 140a can be square, frame, or other suitable shape, and the inner side 140d of the connecting portion 140a is square or the inner side 140d of the frame. The distance D1 between the second side edge 130D of the pixel electrode 130 and the inner side edge 140D of the transparent common electrode 140. In other words, the second side 130D of the pixel electrode 130 corresponds to the first slit 140b of the transparent shared electrode 140, and a distance D1 between a side of the first slit 140b closest to the data line 180 (e.g., the right data line in fig. 1) and the second side 130D of the pixel electrode 130 is provided. The distance D1 is greater than or equal to 0 micrometer (μm) and less than or equal to about 4 micrometers (μm), preferably greater than or equal to 0 micrometer (μm) and less than or equal to about 2 micrometers (μm), and the projecting electrode 130b does not contact with the adjacent data line 108 (e.g., the data line on the right in fig. 1). However, in an alternative embodiment, the second side 130D of the pixel electrode 130 may be located on the left or right side of the inner side 140D of the transparent common electrode 140, and the distance D1 shown in FIG. 3 is only one possible example. The inner edge 140d of the transparent common electrode 140, in detail, the inner edge 140d of the connecting portion 140 a. The distance between the terminal point (or referred to as the topmost point) T of the projection electrode 130b and the connected pixel electrode 130 in the first direction X is a projection length D2, and the projection length D2 is preferably greater than 0 micrometer (μm) and less than or equal to about 4 micrometers (μm).

In the above embodiment, by disposing the pixel electrode 130, the protrusion electrode 130b and the transparent common electrode 140 on the substrate 102, during operation, the liquid crystal material (not shown, refer to the liquid crystal layer 250 of fig. 9) can be driven by the electric field generated by the combination of the transparent common electrode 140, the pixel electrode 130 and the protrusion electrode 130b to achieve the effect of wide viewing angle, and further by disposing the protrusion electrode 130b, the driving performance of the liquid crystal at the contact hole 112 near the connection between the transparent common electrode 140 and the common line 104a is improved, the dark line problem of the sub-pixel unit P at the contact hole 112 near the connection between the transparent common electrode 140 and the common line 104a is reduced, and the overall light transmittance performance of the sub-pixel unit P is improved, thereby improving the display performance of the sub-pixel unit P.

Referring to fig. 4, an enlarged view of a region 150 of fig. 1 according to another embodiment of the invention is shown. Here, the components in the embodiment shown in fig. 4 are substantially similar to those in fig. 3, except that the disposition position of the projecting electrode 130b is not the same as that of the projecting electrode 130b in fig. 3, and it is not further described herein. As shown in fig. 4, the contour C of the notch 130a of the pixel electrode 130 connects a first side 130C and a second side 130d of the pixel electrode 130, respectively, wherein the first side 130C extends along the first direction X, and the second side 130d extends along the second direction Y, and the first direction X is substantially parallel to the gate line 104 b. The protruding electrode 130b extends from the second side 130d to the adjacent data line 108 (e.g. the data line 108 on the right in fig. 4) in the first direction X, so that the extending direction of the protruding electrode 130b is substantially staggered with the data line 108 (e.g. the data line 108 on the right in fig. 4), for example: substantially perpendicular to each other, and the junction F of the protruding electrode 130b and the second side 130D of the connected pixel electrode 130 has a length D3 substantially parallel to the Y direction shown in fig. 4. For example, the connection point F is formed at the connection point of the projection electrode 130b and the contour C, and the length D3 of the projection electrode 130b from the connection point F on the second side 130D is greater than or equal to about 2 micrometers (μm) and less than or equal to about 10 micrometers (μm), preferably greater than or equal to about 4 micrometers (μm) and less than or equal to about 10 micrometers (μm). In other words, the joint F between the protruding electrode 130b and the second side 130D of the connected pixel electrode 130 is a long side S, and the long side S has a length D3 in the second direction Y. Moreover, the protrusion electrode 130b extends toward the adjacent data line 108 (e.g., the data line 108 on the right in fig. 4) in the first direction X by a distance D1, the distance D1 is greater than or equal to 0 micrometer (μm) and less than or equal to about 4 micrometers (μm), preferably greater than or equal to 0 micrometer (μm) and less than or equal to about 2 micrometers (μm), and the protrusion electrode 130b does not contact with the adjacent data line 108 (e.g., the data line 108 on the right in fig. 4). For example, the distance D1 in fig. 4 is the shortest distance between the terminal point (or referred to as the topmost point) T of the protruding electrode 130b and the inner edge 140D of the transparent common electrode 140, wherein the definition of the inner edge 140D is the same as that in fig. 1. In other words, the second side 130D of the pixel electrode 130 corresponds to the first slit 140b of the transparent common electrode 140, and the side of the first slit 140b closest to the data line 180 (e.g., the data line on the right in fig. 4) is a distance D1 from the endpoint (or referred to as the topmost end) T of the projection electrode 130b on the second side 130D of the pixel electrode 130. It should be noted that in fig. 3, the protruding electrode 130b does not protrude and extend in a direction substantially parallel to the common line 104a, so that the distance D1 in fig. 3 is measured by the shortest distance between the second side 130D of the pixel electrode 130 and the inner side 140D of the transparent common electrode 140. However, in an alternative embodiment, the terminal point T of the projecting electrode 130b may be located on the left side or the right side of the inner edge 140D of the transparent common electrode 140, and the distance D1 shown in FIG. 4 is only one possible example.

Referring to fig. 5, fig. 5 shows the simulation results of the light transmittance of the array substrate shown in fig. 4 at a distance D1 (i.e., D1 is about 1.5 micrometers (μm)) and at several different lengths D3 (or extension lengths). The light transmittance (%) is unitless, and for example, the visible light band is used as the measurement light. As shown in fig. 5, it can be understood that when the length D3 is greater than about 2 micrometers (μm), the light transmittance of the array substrate is improved, and when the length D3 is about 10 micrometers (μm), the light transmittance is saturated. Therefore, when the length D exceeds 10 micrometers (μm) or more, the parasitic capacitance between the pixel electrode 130 and the data line 108 becomes large. By properly controlling the size of the protrusion electrode 130b, the driving performance of the liquid crystal at the contact hole 112 near the connection of the transparent common electrode 140 and the common line 104a can be increased, the dark line problem of the sub-pixel unit P at the contact hole 112 near the connection of the transparent common electrode 140 and the common line 104a can be reduced, and the overall light transmittance performance of the sub-pixel unit P can be improved, thereby improving the display performance of the sub-pixel unit P. However, the scope of the present invention should be determined only by the following claims.

Referring to fig. 6, an enlarged schematic view of the area 150 of fig. 1 according to yet another embodiment of the invention is shown, the inner element of the embodiment shown in fig. 6 is substantially similar to the elements shown in fig. 3 and 4, except that the arrangement of the protrusion electrode 130b is adjusted to be different from the arrangement of the protrusion electrode 130b in fig. 3 and 4, as described above, wherein, as shown in fig. 6, the contour C of the notch 130a of the pixel electrode 130 is respectively connected to the first side 130C and the second side 130D of the pixel electrode 130, wherein the protrusion electrode 130b may optionally extend from one of the first direction X and the second direction Y, and then extends from the other of the first direction X and the second direction Y, for example, the first side 130C extends along the first direction X shown in fig. 6, and the second side 130D extends along the second direction Y shown in fig. 6, as a protrusion line 130D, and a protrusion line 130D, the protrusion line 130D is preferably larger than a protrusion line 130D along the length D130D along the length of the length 130D along the longitudinal direction 130D direction 130D, wherein the protrusion line 130D, the protrusion line 130D is larger than the length D of the protrusion line 130D, and the protrusion line 130D of the protrusion line 130D, the protrusion line 130D direction 130D is larger than the protrusion line 130D, and the protrusion line 130D direction 130D, and the length of the protrusion line 130D direction 130D is larger than the length of the protrusion line 130D direction 130D, and the length of the protrusion line 130D direction 130D of the protrusion line 130D, the length of the protrusion line 130D direction 130D is larger than the protrusion line 130D direction 130D, and the length of the protrusion line 130D direction 130D, and the protrusion line 130D of the length of the protrusion line 130D direction 130D of the protrusion line 130D direction 130D, the protrusion line 130D, and the protrusion line 130D, the protrusion line 130D of the protrusion line 130D is larger than the protrusion line 130D direction of the protrusion line 130D, the length of the protrusion line 130D direction of the protrusion line 130D, the protrusion line 130D direction of the length of the protrusion line 130D, the length of the protrusion line 130D is larger than the protrusion line 130D direction of the length of the protrusion line 130D direction 130D, the protrusion line 130D direction of the protrusion line 130D, the protrusion line 130D of the length of the protrusion line 130D direction of the protrusion line 130D, the protrusion line 130D of the protrusion line 130D, the protrusion line 130D direction of the protrusion line 130D, the length of the protrusion line 130D, the protrusion line 130D direction of the length of the protrusion line 130D is larger than the protrusion line 130D direction of the first direction of the second longitudinal direction of the first direction of the second longitudinal direction of the protrusion line 130D direction of the protrusion line 130.

Referring to fig. 7, fig. 7 is a graph illustrating light transmittance of an array substrate according to an embodiment of the invention. Fig. 7 shows simulation results of light transmittance of the array substrate shown in fig. 4 at different distances D1. The light transmittance (%) is unitless, and for example, the visible light band is used as the measurement light. As shown in fig. 7, it can be understood that the overall light transmittance of the sub-pixel unit P is the maximum when the distance D1 between the second side edge 130D of the pixel electrode 130 and the inner side edge 140D of the transparent shared electrode 140 is equal to 0 micrometer (μm). That is, when the defined shortest distance D1 between the second side 130D of the pixel electrode 130 and the inner side 140D of the transparent common electrode 140 in fig. 1-3 and the defined shortest distance D1 between the terminal T of the protrusion electrode 130b and the inner side 140D of the transparent common electrode 140 in fig. 4 and 6 are preferably less than or equal to 2 micrometers (μm), it is helpful to increase the light transmittance of the array substrate, and the driving performance of the liquid crystal at the contact hole 112 near the connection between the transparent common electrode 140 and the common line 104a reduces the dark line problem of the sub-pixel unit P at the contact hole 112 near the connection between the transparent common electrode 140 and the common line 104a, and further increases the overall light transmittance performance of the sub-pixel unit P to improve the display performance of the sub-pixel unit P.

Referring to fig. 8, a top view of an array substrate 100' according to another embodiment of the invention is shown. Here, the illustrated structure in the embodiment shown in fig. 8 is substantially similar to the illustrated structure in fig. 1, except that the pixel electrode 130 is electrically connected to the TFT on the same side of the corresponding contact hole 112. The pixel electrode 130 shown in fig. 1 is electrically connected to the TFT on the other side of the corresponding contact hole 112. Similarly, the cross-section along line 2-2' in FIG. 8 has a similar structure to that of the array substrate 100 shown in FIG. 2.

In several embodiments shown in fig. 1-8, the substrate 102 may be made of glass, organic materials, or other suitable materials. At least one of the insulating

layers

106 and 110 may be a single layer or a multi-layer structure, and the material thereof may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof), an organic material (e.g., photoresist (including color photoresist or transparent photoresist), Polyimide (PI), benzocyclobutene (BCB), Epoxy (Epoxy), Perfluorocyclobutane (PFCB), other suitable materials, or a combination thereof), or other suitable materials, or a combination thereof. The semiconductor layer 107 may be a single layer or a multi-layer structure and may have a material composition including polycrystalline silicon, single crystal silicon, microcrystalline silicon, amorphous silicon, an organic semiconductor material, a metal oxide semiconductor material, or other suitable materials, or a combination of at least two of the foregoing. At least one of the data line 108, the common line 104a and the gate line 104b may be a single layer or a multi-layer structure, preferably a metal, an alloy, a metal oxide, a metal nitride, a metal oxynitride, an organic conductive material, or other suitable materials in view of conductivity. At least one of the pixel electrode 130, the projecting electrode 130b and the transparent common electrode 140 may be a single-layer or multi-layer structure, and is made of a transparent conductive material (such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxides, or stacked layers of at least two of the foregoing), carbon nanotubes/rods, an organic conductive material, or a reflective material with a thickness of less than 60 angstroms, or other suitable oxides, or stacked layers of at least two of the foregoing), and the pixel electrode 130 and/or the projecting electrode 130b may also include a reflective conductive material (such as: the material of the lines (e.g., data lines 108, gate lines 104b, or common lines 104 a)) or the transflective conductive material (e.g.: selection of the aforementioned materials). The material of the transparent common electrode 140 may be substantially the same as or different from that of the pixel electrode 110. Furthermore, the protrusion electrode 130b directly connected and electrically connected to the pixel electrode 130 and the pixel electrode 130 can be integrally formed by the same film layer and substantially the same material, so that the protrusion electrode and the pixel electrode 130 can be formed by defining the same micro-shadow mask without additional process steps, and thus the protrusion electrode 130b has the advantage of simple manufacturing, but is not limited thereto. In other embodiments, the pixel electrode 130 may also be formed of a different layer and/or a different material than the projection electrode 130 b. In addition, the fabrication of the other components can be accomplished by conventional array substrate processes, and therefore, the related fabrication is not described in detail herein.

In the embodiments shown in fig. 1-8, since the protrusion electrode 130b and the pixel electrode 130 are partially overlapped with the common electrode 140 above the protrusion electrode 130b in the vertical projection direction, when displaying an image, the electric field generated by the combination of the common electrode 140, the pixel electrode 130 and the protrusion electrode 130b can drive the liquid crystal material (not shown, refer to the liquid crystal layer 250 of fig. 9) to achieve the effect of wide viewing angle, and the protrusion electrode 130b is additionally disposed to improve the driving performance of the liquid crystal at the contact hole 112 adjacent to the connection of the common electrode 140 and the common line 104a, reduce the generation of the undesirable black line problem at the contact hole 112 adjacent to the connection of the common electrode 140 and the common line 104a of the sub-pixel unit P, and further improve the overall light transmittance performance of the sub-pixel unit P, thereby improving the display performance of the sub-pixel unit P.

In other embodiments, the shape of the slit 140b in the common electrode 140 can have a shape such as a bar or other suitable shape, rather than the generally "dogleg" shape shown in the several embodiments shown in fig. 1, 3-4, 6, and 8. Furthermore, the connecting portion 140a of the common electrode 140 does not completely cover the slits 140b, and one end of the slit 140b may be exposed and only one end of the slit is connected to the connecting portion 140 a. In addition, the position of the notch 130b of the pixel electrode 130 is not limited to the position shown in the embodiments shown in fig. 1, fig. 3-4, fig. 6 and fig. 8 or at least one corner of the pixel electrode 130, and may be adjusted appropriately according to the position of the contact hole 112, or may be formed at other corners or other positions of the pixel electrode 130.

Fig. 9 shows a cross-sectional view of an lcd panel 300 according to an embodiment of the invention. As shown in fig. 9, the liquid crystal display panel 300 includes an array substrate 100 or 100', an opposite substrate 200, and a liquid crystal layer 250 disposed between the opposite substrate 200 and the substrate 102. In one embodiment, the substrate 102 in the lcd panel 300 may include the array substrate 100 or 100' shown in fig. 1, 3-4, 6 and 8 and at least one sub-pixel unit P thereon, and may further include other required components (not shown). The opposite substrate 200 may further include other components such as a color conversion layer (not shown), and the material of the opposite substrate 200 may be the material of the substrate 100 or 100', but the materials of the above components may be substantially the same or different.

In summary, in the array substrate and the liquid crystal display panel of the invention, by the arrangement of the protruding electrode electrically and physically connected to the pixel electrode, the electric field driving effect on the liquid crystal material is further enhanced, and the driving performance of the liquid crystal at the contact hole adjacent to the connection of the common electrode and the common line is improved, thereby reducing the generation of the black line problem of the sub-pixel unit at the adjacent contact hole and improving the overall light transmittance performance of the sub-pixel unit, and further improving the display performance of the sub-pixel unit and the liquid crystal display panel including the sub-pixel unit.

The present invention is capable of other embodiments, and various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An array substrate, comprising:

a substrate;

a gate line disposed on the substrate;

a common line disposed on the substrate and parallel to the gate line;

two adjacent data lines arranged on the substrate; and

at least one sub-pixel unit disposed on the substrate, the sub-pixel unit including:

a thin film transistor including a source, a drain and a gate, wherein the gate is electrically connected to the gate line;

an insulating layer disposed on the thin film transistor and having a contact hole;

a pixel electrode disposed on the substrate and electrically connected to the drain, the pixel electrode having at least one notch;

a transparent common electrode disposed on the insulating layer, wherein the transparent common electrode and the pixel electrode are partially overlapped in a vertical projection direction, and the transparent common electrode is connected to the common line via the contact hole, wherein the gap corresponds to the contact hole and is adjacent to the contact hole; and

a projecting electrode disposed on the substrate, wherein the projecting electrode is connected to the pixel electrode, is adjacent to the notch, and extends along a first direction;

the joint of the projecting electrode and the pixel electrode is provided with a long edge, and the long edge is more than or equal to 2 microns and less than or equal to 10 microns.

2. The array substrate of claim 1, wherein the first direction is parallel to the gate line extending direction.

3. The array substrate of claim 1, wherein the protruding electrodes further extend along a second direction, the first direction is parallel to the extending direction of the gate lines, and the second direction is parallel to the extending direction of the two adjacent data lines.

4. The array substrate of claim 1, wherein the first direction forms an angle with the extending direction of the gate line, the angle being greater than 0 degree and less than 90 degrees.

5. The array substrate of claim 1, wherein the notch is located at least one corner of the pixel electrode.

6. The array substrate of claim 1, wherein the pixel electrode has a first side and a second side, and the notch has a contour connecting the first side and the second side, respectively.

7. The array substrate of claim 6, wherein the protruding electrode extends from the first side.

8. The array substrate of claim 6, wherein the protruding electrode extends from a portion of the outline.

9. The array substrate of claim 6, wherein the pixel electrode and the two adjacent data lines do not overlap in the vertical projection direction.

10. The array substrate of claim 1, wherein the transparent common electrode has a plurality of slits, and the pixel electrode does not have a plurality of slits.

11. The array substrate of claim 10, wherein the transparent common electrode has an inner edge parallel to the two adjacent data lines, and the distance between the pixel electrode and the inner edge is greater than or equal to 0 micron and less than or equal to 4 microns.

12. The array substrate of claim 1, wherein the opening has a profile, and the profile surrounds at least a portion of the contact hole.

13. A liquid crystal display panel, comprising:

the array substrate of any one of claims 1 to 12;

an opposite substrate arranged opposite to the array substrate; and

a liquid crystal layer arranged between the array substrate and the opposite substrate.