CN110543046A - display panel - Google Patents
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- CN110543046A CN110543046A CN201910851716.5A CN201910851716A CN110543046A CN 110543046 A CN110543046 A CN 110543046A CN 201910851716 A CN201910851716 A CN 201910851716A CN 110543046 A CN110543046 A CN 110543046A
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- pixel color
- pixel
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133514—Colour filters
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
- G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The display panel comprises a first substrate, a second substrate opposite to the first substrate, a first sub-pixel color layer, a second sub-pixel color layer and a third sub-pixel color layer, wherein the first sub-pixel color layer, the second sub-pixel color layer and the third sub-pixel color layer are arranged on one of the first substrate or the second substrate, a first supporting structure is arranged between the first substrate and the second substrate, and a plurality of second supporting structures are arranged between the first substrate and the second substrate. In the direction perpendicular to the first substrate, the first support structure overlaps the first subpixel color layer. The first sub-pixel color layer has a first convex portion and a first concave portion. The second sub-pixel color layer has a second protrusion. The second convex portion is fitted into the first concave portion. The orthographic projection of the first supporting structure on the first substrate overlaps the orthographic projection of the first convex part on the first substrate. The first sub-pixel color layer has a first thickness H1, the second sub-pixel color layer has a second thickness H2, and H1 is greater than H2.
Description
Technical Field
The present invention relates to a display panel, and more particularly, to a display panel having a support structure overlapping convex portions of pixel color layers.
Background
With the development of the electro-optical and semiconductor technologies, the development of the flat panel display is driven, and among the flat panel displays, the liquid crystal display has superior characteristics of high space utilization efficiency, low power consumption, no radiation, low electromagnetic interference, and the like, so that the liquid crystal display becomes the mainstream of the market.
Currently, the market demands for the performance of liquid crystal displays are moving toward the characteristics of high resolution, high contrast, and wide viewing angle. In order to improve the resolution and display quality of the lcd, the design of increasing the aperture ratio of the pixel becomes an urgent problem in the art.
Disclosure of Invention
The invention provides a display panel, which can improve the aperture ratio of pixels and the display quality of the display panel.
The display panel comprises a first substrate, a second substrate opposite to the first substrate, a pixel array arranged on the first substrate, a first data line arranged on the first substrate, a first grid line and a second grid line arranged on the first substrate, a first sub-pixel color layer, a second sub-pixel color layer and a third sub-pixel color layer arranged on one of the first substrate and the second substrate, a first supporting structure arranged between the first substrate and the second substrate, and a plurality of second supporting structures arranged between the first substrate and the second substrate. The first gate line and the second gate line are crossed with the first data line, and the first data line, the first gate line and the second gate line are electrically connected with the pixel array. The orthographic projections of the first sub-pixel color layer, the second sub-pixel color layer and the third sub-pixel color layer on the first substrate are positioned between the orthographic projections of the first gate line and the second gate line on the first substrate, and the second sub-pixel color layer is positioned between the first sub-pixel color layer and the third sub-pixel color layer. In the direction perpendicular to the first substrate, the first support structure overlaps the first subpixel color layer. The second support structure is respectively overlapped with the second sub-pixel color layer and the third sub-pixel color layer in the direction vertical to the first substrate. The first sub-pixel color layer has a first convex portion and a first concave portion. The second sub-pixel color layer has a second protrusion. The third subpixel color layer has a third protrusion. The second convex part is embedded into the first concave part at the adjacent boundary of the first sub-pixel color layer and the second sub-pixel color layer. In a direction perpendicular to the first substrate, an orthographic projection of the first supporting structure on the first substrate overlaps an orthographic projection of the first convex portion on the first substrate. An orthographic projection of one of the second supporting structures on the first substrate overlaps an orthographic projection of the second convex part on the first substrate. The first sub-pixel color layer has a first thickness H1, the second sub-pixel color layer has a second thickness H2, and H1 is greater than H2.
The display panel comprises a first substrate, a second substrate opposite to the first substrate, a pixel array arranged on the first substrate, a first data line arranged on the first substrate, a first gate line and a second gate line arranged on the first substrate, a first sub-pixel color layer and a second sub-pixel color layer arranged on one of the first substrate and the second substrate, and a first supporting structure arranged between the first substrate and the second substrate. The first gate line and the second gate line are crossed with the first data line, and the first data line, the first gate line and the second gate line are electrically connected with the pixel array. The orthographic projections of the first sub-pixel color layer and the second sub-pixel color layer on the first substrate are positioned between the orthographic projections of the first gate line and the second gate line on the first substrate. The first subpixel color layer is disposed adjacent to the second subpixel color layer. The first data line is overlapped on the adjacent boundary of the first sub-pixel color layer and the second sub-pixel color layer, and the first data line and the first gate line are provided with openings. The orthographic projection of the first supporting structure on the first substrate is overlapped with the opening.
The display panel provided by the invention is provided with a pixel array and comprises a first substrate, a second substrate and a display medium layer. The first substrate has a plurality of gate lines including a first gate line and a second gate line, a plurality of data lines including a first data line, and a plurality of common electrode lines. The data lines and the gate lines are configured in different directions. The second substrate is provided with a first sub-pixel color layer arranged on the first substrate and the second substrate, and a common electrode layer arranged on the second substrate and covering the first sub-pixel color layer. The display medium layer is arranged between the first substrate and the second substrate. At least part of the pixels comprise a first sub-pixel area and a second sub-pixel area. The first sub-pixel area is provided with a first pixel electrode arranged on the first substrate and electrically connected to the first data line through the first switch element. The second sub-pixel area is provided with a second pixel electrode arranged on the first substrate and electrically connected to the first data line through a second switch element. The second pixel electrode is also connected to the first capacitor through a third switching element. Wherein the first subpixel color layer has a first protrusion. The first supporting structure is arranged on the second substrate and overlaps the first convex portion.
In view of the above, the light-shielding layer of the display panel according to an embodiment of the invention may be disposed corresponding to the pixel array, the data line, and the first supporting structure or the second supporting structure. Therefore, the display panel can integrate the light shielding layer required for arranging the first support structure and/or the second support structure and the light shielding layer for shielding the pixel array into the first light shielding pattern and/or the second light shielding pattern. Therefore, the area occupied by the whole light shielding layer can be reduced, and the aperture opening ratio and the display quality of the pixels of the display panel are improved.
in addition, the first thickness of the first subpixel color layer is greater than the second thickness of the second subpixel color layer. As such, the first support structure overlapping the first light shielding pattern may overlap and contact the first protrusion or the first light shielding pattern. The second support structure overlapping the second light shielding pattern may overlap but not contact the second protrusion or the second light shielding pattern. Therefore, the first supporting structure and the second supporting structure can be used as a main supporting structure and an auxiliary supporting structure respectively. Under the above arrangement, the display panel can control the thickness of the sub-pixel color layer and the heights of the first supporting structure and the second supporting structure, so that the first supporting structure and the second supporting structure can respectively provide the support and the elasticity required by the display panel, thereby improving the reliability and the quality of the display panel.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
fig. 1 is a schematic top view of a sub-pixel color layer of a display panel according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of the display panel of fig. 1 along a sectional line a-a'.
Fig. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the invention.
Fig. 4A is a schematic cross-sectional view illustrating a display panel according to another embodiment of the invention.
Fig. 4B is a partially enlarged schematic cross-sectional view of a first light shielding pattern according to another embodiment of the invention.
fig. 5 is a schematic cross-sectional view of a display panel according to another embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a display panel according to still another embodiment of the present invention.
fig. 7 is a schematic cross-sectional view illustrating a display panel according to still another embodiment of the invention.
Fig. 8 is a schematic partial top view illustrating a display panel according to another embodiment of the invention.
Fig. 9 is a partially enlarged schematic top view of a first opening of a display panel according to another embodiment of the invention.
Fig. 10 is a schematic cross-sectional view of the display panel of fig. 9 along the section line B-B'.
Fig. 11 is a partially enlarged schematic top view illustrating a second opening of a display panel according to still another embodiment of the invention.
Fig. 12 is a schematic cross-sectional view of the display panel of fig. 11 along the section line C-C'.
Fig. 13 is a partially enlarged top view schematically illustrating a second opening according to another embodiment of the present invention.
Fig. 14A is a schematic circuit diagram of a pixel array of a display panel according to another embodiment of the invention.
Fig. 14B is a schematic circuit diagram of a pixel array of a display panel according to another embodiment of the invention.
Fig. 15 is an equivalent circuit diagram of a display panel according to another embodiment of the present invention.
description of reference numerals:
10. 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I', 10J: display panel
100: first substrate
120: gate insulating layer
140: a first insulating layer
160. 260: sub-pixel color layer
161. 261: first sub-pixel color layer
161A, 261A: first convex part
161B: first concave part
162. 262: second sub-pixel color layer
162A, 262A: second convex part
163. 263: third sub-pixel color layer
163A: third convex part
163B: third concave part
164: fourth sub-pixel color layer
164B: the fourth concave part
165: fifth sub-pixel color layer
165A: fifth convex part
166. 266: sixth sub-pixel color layer
166B: sixth concave part
180. 180A: a second insulating layer
181. 181A, 181B, 221: surface of
183. 223: side wall
200: second substrate
220: common electrode layer
242: flat part
244: protrusion part
243: containing space
241: surface of the flat part
245; lower surface of the protrusion
A-A ', B-B ', C-C ': section line
BM: light shielding layer
BM1, BM 1': a first light shielding pattern
BM 2: second light-shielding pattern
BM 3: third light-shielding pattern
BM 4: fourth light-shielding pattern
BM 5: fifth light-shielding pattern
BM 6: sixth light-shielding pattern
C: electric charge
c1, C2: storage capacitor
CCS: first capacitor
CH 1: first semiconductor layer
CH 2: a second semiconductor layer
CH 3: third semiconductor layer
COM: common electrode wire
D1: a first drain electrode
D2: second drain electrode
DL, DLm-DLm + 2: data line
DL 1: first data line
DL 1A: first branch
DL 1B: second branch
DL 2: second data line
DL 3: third data line
G1: a first grid electrode
G2: second grid
g3: third grid
H1: a first thickness
H2: second thickness
H3, H4: height
H5, H6: thickness of
K1, K2, K3, K4, K5, K6: distance between each other
LC: display medium layer
N: direction of rotation
N1: a first direction
N2: second direction
O1: first opening
O2: second opening
PA: pixel array
PE: pixel electrode
PE 1: a first pixel electrode
PE 2: second pixel electrode
PX 1: a first sub-pixel region
PX 2: second sub-pixel region
PS1, PS 3: first supporting structure
PS1A, PS2A, PS3A, PS 4A: the top surface
PS1B, PS2B, PS3B, PS 4B: bottom surface
PS2, PS 4: second support structure
S1: a first source electrode
S2: second source electrode
SL, SLn to SLn + 4: gate line
SL 1: a first gate line
SL 2: a second gate line
SL 3: third gate line
A TFT: switching element
TFT 1: a first switch element
TFT 2: second switch element
TFT 3: third switching element
V1: a first voltage potential
v2: second voltage potential
w1, W1A: first width
W2: second width
X: height difference
Detailed Description
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present invention.
In the drawings, the thickness of various elements and the like are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" or "overlapping" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physically and/or electrically connected.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.
Fig. 1 is a schematic partial top view of a sub-pixel color layer of a display panel according to an embodiment of the invention, and fig. 1 schematically illustrates only some of the components for convenience of illustration and observation. Fig. 2 is a schematic cross-sectional view of the display panel of fig. 1 along a sectional line a-a'. Referring to fig. 1 and fig. 2, in the present embodiment, the display panel 10 includes a first substrate 100, a second substrate 200, a pixel array PA, a plurality of data lines DL, a plurality of gate lines SL, a sub-pixel color layer 160, a pixel electrode PE, a first supporting structure PS1, a plurality of second supporting structures PS2, a common electrode layer 220, a light shielding layer BM, and a display medium layer LC. In the present embodiment, the Display panel 10 is, for example, a Liquid Crystal Display (LCD), but the invention is not limited thereto. In some embodiments, the display panel 10 may also be a Light-Emitting Diode display panel (LED display), an Organic Light-Emitting Diode display panel (OLED display), or an Electrophoretic display panel (EPD).
referring to fig. 1 and 2, the display panel 10 includes a first substrate 100 and a second substrate 200 disposed opposite to the first substrate 100. The first substrate 100 and the second substrate 200 are made of glass, quartz, plastic, organic polymer, opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material) or other suitable materials. In some embodiments, the first substrate 100 and the second substrate 200 may also be flexible substrates, and the materials thereof include organic polymers, such as: polyimide (PI), polyethylene naphthalate (PEN), or other suitable material, although the invention is not limited thereto. In the embodiment, the materials of the first substrate 100 and the second substrate 200 may be the same or different, but the invention is not limited thereto.
As shown in fig. 2, a plurality of gate lines SL are disposed on the first substrate 100. The plurality of gate lines SL include a first gate line SL1 and a second gate line SL2 disposed on the first substrate 100, but the invention is not limited thereto. The first gate line SL1 is parallel to the second gate line SL 2. The gate insulating layer 120 is disposed on the first substrate 100 and covers the gate lines SL. The data lines DL are disposed on the gate insulating layer 120 and cross the gate lines SL. The data lines DL include a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, a fifth data line DL5 and a sixth data line DL 6. The plurality of data lines DL are respectively disposed parallel to each other. For example, the second data line DL2 is disposed in parallel with the first data line DL1, and the third data line DL3 is disposed in parallel with the second data line DL2, but not limited thereto. It should be understood by one skilled in the art that the number of the gate lines SL and the data lines DL can be set according to the user's requirement, and is not limited to the number shown in fig. 2.
Generally, the gate lines SL and the data lines DL are made of metal materials for conductivity, but other suitable conductive materials may be used. For example: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.
As shown in fig. 2, the pixel array PA is disposed on the first substrate 100. In other words, the first substrate 100 is, for example, an array substrate of the display panel 10, but the invention is not limited thereto. The pixel array PA is formed by arraying a plurality of switching elements, for example. In general, the pixel array PA may have a single-layer or multi-layer structure, and includes a plurality of switching elements and a plurality of insulating layers. The pixel array PA is electrically connected to a plurality of signal lines (e.g., a plurality of gate lines SL and a plurality of data lines DL).
As shown in fig. 2, the pixel array PA includes a first switching element TFT1, a second switching element TFT2, and a third switching element TFT3 disposed on the first substrate 100. In some embodiments, the pixel array PA may further include more switching elements, not limited to the one shown in fig. 2. For example, the switching element is a low temperature polysilicon thin film transistor (LTPS) or an amorphous silicon thin film transistor (a-Si), but the invention is not limited thereto. In this embodiment, the first switching element TFT1, the second switching element TFT2, and the third switching element TFT3 have the same structure and material. For example, the first switching element TFT1 includes a first gate G1 and a first semiconductor layer CH 1. By analogy, the second switching element TFT2 is disposed adjacent to the first switching element TFT1, and the second switching element TFT2 includes a second gate electrode G2 and a second semiconductor layer CH 2. The third switching element TFT3 is disposed adjacent to the second switching element TFT2, and the second switching element TFT2 is located between the first switching element TFT1 and the second switching element TFT 2. The third switching element TFT3 includes a third gate G3 and a third semiconductor layer CH 3.
In the present embodiment, the first switching element TFT1 is electrically connected to the first gate line SL1 through the first gate G1. For example, the first gate G1 and the first gate line SL1 are formed from the same film and electrically connected to each other. Similarly, the second gate G2 of the second switching element TFT2 and the first gate line SL1 are made of the same film and electrically connected to each other. The third gate G3 of the third switching element TFT3 and the first gate line SL1 are made of the same film and electrically connected to each other. In other words, the adjacent first switching element TFT1, second switching element TFT2 and third switching element TFT3 are electrically connected to the same signal line (first gate line SL 1). In the present embodiment, the materials of the first gate G1, the second gate G2, the third gate G3 and the gate line SL may be the same, and are not described herein again.
The materials of the first semiconductor layer CH1, the second semiconductor layer CH2, and the third semiconductor layer CH3 include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium germanium zinc oxide, or other suitable materials, or combinations thereof), or other suitable materials, or include dopants (dopants) in the above materials, or combinations thereof, but the invention is not limited thereto.
In the present embodiment, the first data line DL1 is disposed corresponding to the first switching element TFT1 and electrically connected to the first semiconductor layer CH 1. The first switching element TFT1 further includes a first source and a first drain (not shown) electrically connected to the first semiconductor layer CH1, respectively, and the first data line DL1 may be electrically connected to the first source of the first switching element TFT1 for providing a driving signal to the first switching element TFT 1. In the present embodiment, the first data line DL1 and the first drain are made of the same film, for example, but the invention is not limited thereto.
as shown in fig. 2, the second data line DL2 is disposed corresponding to the second switching element TFT2 and electrically connected to the second semiconductor layer CH 2. In this embodiment, the second switching element TFT2 further includes a second source and a second drain (not shown) electrically connected to the second semiconductor layer CH2, respectively, and the second data line DL2 may be electrically connected to the second source of the second switching element TFT2 for providing a driving signal to the second switching element TFT 2. In the present embodiment, the second data line DL2 and the second drain are made of the same film, for example, but the invention is not limited thereto. The third data line DL3 is disposed corresponding to the third switching element TFT3 and electrically connected to the third semiconductor layer CH 3. In the present embodiment, the third switching element TFT3 also includes a source and a drain (not shown). The third data line DL3 may be electrically connected to the third switching element TFT3 to provide a driving signal to the third switching element TFT 3.
In the present embodiment, the first source and the second source, and the first drain and the second drain are made of metal materials, but the invention is not limited thereto, and according to other embodiments, other suitable conductive materials may be used for the first source and the second source, and the first drain and the second drain. For example: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.
In the embodiment, the first switching element TFT1, the second switching element TFT2 and the third switching element TFT3 are, for example, bottom gate thin film transistors (bottom gate TFTs), but the invention is not limited thereto. In other embodiments, the first switching element TFT1, the second switching element TFT2, and the third switching element TFT3 may also be top gate thin film transistors (top gate TFTs) or other suitable thin film transistors.
As shown in fig. 2, in a direction N perpendicular to the first substrate 100, an orthographic projection of the first data line DL1 on the first substrate 100 overlaps an orthographic projection of the first gate G1 on the first substrate 100. The orthographic projection of the second data line DL2 on the first substrate 100 overlaps the orthographic projection of the second gate G2 on the first substrate 100. The orthographic projection of the third data line DL3 on the first substrate 100 overlaps the orthographic projection of the third gate G3 on the first substrate 100.
The first insulating layer 140 is disposed on the gate insulating layer 120, and covers the corresponding pixel array PA and the plurality of data lines DL (e.g., including the first data line DL1, the second data line DL2, and the third data line DL3) electrically connected to the pixel array PA. The material of the first insulating layer 140 and the gate insulating layer 120 includes inorganic material, organic material, or a combination thereof, or other suitable materials. Such inorganic materials are for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the foregoing materials. Examples of such organic materials are (but not limited to): a polymer material such as a polyimide resin, an epoxy resin or an acryl resin. In the present embodiment, the gate insulating layer 120 and the first insulating layer 140 are respectively a single layer, but the invention is not limited thereto. In other embodiments, the gate insulating layer 120 and the first insulating layer 140 may also be formed by stacking a plurality of layers.
Referring to fig. 1 and 2, the sub-pixel color layer 160 is disposed on the first insulating layer 140 and covers a plurality of data lines DL (for example, as shown in fig. 2, the sub-pixel color layer includes a first data line DL1 and a second data line DL2), but the invention is not limited thereto. In some embodiments, the subpixel color layer 160 may be disposed on one of the first substrate 100 or the second substrate 200. The material of subpixel color layer 160 includes, for example, a color photoresist material. The following embodiments are described with the first insulating layer 140 having the sub-pixel color layer 160 disposed on the first substrate 100. In other words, the display panel 10 includes the first substrate 100 integrating the sub-pixel Color layer 160 onto the pixel Array PA (COA).
as shown in fig. 1 and 2, the sub-pixel color layers 160 include a first sub-pixel color layer 161, a second sub-pixel color layer 162, and a third sub-pixel color layer 163, which are arranged in order from left to right, but the present invention is not limited thereto. As shown in fig. 1, the sub-pixel color layers 160 may further include a fourth sub-pixel color layer 164, a fifth sub-pixel color layer 165, and a sixth sub-pixel color layer 166, which are sequentially arranged from left to right. In the present embodiment, the second subpixel color layer 162 is positioned between the first subpixel color layer 161 and the third subpixel color layer 163. Since fig. 2 is a partial cross-sectional view along a sectional line a-a' of fig. 1, the first sub-pixel color layer 161, the second sub-pixel color layer 162, and the third sub-pixel color layer 163 will be described first. The relative positional relationship of the fourth sub-pixel color layer 164, the fifth sub-pixel color layer 165, and the sixth sub-pixel color layer 166 will be described later.
As shown in fig. 1 and 2, an orthogonal projection of the first sub-pixel color layer 161 on the first substrate 100 overlaps the first switching element TFT1, and an orthogonal projection of the second sub-pixel color layer 162 on the second substrate 200 overlaps the second switching element TFT2 and the third switching element TFT 3. As shown in fig. 1, the orthographic projection parts of the first sub-pixel color layer 161, the second sub-pixel color layer 162 and the third sub-pixel color layer 163 on the first substrate 100 are located between the orthographic projection parts of the first gate line SL1 and the second gate line SL2 on the first substrate 100.
in the present embodiment, the first subpixel color layer 161 has a first protrusion 161A and a first recess 161B. As shown in fig. 1, the first protrusion 161A is, for example, a portion of the first sub-pixel color layer 161 protruding to the left, and the first recess 161B is, for example, a portion of the first sub-pixel color layer 161 recessed to the left. The second subpixel color layer 162 disposed at the right side of the first subpixel color layer 161 has two second protrusions 162A. For example, the second protrusion 162A is, for example, a portion of the second sub-pixel color layer 162 protruding to the left and a portion of the second sub-pixel color layer 162 protruding to the right. In another aspect, second subpixel color layer 162 has no concave portion, and has a cross-shaped or embossed pattern that is convex to the left and right in a plan view. The third subpixel color layer 163 has a third protrusion 163A and a third recess 163B. For example, the third protrusion 163A is, for example, a portion of the third sub-pixel color layer 163 protruding to the right, and the third recess 163B is, for example, a portion of the third sub-pixel color layer 163 recessed to the right.
Under the above arrangement, as shown in fig. 1 and 2, the second protrusion 162A of the second sub-pixel color layer 162 disposed adjacent to the first sub-pixel color layer 161 may extend into the first recess 161B. In other words, at the adjacent boundary between the first sub-pixel color layer 161 and the second sub-pixel color layer 162, the second protrusion 162A is embedded in the first recess 161B. The second protrusion 162A of the second sub-pixel color layer 162 disposed adjacent to the third sub-pixel color layer 163 may extend into the third recess 163B. In other words, at the adjacent boundary between the second subpixel color layer 162 and the third subpixel color layer 163, the second protrusion 162A is embedded in the third recess 163B.
As shown in fig. 1, the fourth, fifth, and sixth sub-pixel color layers 164, 165, and 166 are disposed in the same column as the first, second, and third sub-pixel color layers 161, 162, and 163. For example, the arrangement order from left to right is: a first sub-pixel color layer 161, a second sub-pixel color layer 162, a third sub-pixel color layer 163, a fourth sub-pixel color layer 164, a fifth sub-pixel color layer 165, and a sixth sub-pixel color layer 166, but the invention is not limited thereto. The orthographic projections of the fourth sub-pixel color layer 164, the fifth sub-pixel color layer 165 and the sixth sub-pixel color layer 166 on the first substrate 100 are located between the orthographic projections of the first gate line SL1 and the second gate line SL2 on the first substrate 100. As shown in fig. 1, the fourth sub-pixel color layer 164 is located between the third sub-pixel color layer 163 and the fifth sub-pixel color layer 165, and the fifth sub-pixel color layer 165 is located between the fourth sub-pixel color layer 164 and the sixth sub-pixel color layer 166. In this embodiment, a first subpixel color layer 161 may also be disposed to the right of the sixth subpixel color layer 166, and a sixth subpixel color layer 166 may be disposed to the left of the first subpixel color layer 161. In other words, the sub-pixel color layers 160 of the present embodiment may be arranged in a circular manner from the first sub-pixel color layer 161 to the sixth sub-pixel color layer 166 in sequence from left to right, but the invention is not limited thereto.
In the present embodiment, the fourth sub-pixel 164 has two fourth recesses 164B. For example, the fourth concave portion 164B is, for example, a portion of the fourth sub-pixel color layer 164 depressed to the right and a portion of the fourth sub-pixel color layer 164 depressed to the left. In another aspect, the fourth sub-pixel color layer 164 has no convex portion, and has an I-shaped or I-shaped pattern depressed leftward and rightward in a plan view. The fifth sub-pixel color layer 165 is similar to the second sub-pixel color layer 162 and has two fifth protrusions 165A, so the description thereof is omitted. The sixth subpixel color layer 166 is similar to the fourth subpixel color layer 164 and has two sixth recesses 166B, so that the description thereof is omitted.
under the above-described arrangement, the third protrusion 163A of the third sub-pixel color layer 163 disposed adjacent to the fourth sub-pixel color layer 164 may extend into the fourth recess 164B. In other words, the third protrusion 163A is embedded in the fourth recess 164B at the adjacent boundary between the third sub-pixel color layer 163 and the fourth sub-pixel color layer 164. The fifth protrusion 165A of the fifth sub-pixel color layer 165 disposed adjacent to the fourth sub-pixel color layer 164 may extend into the fourth recess 164B. In other words, the fifth protrusion 165A is embedded in the fourth recess 164B at the adjacent boundary between the fourth sub-pixel color layer 164 and the fifth sub-pixel color layer 165. Fifth protrusions 165A of fifth sub-pixel color layer 165 disposed adjacent to sixth sub-pixel color layer 166 may extend into sixth recesses 166B. In other words, the fifth protrusion 165A is fitted into the sixth recess 166B at the adjacent boundary between the fifth subpixel color layer 165 and the sixth subpixel color layer 166. In addition, the first protrusion 161A is embedded in the sixth recess 166B at the adjacent boundary between the first sub-pixel color layer 161 and the sixth sub-pixel color layer 166, but the invention is not limited thereto.
As a result, as shown in fig. 1 and 2, the first protrusion 161A of the first sub-pixel color layer 161 may overlap the first switching element TFT1 in the direction N perpendicular to the first substrate 100. The second protrusion 162A of the second sub-pixel color layer 162 may overlap the second switching element TFT2 and the third switching element TFT3, but the invention is not limited thereto.
In the present embodiment, the first sub-pixel color layer 161, the second sub-pixel color layer 162, and the third sub-pixel color layer 163 are, for example, color photoresists having different colors, respectively. In other words, the first sub-pixel color layer 161 has a first color, the second sub-pixel color layer 162 has a second color and the third sub-pixel color layer 163 has a third color, and the first color, the second color and the third color are red light, green light, blue light, yellow light, orange light or white light, for example, but the invention is not limited thereto. In the present embodiment, the first color light, the second color light and the third color light are color lights with different colors, but the invention is not limited thereto. In some embodiments, two of the first, second, and third colors of light may be the same color of light, or all the same color of light.
In this embodiment, the first sub-pixel color layer 161 and the fourth sub-pixel color layer 164 can be color photoresists of the same color and have a first color light, such as blue light. The second sub-pixel color layer 162 and the fifth sub-pixel color layer 165 may be color photoresists of the same color to have a second color light, and the second color light is, for example, green light. The third sub-pixel color layer 163 and the sixth sub-pixel color layer 166 may be color photoresists of the same color and have a third color light, and the third color light is, for example, red light. However, the invention is not limited thereto.
referring to fig. 2, the second insulating layer 180 is disposed on the entire surface of the sub-pixel color layer 160. The second insulating layer 180 is made of the same material as the first insulating layer 140, and includes an inorganic material, an organic material, a combination of the above materials, or other suitable materials. Such inorganic materials are for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the foregoing materials. Examples of such organic materials are (but not limited to): a polymer material such as a polyimide resin, an epoxy resin or an acryl resin. In the embodiment, the second insulating layer 180 is a single layer, but the invention is not limited thereto. In other embodiments, the second insulating layer 180 may also be formed by stacking a plurality of film layers.
In the present embodiment, a plurality of pixel electrodes PE are disposed on the second insulating layer 180. The pixel electrodes PE may be electrically connected to the pixel arrays PA, respectively. For example, one of the pixel electrodes PE may be electrically connected to the first switching element TFT 1. Another of the pixel electrodes PE may be electrically connected to the second switching element TFT 2. In other words, the pixel electrode PE may be disposed corresponding to the first switching element TFT1 and the second switching element TFT2, respectively, but the invention is not limited thereto. In the embodiment, the pixel electrode PE may be made of a transparent conductive material, such as a metal oxide, for example, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), or Indium Germanium Zinc Oxide (IGZO), but the invention is not limited thereto.
in the present embodiment, the light-shielding layer BM is disposed on the second substrate 200. For example, the light-shielding layer BM includes a first light-shielding pattern BM1, a second light-shielding pattern BM2 and a third light-shielding pattern BM3 respectively disposed on the second substrate 200, but the invention is not limited thereto. As shown in fig. 1, the light-shielding layer BM further includes a fourth light-shielding pattern BM4, a fifth light-shielding pattern BM5 and a sixth light-shielding pattern BM6 disposed on the second substrate 200.
In this embodiment, in the direction N perpendicular to the first substrate 100, the first light-shielding pattern BM1 corresponds to overlap the first switching element TFT1, the second light-shielding pattern BM2 corresponds to overlap the second switching element TFT2, and the third light-shielding pattern BM3 corresponds to overlap the third switching element TFT 3. From another perspective, the first light shielding pattern BM1 may overlap portions of the first and sixth sub-pixel color layers 161 and 166. In addition, an orthogonal projection of the first protrusion 161A of the first sub-pixel color layer 161 on the first substrate 100 may be located within an orthogonal projection of the first light shielding pattern BM1 on the first substrate 100. The second light shielding pattern BM2 may overlap a portion of the first sub-pixel color layer 161 and a portion of the second sub-pixel color layer 162. An orthogonal projection of one second protrusion 162A of the second sub-pixel color layer 162 on the first substrate 100 may be located within an orthogonal projection of the second light shielding pattern BM2 on the first substrate 100. In addition, the third light shielding pattern BM3 may also overlap a portion of the second sub-pixel color layer 162 and a portion of the third sub-pixel color layer 163. An orthogonal projection of the other second protrusion 162A of the second subpixel color layer 162 on the first substrate 100 may be located within an orthogonal projection of the third light blocking pattern BM3 on the first substrate 100.
As shown in fig. 1, the fourth light shielding pattern BM4 may overlap portions of the third sub-pixel color layer 163 and portions of the fourth sub-pixel color layer 164. An orthogonal projection of the third protrusion 163A of the third sub-pixel color layer 163 on the first substrate 100 may be located within an orthogonal projection of the fourth light shielding pattern BM4 on the first substrate 100. The fifth light shielding pattern BM5 may overlap portions of the fourth sub-pixel color layer 164 and portions of the fifth sub-pixel color layer 165. An orthogonal projection of one fifth protrusion 165A of the fifth sub-pixel color layer 165 on the first substrate 100 may be positioned within an orthogonal projection of the fifth light shielding pattern BM5 on the first substrate 100. The sixth light shielding pattern BM6 may overlap a portion of the fifth sub-pixel color layer 165 and a portion of the sixth sub-pixel color layer 166. An orthogonal projection of another fifth protrusion 165A of the fifth sub-pixel color layer 165 on the first substrate 100 may be located within an orthogonal projection of the sixth light shielding pattern BM6 on the first substrate 100. However, the invention is not limited thereto.
As shown in fig. 1 and 2, the gate electrode of the pixel array PA and the plurality of data lines DL may be overlapped by the orthographic projection of the light-shielding layer BM on the first substrate 100. For example, the first light shielding pattern BM1 may overlap the first gate electrode G1 of the first switching element TFT1 and the first data line DL 1. The second light shielding pattern BM2 may overlap the second gate electrode G2 of the second switching element TFT2 and the second data line DL 2. In other words, the light-shielding layer BM may be disposed corresponding to the data line DL and the switching elements (for example, the first switching element TFT1, the second switching element TFT2, and the third switching element TFT3), but the invention is not limited thereto.
in this embodiment, the common electrode layer 220 may be entirely disposed on the second substrate 200 and cover the light-shielding layer BM. In other words, the light-shielding layer BM may be located between the common electrode layer 220 and the second substrate 200. In addition, as shown in fig. 2, the common electrode layer 220 is located between the first substrate 100 and the second substrate 200. The common electrode layer 220 may be made of a transparent conductive material, such as a metal oxide, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), or Indium Germanium Zinc Oxide (IGZO), but the invention is not limited thereto.
In some embodiments, the display panel 10 may further include an alignment layer, an anti-reflection layer or other optical film layer disposed on the second insulating layer 180 and/or the common electrode layer 220, but not limited thereto.
In the present embodiment, the display medium layer LC is disposed between the first substrate 100 and the second substrate 200. The display medium layer LC may comprise liquid crystal molecules, an electrophoretic display medium, or other applicable media. The display medium layer LC in the following embodiments of the present invention is exemplified by including liquid crystal molecules, but the present invention is not limited thereto. Furthermore, the liquid crystal molecules in the following embodiments of the present invention are preferably liquid crystal molecules that can be rotated or switched by a horizontal electric field or liquid crystal molecules that can be rotated or switched by a vertical electric field, but the present invention is not limited thereto.
In the embodiment, the first supporting structure PS1 and the plurality of second supporting structures PS2 are disposed between the first substrate 100 and the second substrate 200. The first support structure PS1 overlaps the first sub-pixel color layer 161 in the direction N perpendicular to the first substrate 100. These second support structures PS2 overlap the second sub-pixel color layer 162 and the third sub-pixel color layer 163, respectively, in the direction N perpendicular to the first substrate 100. As shown in fig. 1, these second support structures PS2 may also overlap the fifth sub-pixel color layer 165, but the invention is not limited thereto. In some embodiments, second support structure PS2 may also overlap fourth subpixel color layer 164 and/or sixth subpixel color layer 166. In other embodiments, the second support structure PS2 may also overlap the first sub-pixel color layer 161, and the first support structure PS1 may also overlap any one of the first sub-pixel color layer 161 to the sixth sub-pixel color layer 166, which is not limited to that shown in fig. 1.
As shown in fig. 2, the first support structure PS1 and the second support structure PS2 may be disposed on the second substrate 200. The bottom surface PS1B of the first supporting structure PS1 is disposed on the first light shielding pattern BM1, and the top surface PS1A of the first supporting structure PS1 abuts against the surface 181 of the second insulating layer 180 on the first sub-pixel color layer 161. One of the second support structures PS2 is disposed on the second light shielding pattern BM2, and the other of the second support structures PS2 is disposed on the third light shielding pattern BM 3. For example, the second supporting structure PS2 may be disposed on any one of the light-shielding layers BM except the first light-shielding pattern BM1, but the invention is not limited thereto. As shown in fig. 2, the bottom surface PS2B of the second support structure PS2 is disposed on the second light shielding pattern BM2, but the top surface PS2A of the second support structure PS2 does not abut against the second sub-pixel color layer 162. From another perspective, there is a spacing K1 between second support structure PS2 and second insulating layer 180 on second subpixel color layer 162. The spacing K1 can be defined as the step distance between the top surface PS2A and the surface 181 of the second insulating layer 180. In other words, in the cross-sectional view, the top surface PS1A is located at a different level than the top surface PS 2A. Specifically, the height H3 of the first support structure PS1 is greater than the height H4 of the second support structure PS 2. In the present embodiment, the material of the first support structure PS1 and the second support structure PS2 includes a photoresist material. In addition, in the embodiment, the first support structures PS1 and the second support structures PS2 may be fabricated by a half-tone mask (HTM) process or a gray-tone mask (gray-tone mask) process, but the invention is not limited thereto.
With the above arrangement, the first support structure PS1 can abut against the first light shielding pattern BM1 without any space between the first support structure PS1 and the first light shielding pattern BM 1. Accordingly, the first support structure PS1 may be a main photospacer (main photospacer) of the display panel 10. There is a spacing K1 between the second support structure PS2 and the sub-pixel color layer 160 (e.g., the second sub-pixel color layer 162 or the third sub-pixel color layer 163), so the second support structure PS2 can be an auxiliary support structure (sub-pixel) of the display panel 10. However, the invention is not limited thereto, and in some embodiments, the heights of the first support structure PS1 and the second support structure PS2 may be the same, and the spacing between the second support structure PS2 and the sub-pixel color layer may be formed by different thicknesses of different sub-pixel color layers. In other words, the sub-pixel color layer corresponding to the first support structure PS1 may be thicker than the sub-pixel color layer corresponding to the second support structure PS2, such that the first support structure PS1 abuts against the sub-pixel color layer. It should be understood by those skilled in the art that any design that allows a space between the second support structure PS2 and the sub-pixel color layer does not depart from the scope and spirit of the present invention.
In some embodiments, an alignment layer, an anti-reflection layer, a polarizer, or an optical film of a light-gathering sheet may be further disposed on the first substrate 100 and the second substrate 200, but not limited thereto. For example, the alignment layer may be disposed on the surface 181 between the first substrate 100 and the second substrate 200 or on the common electrode layer 220 according to the user's requirement. That is, a plurality of layers having optical or structural functions may be disposed between the first support structure PS1 and/or the second support structure PS2 and the second insulating layer 180, which is not limited to the embodiment shown in fig. 2.
It is noted that, in the direction N perpendicular to the first substrate 100, an orthographic projection of the first supporting structure PS1 on the first substrate 100 overlaps an orthographic projection of the first protrusion 161A on the first substrate 100. Specifically, the orthographic projection of the first support structure PS1 on the first substrate 100 may overlap portions of the first gate G1, the first data line DL1 and the first protrusion 161A. In addition, the orthographic projection of the first light shielding pattern BM1 on the first substrate 100 may overlap the orthographic projection of the first protrusion 161A and the first support structure PS1 on the substrate 100. As such, the first supporting structure PS1 can be disposed on the first light shielding pattern BM1 shielding the first switching element TFT1 and the first data line DL 1. Therefore, the light-shielding layer BM required for providing the first support structure PS1 and the light-shielding layer BM shielding the pixel array PA can be integrated into the first light-shielding pattern BM 1. Thus, the area occupied by the whole light-shielding layer BM can be reduced, and the aperture ratio and the display quality of the pixels of the display panel 10 can be improved.
In addition, in the direction N perpendicular to the first substrate 100, an orthographic projection of the second supporting structure PS2 on the first substrate 100 overlaps an orthographic projection of the second protrusion 162A on the first substrate 100. Specifically, the orthographic projection of the second support structure PS2 on the first substrate 100 may overlap portions of the second gate G2, the second data line DL2 and the second protrusion 162A. In addition, the orthographic projection of the second light shielding pattern BM2 on the first substrate 100 may further overlap the orthographic projection of the second protrusion 162A and one of the second supporting structures PS2 on the first substrate 100. As such, the second supporting structure PS2 can be disposed on the second light shielding pattern BM2 shielding the second switching element TFT2 and the second data line DL 2. Therefore, the light-shielding layer BM required for providing the second support structure PS2 and the light-shielding layer BM shielding the pixel array PA can be integrated into the second light-shielding pattern BM 2. Thus, the area occupied by the whole light-shielding layer BM can be reduced, and the aperture ratio and the display quality of the pixels of the display panel 10 can be improved.
As shown in fig. 2, the second support structure PS2 may further include a third gate G3, a third data line DL3 and a second protrusion 162A overlapping with the orthographic projection of the first substrate 100. In addition, the orthographic projection of the third light shielding pattern BM3 on the first substrate 100 may further overlap the orthographic projection of the second protrusion 162A and one of the second supporting structures PS2 on the first substrate 100. In this way, the second supporting structure PS2 can also be disposed on the third light shielding pattern BM3 shielding the third switching element TFT3 and the third data line DL 3. Therefore, the area occupied by the whole light-shielding layer BM can be reduced, and the aperture ratio and the display quality of the pixels of the display panel 10 can be improved.
However, the invention is not limited to what is shown in FIG. 2. In fact, as shown in fig. 1, the second support structures PS2 may also overlap the fourth light shielding pattern BM4, the fifth light shielding pattern BM5 and/or the sixth light shielding pattern BM6, respectively. Specifically, as shown in fig. 1, the second supporting structures PS2 may also overlap the third protrusion 163A and the fifth protrusion 165A in the direction N perpendicular to the first substrate 100, but the invention is not limited thereto. Therefore, the light-shielding layer BM required for providing the second support structure PS2 and the light-shielding layer BM shielding the pixel array PA can be further integrated into the fourth light-shielding pattern BM4, the fifth light-shielding pattern BM5 and/or the sixth light-shielding pattern BM6, so as to reduce the area occupied by the whole light-shielding layer BM, and further improve the aperture ratio and the display quality of the pixels of the display panel 10.
Further, as shown in fig. 2, the first sub-pixel color layer 161 has a first thickness H1, and the second sub-pixel color layer 162 has a second thickness H2, and H1 is greater than H2. In other words, the first subpixel color layer 161 is thicker than the second subpixel color layer 162. In some embodiments, the thickness of the third subpixel color layer 163 is the same as the second thickness H2 of the second subpixel color layer 162 and is less than the first thickness H1 of the first subpixel color layer 161, but the invention is not limited thereto.
In the present embodiment, the first protrusion 161A overlaps the first data line DL1, and the first supporting structure PS1 overlaps and abuts against the first protrusion 161A. In this way, the first supporting structure PS1 is ensured to abut against the first sub-pixel color layer 161 with a relatively thick thickness. The second support structure PS2 overlaps the second data line DL2 and/or the third data line DL3 and does not abut against any of the two second protrusions 162A. Accordingly, a space K1 between the second support structure PS2 and the second sub-pixel color layer 162 can be secured. In other words, the display panel 10 may pass through different thicknesses of the sub-pixel color layer 160 to correspond to the first support structure PS1 or the second support structure PS2, respectively. In this way, the first supporting structure PS1 and the second supporting structure PS2 can respectively provide the required support and elasticity for the display panel 10, thereby improving the reliability and quality of the display panel 10.
In short, the light-shielding layer BM of the display panel 10 of the present embodiment is disposed corresponding to the pixel array PA, the data line DL, and the first supporting structure PS1 or the second supporting structure PS 2. Therefore, the display panel 10 can integrate the light-shielding layer BM required for providing the first support structure PS1 and/or the second support structure PS2 and the light-shielding layer BM shielding the pixel array PA into the first light-shielding pattern BM1 and/or the second light-shielding pattern BM 2. Thus, the area occupied by the whole light-shielding layer BM can be reduced, and the aperture ratio and the display quality of the pixels of the display panel 10 can be improved.
In addition, the first thickness H1 of the first sub-pixel color layer 161 is greater than the second thickness H2 of the second sub-pixel color layer 162. As such, the first support structures PS1 on the first light shielding pattern BM1 may overlap and abut against the first protrusion 161A. The second support structures PS2 on the second light shielding pattern BM2 may overlap but not abut against the second protrusion 162A. In addition, the height H3 of the first support structure PS1 may also be greater than the height H4 of the second support structure PS 2. Therefore, the first support structure PS1 and the second support structure PS2 can be used as a main support structure and an auxiliary support structure, respectively. Under the above configuration, the display panel 10 can control the thickness of the sub-pixel color layer 160 and the heights of the first support structure PS1 and the second support structure PS2, so that the first support structure PS1 and the second support structure PS2 can respectively provide the required support and elasticity for the display panel 10, thereby improving the reliability and quality of the display panel 10.
In some embodiments, the first support structure PS1 may also be disposed corresponding to the color of the subpixel color layer 160. For example, the orthographic projection of the first supporting structure PS1 on the first substrate 100 may overlap the orthographic projection of the first protrusion 161A of the first sub-pixel color layer 161 of blue color on the first substrate 100. The orthographic projection of the second support structure PS2 on the first substrate 100 may overlap the orthographic projection of the second protrusion 162A of the second sub-pixel color layer 162 of green or red on the first substrate 100, but not limited thereto. This is because the film thickness of the blue sub-pixel color layer 160 can be made thicker than the film thickness of the green or red sub-pixel color layer 160. Accordingly, the first support structure PS1 may abut against the blue first sub-pixel color layer 161 having a relatively thick film thickness, and the second support structure PS2 may abut against the green or red second sub-pixel color layer 162 having a relatively thin film thickness. In this way, the display panel 10 can be disposed by correspondingly overlapping the sub-pixel color layers 160 with different colors and film thicknesses on the first support structure PS1 and the second support structure PS2, so that the first support structure PS1 and the second support structure PS2 can respectively provide the required support and elasticity for the display panel 10, thereby improving the reliability and quality of the display panel 10.
The following embodiments follow the reference numerals and part of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and for the part of the description where the same technical contents are omitted, reference may be made to the foregoing embodiments, and the description in the following embodiments is not repeated.
Fig. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the invention. The display panel 10A shown in the present embodiment is similar to the display panel 10 shown in fig. 2, and the main difference is that: the material of the second insulating layer 180A is, for example, a photoresist material. In this embodiment, portions with different thicknesses may be respectively fabricated on the second insulating layer 180A through a half-tone mask (HTM) process or a gray-tone mask (gray-tone mask) process to further ensure a height difference between the surface 181A and the surface 181B, but the invention is not limited thereto. For example, the thickness H5 of the second insulating layer 180A at the position overlapping the first data line DL1 is greater than the thickness H6 of the second insulating layer 180A at the position overlapping the second data line DL 2. From another perspective, in the direction N perpendicular to the first substrate 100, the surface 181A of the portion of the second insulating layer 180A having the thickness H5 is located at a higher level than the surface 181B of the portion having the thickness H6. Under the above arrangement, the top surface PS1A of the first supporting structure PS1 overlapping the surface 181A can abut against the surface 181A. The top surface PS2A of the second support structure PS2 overlapping the surface 181B does not abut against the surface 181B, and a gap K2 exists between the top surface PS2A and the surface 181B. In other words, a step with a spacing K2 can be defined between the top PS2A and the surface 181B. Therefore, the display panel 10A can control the different thicknesses of the sub-pixel color layers 160, the heights of the first support structures PS1 and the second support structures PS2, and the surfaces 181A and 181B of the second insulating layer 180A at different heights, so that the first support structures PS1 and the second support structures PS2 can be used as main support structures and auxiliary support structures, respectively, to provide the support and elasticity required by the display panel 10A, thereby improving the reliability and quality of the display panel 10A.
fig. 4A is a schematic cross-sectional view illustrating a display panel according to another embodiment of the invention. The display panel 10B shown in the present embodiment is similar to the display panel 10 shown in fig. 2, and the main difference is that: the first and second support structures PS3 and PS4 are disposed on the second insulating layer 180 on the first substrate 100. In other words, the display panel 10B of the present embodiment integrates the supporting structure on the pixel Array PA (POA).
in the present embodiment, the bottom surface PS3B of the first supporting structure PS3 is disposed on the second insulating layer 180 on the first sub-pixel color layer 161, and the top surface PS3A of the first supporting structure PS3 abuts against the surface 221 of the common electrode layer 220 on the first light shielding pattern BM 1. As shown in fig. 4A, a bottom surface PS4B of the second support structure PS4 is disposed on the second sub-pixel color layer 162. In this way, the first support structure PS3 and the second support structure PS4 can use the first light-shielding pattern BM1 and the second light-shielding pattern BM2 as the film layers required for disposing the support structures, respectively. In addition, one of the second support structures PS4 overlaps the second data line DL2, and the other of the second support structures PS4 overlaps the third data line DL 3. In the present embodiment, the first support structure PS3 is disposed on the first subpixel color layer 161 having a relatively thick thickness. The second support structure PS4 is disposed on the second sub-pixel color layer 162 with a relatively thin thickness, so that the top surface PS4A of the second support structure PS4 does not abut against the surface 221 of the common electrode layer 220 on the second light-shielding pattern BM2, and a gap K3 exists between the top surface PS4A and the surface 221. In other words, a step difference having a spacing K3 may be defined between the top surface PS4A and the surface 221. Therefore, the display panel 10B can control the different thicknesses of the sub-pixel color layers 160 and make the first support structures PS3 and the second support structures PS4 have different heights, so that the first support structures PS3 and the second support structures PS4 can be used as main support structures and auxiliary support structures, respectively, to provide the support and elasticity required by the display panel 10B, thereby improving the reliability and quality of the display panel 10B.
Fig. 4B is a partially enlarged schematic cross-sectional view of a first light shielding pattern according to another embodiment of the invention. The first light shielding pattern BM 1' shown in this embodiment is similar to the first light shielding pattern BM1 shown in fig. 4A, and the main difference is that: the first light shielding pattern BM 1' includes a flat portion 242 and a convex portion 244. In the present embodiment, the flat portion 242 and the protruding portion 244 can be formed by the same film layer. For example, the accommodating space 243 may be formed on the first light shielding pattern BM 1' by photolithography and the accommodating space 243 is surrounded by the protrusion 244. In the present embodiment, there is a height difference X between the surface 241 of the flat portion 242 and the lower surface 245 of the convex portion 244. The height difference X may define a height of the accommodating space 243. As shown in fig. 4B, the first support structure PS3 overlapped on the first sub-pixel color layer 161 overlaps the accommodating space 243, and the top surface PS3A of the first support structure PS3 abuts against the common electrode layer 220 on the surface 241 of the flat portion 242. From another perspective, the first support structure PS3 can be located in the accommodating space 243 and surrounded by the protrusion 244. Under the above arrangement, the first supporting structure PS3 can be limited by the accommodating space 243 and the sidewall 223 of the common electrode layer 220 formed on the side of the protrusion 244. As such, when the second substrate 200 and the first substrate 100 (shown in fig. 4A) have a tolerance of displacement when being aligned, the first supporting structure PS3 can be limited by the sidewall 223 and maintain overlapping the accommodating space 243. Therefore, the first light shielding pattern BM 1' can further reduce the probability of the first supporting structure PS3 displacement, thereby improving the reliability of the display panel.
Fig. 5 is a schematic cross-sectional view of a display panel according to another embodiment of the invention. The display panel 10C shown in the present embodiment is similar to the display panel 10B shown in fig. 4A, and the main difference is that: the material of the second insulating layer 180A is, for example, a photoresist material. In this embodiment, portions with different thicknesses may be respectively fabricated on the second insulating layer 180A through a half-tone mask (HTM) process or a gray-tone mask (gray-tone mask) process to further ensure a height difference between the surface 181A and the surface 181B, but the invention is not limited thereto. For example, the thickness H5 of the second insulating layer 180A at the position overlapping the first data line DL1 is greater than the thickness H6 of the second insulating layer 180A at the position overlapping the second data line DL 2. From another perspective, in the direction N perpendicular to the first substrate 100, the surface 181A of the portion of the second insulating layer 180A having the thickness H5 is located at a higher level than the surface 181B of the portion having the thickness H6. Under the above arrangement, the top surface PS3A of the first supporting structure PS3 disposed on the surface 181A can abut against the surface 221 of the common electrode layer 220 on the first light shielding pattern BM 1. The top PS4A of the second support structure PS4 disposed on the surface 181B does not abut against the surface 221, and a gap K4 exists between the top PS4A and the surface 221. In other words, a step difference having a spacing K4 may be defined between the top surface PS4A and the surface 221. Therefore, the display panel 10C can control the different thicknesses of the sub-pixel color layers 160, the heights of the first support structures PS3 and the second support structures PS4, and the surfaces 181A and 181B of the second insulating layer 180A, which are located at different heights, so that the first support structures PS3 and the second support structures PS4 can be used as main support structures and auxiliary support structures, respectively, to provide the support and elasticity required by the display panel 10C, thereby improving the reliability and quality of the display panel 10A.
fig. 6 is a schematic cross-sectional view of a display panel according to still another embodiment of the present invention. The display panel 10D shown in the present embodiment is similar to the display panel 10 shown in fig. 2, and the main difference is that: the sub-pixel color layer 260 is disposed on the second substrate 200. The sub-pixel color layer 260 includes, for example, a first sub-pixel color layer 261, a second sub-pixel color layer 262, a third sub-pixel color layer 263, and a sixth sub-pixel color layer 266, but the invention is not limited thereto. In some embodiments, subpixel color layer 260 may further comprise a fourth subpixel color layer and a fifth subpixel color layer. As shown in fig. 6, the first sub-pixel color layer 261 overlaps a portion of the first light blocking pattern BM1, the second sub-pixel color layer 262 overlaps a portion of the second light blocking pattern BM2, and the third sub-pixel color layer 263 overlaps a portion of the third light blocking pattern BM 3. Second subpixel color layer 262 is positioned between first subpixel color layer 261 and third subpixel color layer 263.
In the present embodiment, the second insulating layer 180 covers the entire surface of the first substrate 100 and overlaps the pixel array PA and the plurality of data lines DL. As shown in fig. 6, the first data line DL1 overlaps the first light blocking pattern BM1 and the first protrusion 261A of the first sub-pixel color layer 261 in the direction N perpendicular to the first substrate 100. The second data line DL2 and the third data line DL3 overlap the second light-shielding pattern BM2 and the third light-shielding pattern BM3, respectively. In addition, the two second protrusions 262A of the second sub-pixel color layer 262 overlapping the second light-shielding pattern BM2 and the third light-shielding pattern BM3 overlap the second data line DL2 and the third data line DL3, respectively.
In the present embodiment, the first support structure PS1 is disposed overlapping the first sub-pixel color layer 261. The bottom surface PS1B of the first supporting structure PS1 is disposed on the first sub-pixel color layer 261, and the top surface PS1A of the first supporting structure PS1 abuts against the surface 181 of the second insulating layer 180 on the first data line DL 1. The bottom surface PS2B of the second support structure PS2 is disposed on the second sub-pixel color layer 262, and a space K5 exists between the top surface PS2A of the second support structure PS2 and the surface 181 of the second insulating layer 180 on the second data line DL 2. In other words, a step with a spacing K5 may be defined between the top PS2A and the surface 181. Therefore, the display panel 10D can control the different thicknesses of the sub-pixel color layers 260 and make the first support structures PS1 and the second support structures PS2 have different heights, so that the first support structures PS1 and the second support structures PS2 can be used as main support structures and auxiliary support structures, respectively, to provide the support and elasticity required by the display panel 10D, thereby improving the reliability and quality of the display panel 10B.
Fig. 7 is a schematic cross-sectional view illustrating a display panel according to still another embodiment of the invention. The display panel 10E shown in the present embodiment is similar to the display panel 10D shown in fig. 6, and the main difference is that: the second insulating layer 180A covers the entire surface of the first substrate 100 and overlaps the pixel array PA and the plurality of data lines DL. The material of the second insulating layer 180A is, for example, a photoresist material. In this embodiment, portions with different thicknesses may be respectively fabricated on the second insulating layer 180A through a half-tone mask (HTM) process or a gray-tone mask (gray-tone mask) process to further ensure a height difference between the surface 181A and the surface 181B, but the invention is not limited thereto. For example, the thickness H5 of the second insulating layer 180A at the position overlapping the first data line DL1 is greater than the thickness H6 of the second insulating layer 180A at the position overlapping the second data line DL 2. From another perspective, in the direction N perpendicular to the first substrate 100, the surface 181A of the portion of the second insulating layer 180A having the thickness H5 is located at a higher level than the surface 181B of the portion having the thickness H6. Under the above arrangement, the top surface PS1A of the first supporting structure PS1 disposed on the first sub-pixel color layer 261 and overlapping the surface 181A may abut against the surface 181A. The top surface PS2A of the second support structure PS2 disposed on the second sub-pixel color layer 262 and overlapping the surface 181B does not abut against the surface 181B, and a gap K6 exists between the top surface PS2A and the surface 181B. In other words, a step with a spacing K6 can be defined between the top PS2A and the surface 181B. Therefore, the display panel 10E can control the different thicknesses of the sub-pixel color layers 260, the heights of the first support structures PS1 and the second support structures PS2, and the surfaces 181A and 181B of the second insulating layer 180A at different heights, so that the first support structures PS1 and the second support structures PS2 are respectively used as main support structures and auxiliary support structures to provide the support and elasticity required by the display panel 10E, thereby improving the reliability and quality of the display panel 10A.
Fig. 8 is a schematic partial top view illustrating a display panel according to another embodiment of the invention. Referring to fig. 1, fig. 2 and fig. 8, in the present embodiment, a difference between the display panel 10F and the display panel 10 of fig. 1 is: the first data line DL1 and the second data line DL2 may be adjacently disposed between the adjacent first switching element TFT1 and the second switching element TFT 2. The first switching element TFT1 includes a first gate G1, a first semiconductor layer CH1, a first source S1, and a first drain D1 electrically connected to the storage capacitor C1. The second switching element TFT2 includes a second gate G2, a second semiconductor layer CH2, a second source S2, and a second drain D2 electrically connected to the storage capacitor C2. The first switching element TFT1 and the second switching element TFT2 are electrically connected to the same first gate line SL1, respectively. As shown in fig. 8, the adjacent boundary of the first and second sub-pixel color layers 161 and 162 may be partially located between the first and second data lines DL1 and DL 2. The first protrusion 161A may be inserted into the second recess 162B rightward, but the invention is not limited thereto.
As shown in fig. 8, the first data line DL1 overlaps the first sub-pixel color layer 161 and is electrically connected to the first source S1 of the first switching element TFT 1. The second data line DL2 overlaps the second sub-pixel color layer 162 and the first protrusion 161A of the first sub-pixel color layer 161 and is electrically connected to the second source S2 of the second switching element TFT 2.
In this embodiment, the display panel 10F further includes a common electrode line COM, and the common electrode line COM and the first gate line SL1 extend in the same direction. As shown in fig. 8, the first data line DL1 crosses the second data line DL2 and the common electrode line COM parallel to the first gate line SL 1. Under the above arrangement, the overlapping area of the common electrode line COM with the first data line DL1 and the second data line DL2 can be reduced, and the cross capacitance (cross capacitance) between the common electrode line COM and the first data line DL1 and the second data line DL2 can be further reduced. In this way, the load of the signal lines can be reduced, and the display quality of the display panel 10F can be improved.
in the embodiment, the orthographic projection of the first support structure PS1 on the first substrate 100 is located between the orthographic projection of the first data line DL1 and the orthographic projection of the second data line DL2 on the first substrate 100. Further, the first support structure PS1 also overlaps the first protrusion 161A and overlaps the portion of the common electrode line COM. Thus, the first supporting structures PS1 can be disposed at the intersection of the data lines and the common electrode lines COM, thereby improving the aperture ratio and the display quality of the pixels of the display panel 10F.
Fig. 9 is a partially enlarged schematic top view of a first opening of a display panel according to another embodiment of the present invention, and fig. 9 schematically illustrates only some of the components for convenience of illustration and observation. Fig. 10 is a schematic cross-sectional view of the display panel of fig. 9 along the section line B-B'. The display panel 10G shown in the present embodiment is similar to the display panel 10G shown in fig. 8, and the main difference is that: the first data line DL1 has an opening (e.g., a first opening O1). Specifically, the first data line DL1 may be divided into a first branch DL1A and a second branch DL1B by a first opening O1, which are respectively located at the left and right sides of the first opening O1. The first opening O1 overlaps the first gate line SL 1. The first supporting structure PS1 overlaps the first opening O1 in the orthographic projection of the first substrate 100. As shown in fig. 10, the second insulating layer 180 is disposed on the first data line DL1, and covers the first opening O1 to form a sidewall 183 at an edge of the first opening O1. The orthographic projection of the first supporting structure PS1 on the first substrate 100 overlaps the first opening O1, and the top surface PS1A of the first supporting structure PS1 abuts against the surface 181 inside the first opening O1.
With the above arrangement, the first supporting structure PS1 can be limited by the first opening O1 and the sidewall 183 of the second insulating layer 180 formed at the edge of the first opening O1. In this way, when the second substrate 200 and the first substrate 100 are aligned to generate a displacement tolerance, the first supporting structure PS1 can be limited by the sidewall 183 to maintain overlapping the first opening O1A. Therefore, the first opening O1 can further reduce the probability of displacement of the first supporting structure PS1, thereby improving the reliability of the display panel 10G.
fig. 11 is a partially enlarged schematic top view of a second opening of a display panel according to still another embodiment of the present invention, and fig. 11 schematically illustrates only some of the components for convenience of illustration and observation. Fig. 12 is a schematic cross-sectional view of the display panel of fig. 11 along the section line C-C'. The display panel 10H of the present embodiment is similar to the display panel 10G shown in fig. 9 and 10, and the main difference is that: the first gate line SL1 has an opening (e.g., the second opening O2). The first data line DL1 overlaps the second opening O2. In the present embodiment, the first data line DL1 has a first width W1A and the second opening O2 has a second width W2 in a direction perpendicular to the first data line DL 1. The first width W1A is greater than the second width W2. In other words, the first data line DL1 may completely overlap the second opening O2.
In the embodiment, the first supporting structure PS1 overlaps the second opening O2 in the orthographic projection of the first substrate 100. As shown in fig. 12, the gate insulating layer 120, the first data line DL1 and the second insulating layer 180 are disposed on the first gate line SL1 and cover the second opening O2. The second insulating layer 180 forms a sidewall 183 at an edge of the second opening O2. The orthographic projection of the first supporting structure PS1 on the first substrate 100 overlaps the second opening O2, and the top surface PS1A of the first supporting structure PS1 abuts against the surface 181 inside the second opening O2.
Under the above arrangement, the first supporting structure PS1 can be limited by the second opening O2 and the sidewall 183 of the second insulating layer 180 formed at the edge of the second opening O2. As such, when the second substrate 200 and the first substrate 100 are aligned to generate a displacement tolerance, the first supporting structure PS1 can be limited by the sidewall 183 to maintain overlapping the second opening O2. Therefore, the second opening O2 can further reduce the probability of displacement of the first supporting structure PS1, thereby improving the reliability of the display panel 10H.
Fig. 13 is a partially enlarged top view schematically illustrating a second opening according to another embodiment of the present invention. The first data line DL 1' shown in this embodiment is similar to the first data line DL1 shown in fig. 11, and the main difference is that: in a direction extending perpendicular to the first data line DL1 ', the first data line DL 1' has a first width W1, and the second opening O2 has a second width W2. The second width W2 is greater than the first width W1. In other words, the first data line DL 1' only partially overlaps the second opening O2. As shown in fig. 13, the first supporting structure PS1 overlaps the second opening O2 in the orthographic projection of the first substrate 100. Thus, the second opening O2 can achieve the similar technical effects as the above embodiments.
Fig. 14A is a schematic circuit diagram of a pixel array of a display panel according to another embodiment of the invention, and fig. 14A schematically illustrates only some of the components for convenience of illustration and observation. In the present embodiment, the display panel 10I includes a plurality of data lines DLm, DLm +1 extending in the first direction N1 arranged along the second direction N2, a plurality of gate lines SLn, SLn +1, SLn +2, SLn +3, SLn +4 extending in the second direction N2 arranged along the first direction N1, and a plurality of pixel electrodes PE arranged in an array. The data lines and the gate lines are staggered (e.g., data line DLm is staggered with respect to gate lines SLn, SLn +1, SLn +2, SLn +3, SLn + 4). In the embodiment, the first direction N1 is perpendicular to the second direction N2, but not limited thereto. The pixel electrodes PE may be electrically connected to a plurality of switching elements TFT in the pixel array, respectively. As shown in fig. 14A, the plurality of pixel electrodes PE may be arranged in a plurality of columns along the second direction N2. For example, the pixel electrodes PE arranged in a row may be located between the gate line SLn (e.g., a first gate line) and the gate line SLn +1 (e.g., a second gate line). Two of the adjacent pixel electrodes PE in the same row may be electrically connected to the same data line DLm (e.g., the first data line) and to the gate line SLn and the gate line SLn +1, respectively. For example, two pixel electrodes PE in the same row and located at two sides of the data line DLm may be electrically connected to the data line DLm. In other words, the pixel electrode PE and the signal line of the display panel 10I are disposed in a Half Source Driving (HSD) structure, for example, so that the number of data lines is reduced by half. In other words, the number of data lines can be half of the number of gate lines, so that the power consumption of the source driver can be reduced, and the performance of the display panel 10I can be improved.
Fig. 14B is a schematic circuit diagram of a pixel array of a display panel according to another embodiment of the invention, and fig. 14B schematically illustrates only some of the components for convenience of illustration and observation. The display panel 10I' shown in the present embodiment is similar to the display panel 10I shown in fig. 14A, and the main difference is that: the two pixel electrodes PE in the same row and on the same side of the data line DLm +1 can be electrically connected to the same data line DLm + 1. In detail, the display panel 10I' includes a plurality of data lines DLm, DLm +1, DLm +2 extending in the first direction N1 arranged along the second direction N2, a plurality of gate lines SLn, SLn +1, SLn +2, SLn +3, SLn +4 extending in the second direction N2 arranged along the first direction N1, and a plurality of pixel electrodes PE arranged in an array. As shown in fig. 14B, the plurality of pixel electrodes PE may be arranged in a plurality of columns along the second direction N2. For example, the pixel electrodes PE arranged in a row may be located between the gate line SLn (e.g., a first gate line) and the gate line SLn +1 (e.g., a second gate line). In addition, two of the adjacent pixel electrodes PE in the same column may be located between the data line DLm and the data line DLm +1 or between the data line DLm +1 and the data line DLm + 2. The two pixel electrodes PE on the left side of the data line DLm +1 can be electrically connected to the data line DLm +1 (e.g., the first data line) and the gate line SLn +1, respectively. The two pixel electrodes PE on the right side of the data line DLm +1 can be electrically connected to the data line DLm +2 (e.g., the second data line) and the gate line SLn +1, respectively. In other words, the pixel electrode PE and the signal line of the display panel 10I' are disposed in a Half Source Driving (HSD) structure, for example, so that the number of data lines is reduced by half. In other words, the number of the data lines may be half of the number of the gate lines, so that the power consumption of the source driver may be reduced, and the performance of the display panel 10I' may be improved.
Fig. 15 is an equivalent circuit diagram of a display panel according to another embodiment of the present invention. Referring to fig. 15, in the present embodiment, the display panel 10J includes a first gate line SL1, a second gate line SL2 and a first data line DL 1. The first data line DL1 and the first gate line SL1 and/or the second gate line SL2 are disposed on the first substrate 100 and extend in different directions. For example, the first data line DL1 crosses the first gate line SL1 and the second gate line SL 2.
The display panel 10J further includes pixels (not shown) electrically connected to the first gate line SL1, the second gate line SL2 and the first data line DL 1. For example, the pixel includes a first sub-pixel area PX1 and a second sub-pixel area PX 2. The first sub-pixel region PX1 includes a first switching element TFT1 and a first pixel electrode PE1 electrically connected to the first switching element TFT 1. The first switching element TFT1 is electrically connected to the first data line DL1 and the first gate line SL 1. In the present embodiment, a pixel capacitor (not labeled) is formed between the first pixel electrode PE1 and the common electrode layer 220 to electrically connect the first pixel electrode PE1 to the common electrode layer 220. The first pixel electrode PE1 may also be electrically connected to the first data line DL1 through the first switching element TFT 1. As shown in fig. 15, the first switching element TFT1 may also be electrically connected to a common electrode line COM to form a storage capacitor C1, but the invention is not limited thereto. In the present embodiment, the first switching element TFT1 has a control terminal electrically connected to the first gate line SL 1. Therefore, the charging and discharging of the first pixel electrode PE1 and the storage capacitor C1 are controlled by the first gate line SL1 through the first switching element TFT 1.
The second sub-pixel region PX2 includes a second switching element TFT2, a third switching element TFT3, and a second pixel electrode PE2 electrically connected to the second switching element TFT 2. The second switching element TFT2 is electrically connected to the first data line DL1 and the first gate line SL 1. In the present embodiment, a pixel capacitor (not labeled) is formed between the second pixel electrode PE2 and the common electrode layer 220 to electrically connect the second pixel electrode PE2 to the common electrode layer 220. The second pixel electrode PE2 may also be electrically connected to the first data line DL1 through the second switching element TFT 2. In this embodiment, the third switching element TFT3 may also be connected in series to the second switching element TFT2 and electrically connected to the second gate line SL 2. The third switching element TFT3 is electrically connected to the first capacitor CCS having the charge C. Under the above arrangement, the second pixel electrode PE2 can be electrically connected to the first capacitor CCS through the third switching element TFT 3. As shown in fig. 15, the second switching element TFT2 may also be electrically connected to the common electrode line COM to form a storage capacitor C2, but the invention is not limited thereto. In the present embodiment, the second switching element TFT2 has a control terminal electrically connected to the first gate line SL 1. Therefore, the charging and discharging of the second pixel electrode PE2 and the storage capacitor C2 are controlled by the first gate line SL1 through the second switching element TFT 2. In addition, the third switching element TFT3 has a control terminal electrically connected to the second gate line SL 2. Accordingly, charging and discharging of the first capacitor CCS is controlled by the second gate line SL2 through the third switching element TFT 3.
In the present embodiment, the display panel 10J can operate in a first state and a second state. When the display panel 10J operates in the first state, the first switching element TFT1 and the second switching element TFT2 are closed (ON), and the third switching element TFT3 is Open (OFF). In detail, the first switching element TFT1 and the second switching element TFT2 can be closed by the control of the first gate line SL 1. The third switching element TFT3 may be opened by the control of the second gate line SL 2.
Under the above configuration, the first pixel electrode PE1 and the second pixel electrode PE2 are electrically connected to the first data line DL1, such that the first voltage potential V1 is substantially equal to the second voltage potential V2. In the present embodiment, the first voltage potential V1 is defined as a voltage potential between the first pixel electrode PE1 and the common electrode layer 220. The second voltage potential V2 is defined as the voltage potential between the second pixel electrode PE2 and the common electrode layer 220. In the present embodiment, the second pixel electrode PE2 is not connected to the first capacitor CCS, and the first capacitor CCS may be charged with the charge C through the common electrode line COM.
when the display panel 10J operates in the second state, the first switching element TFT1 and the second switching element TFT2 are Open (OFF), and the third switching element TFT3 is closed (ON). In detail, the first switching element TFT1 and the second switching element TFT2 can be opened by the control of the first gate line SL 1. The third switching element TFT3 can be closed by the control of the second gate line SL 2.
Under the above arrangement, the first pixel electrode PE1 and the second pixel electrode PE2 are not electrically connected to the first data line DL 1. At this time, the first capacitor CCS is electrically connected to the second pixel electrode PE 2. Therefore, the charge C on the first capacitor CCS can be redistributed to the second pixel electrode PE2, so as to achieve the charge sharing requirement. Thus, the first voltage potential V1 can be made different from the second voltage potential V2. Based on the above, the overall voltage potential of the first sub-pixel PX1 may be different from the overall voltage potential of the second sub-pixel PX2, so as to improve the voltage difference between the liquid crystal layers of the display panel 10J, and further improve the display quality of the display panel 10J.
In summary, the light-shielding layer of the display panel according to an embodiment of the invention can be disposed corresponding to the pixel array, the data line, and the first supporting structure or the second supporting structure. Therefore, the display panel can integrate the light shielding layer required for arranging the first support structure and/or the second support structure and the light shielding layer for shielding the pixel array into the first light shielding pattern and/or the second light shielding pattern. Therefore, the area occupied by the whole light shielding layer can be reduced, and the aperture opening ratio and the display quality of the pixels of the display panel are improved.
In addition, the first thickness of the first subpixel color layer is greater than the second thickness of the second subpixel color layer. As such, the first support structure overlapping the first light shielding pattern may overlap and contact the first protrusion or the first light shielding pattern. The second support structure overlapping the second light shielding pattern may overlap but not contact the second protrusion or the second light shielding pattern. Therefore, the first supporting structure and the second supporting structure can be used as a main supporting structure and an auxiliary supporting structure respectively. Under the above arrangement, the display panel can control the thickness of the sub-pixel color layer and the heights of the first supporting structure and the second supporting structure, so that the first supporting structure and the second supporting structure can respectively provide the support and the elasticity required by the display panel, thereby improving the reliability and the quality of the display panel.
In addition, the display panel of the invention can also control the surfaces of the second insulating layer at different heights, so that the first supporting structure and the second supporting structure can respectively provide the support and the elasticity required by the display panel, thereby improving the reliability and the quality of the display panel.
In addition, the light-shielding layer and the gate line or the data line of the invention can also be respectively provided with corresponding accommodating spaces or openings. Therefore, the first supporting structure can be limited by the side wall and kept to be overlapped in the accommodating space or the opening. Therefore, the probability of displacement of the first supporting structure can be further reduced, and the reliability of the display panel is improved. In addition, the openings on the data lines can reduce the generation of crosstalk and parasitic capacitance, thereby improving the display quality of the display panel.
In addition, the invention can also make the number of the data lines half of the number of the gate lines through a half-source driving framework, thereby reducing the power consumption of the source driver and improving the performance of the display panel.
in addition, the display panel of the invention may further include a first capacitor electrically connected to the second pixel electrode pair through a third switching element. Therefore, the charges on the first capacitor can be redistributed to the second pixel electrode, and the charge sharing requirement is realized. Therefore, the pressure difference between the liquid crystal layers of the display panel can be improved, and the display quality of the display panel is further improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (23)
1. A display panel, comprising:
A first substrate and a second substrate opposite to the first substrate;
A pixel array disposed on the first substrate;
A first data line disposed on the first substrate;
A first gate line and a second gate line disposed on the first substrate, the first gate line and the second gate line intersecting the first data line, and the first data line, the first gate line and the second gate line being electrically connected to the pixel array;
A first sub-pixel color layer, a second sub-pixel color layer and a third sub-pixel color layer are arranged on one of the first substrate and the second substrate, the orthographic projection parts of the first sub-pixel color layer, the second sub-pixel color layer and the third sub-pixel color layer on the first substrate are positioned between the orthographic projection of the first gate line and the orthographic projection of the second gate line on the first substrate, and the second sub-pixel color layer is positioned between the first sub-pixel color layer and the third sub-pixel color layer;
A first supporting structure arranged between the first substrate and the second substrate, wherein the first supporting structure overlaps the first sub-pixel color layer in a direction perpendicular to the first substrate; and
a plurality of second supporting structures arranged between the first substrate and the second substrate, wherein the second supporting structures are respectively overlapped with the second sub-pixel color layer and the third sub-pixel color layer in the direction vertical to the first substrate,
Wherein the first sub-pixel color layer has a first protrusion and a first recess, the second sub-pixel color layer has a second protrusion, the third sub-pixel color layer has a third protrusion, and the second protrusion is embedded into the first recess at the adjacent boundary of the first sub-pixel color layer and the second sub-pixel color layer,
Wherein, in the direction perpendicular to the first substrate, the orthographic projection of the first supporting structure on the first substrate overlaps the orthographic projection of the first convex part on the first substrate, and the orthographic projection of one of the plurality of second supporting structures on the first substrate overlaps the orthographic projection of the second convex part on the first substrate,
Wherein the first sub-pixel color layer has a first thickness H1, the second sub-pixel color layer has a second thickness H2, and H1 is greater than H2.
2. The display panel of claim 1, further comprising a first light-shielding pattern and a second light-shielding pattern respectively disposed on the second substrate, wherein the first light-shielding pattern partially overlaps the first protrusion and the first supporting structure, and the second light-shielding pattern partially overlaps the second protrusion and one of the plurality of second supporting structures.
3. The display panel of claim 2, wherein the first, second, and third subpixel color layers are disposed on the first substrate, the first subpixel color layer covers the first data line, and a portion of the first data line overlaps the first protrusion and the first support structure.
4. the display panel of claim 3, further comprising a second data line disposed parallel to the first data line, the second data line overlapping an adjacent boundary of the first subpixel color layer and the second subpixel color layer, the second subpixel color layer covering the second data line, and a portion of the second data line overlapping one of the second protrusion and the second support structure.
5. The display panel of claim 2, wherein the first supporting structure and the plurality of second supporting structures are disposed on the second substrate, a bottom surface of the first supporting structure is disposed on the first light-shielding pattern, a top surface of the first supporting structure abuts against the first sub-pixel color layer, and one of the plurality of second supporting structures is disposed on the second light-shielding pattern.
6. The display panel of claim 2, wherein the first support structure and the plurality of second support structures are disposed on the first substrate, a bottom surface of the first support structure is disposed on the first sub-pixel color layer, a top surface of the first support structure abuts against the first light blocking pattern, and one of the plurality of second support structures is disposed on the second sub-pixel color layer.
7. The display panel of claim 6, wherein the first light-shielding pattern comprises a flat portion and a protrusion portion, a height difference is formed between a surface of the flat portion and a lower surface of the protrusion portion, and the protrusion portion surrounds an accommodating space, wherein the first supporting structure overlaps the accommodating space, and the top surface of the first supporting structure abuts against a surface of the flat portion.
8. The display panel of claim 1, wherein the first data line includes a first opening, the first supporting structure correspondingly overlaps the first opening, and the first data line further includes a first branch and a second branch respectively located at two opposite sides of the first opening, an orthographic projection of the first supporting structure on the first substrate is located between orthographic projections of the first branch and the second branch on the first substrate.
9. the display panel of claim 1, wherein the first gate line includes a second opening, a portion of the first data line overlaps the second opening, and the first data line has a first width W1 in a direction perpendicular to an extension direction of the first data line, the second opening has a second width W2, and W2> W1.
10. The display panel of claim 1, further comprising:
A common electrode line and the first gate line extend in the same direction;
a second data line extending in the same direction as the first data line and crossing the first gate line and the common electrode line,
the first support structure is correspondingly overlapped between the common electrode line and the first gate line and between the first data line and the second data line.
11. The display panel of claim 1, further comprising:
A plurality of pixel electrodes electrically connected to the pixel array, respectively,
Wherein the plurality of pixel electrodes are located between the first gate line and the second gate line,
Wherein two of the pixel electrodes located in the same row and adjacent to each other are electrically connected to the first data line, the first gate line and the second gate line, respectively.
12. the display panel of claim 1, further comprising:
a fourth sub-pixel color layer, a fifth sub-pixel color layer and a sixth sub-pixel color layer disposed on one of the first substrate and the second substrate, wherein orthographic projections of the fourth sub-pixel color layer, the fifth sub-pixel color layer and the sixth sub-pixel color layer on the first substrate are located between orthographic projections of the first gate line and the second gate line on the first substrate,
Wherein the fourth sub-pixel color layer is located between the third sub-pixel color layer and the fifth sub-pixel color layer, the fifth sub-pixel color layer is located between the fourth sub-pixel color layer and the sixth sub-pixel color layer,
Wherein the first sub-pixel color layer and the fourth sub-pixel color layer have a first color light, the second sub-pixel color layer and the fifth sub-pixel color layer have a second color light, and the third sub-pixel color layer and the sixth sub-pixel color layer have a third color light,
Wherein the plurality of second support structures overlap the fifth subpixel color layer and the sixth subpixel color layer, respectively.
13. The display panel of claim 12, wherein the third sub-pixel color layer further comprises a third protrusion, the fourth sub-pixel color layer comprises a fourth recess, and the third protrusion is embedded in the fourth recess at the boundary between the third sub-pixel color layer and the fourth sub-pixel color layer, and the second supporting structure overlaps the third protrusion in a direction perpendicular to the first substrate.
14. A display panel, comprising:
A first substrate and a second substrate opposite to the first substrate;
A pixel array disposed on the first substrate;
A first data line disposed on the first substrate;
a first gate line and a second gate line disposed on the first substrate, the first gate line and the second gate line intersecting the first data line, and the first data line, the first gate line and the second gate line being electrically connected to the pixel array;
A first sub-pixel color layer and a second sub-pixel color layer are arranged on one of the first substrate and the second substrate, the orthographic projections of the first sub-pixel color layer and the second sub-pixel color layer on the first substrate are positioned between the orthographic projections of the first gate line and the second gate line on the first substrate, and the first sub-pixel color layer is arranged adjacent to the second sub-pixel color layer; and
A first supporting structure disposed between the first substrate and the second substrate,
Wherein the first data line is overlapped with the adjacent boundary of the first sub-pixel color layer and the second sub-pixel color layer, and the first data line or the first gate line is provided with an opening,
Wherein, the orthographic projection of the first supporting structure on the first substrate is overlapped with the opening.
15. The display panel of claim 14, wherein the first subpixel color layer has a first protrusion, the second subpixel color layer has a second recess, and the first protrusion is embedded into the second recess at an adjacent boundary of the first subpixel color layer and the second subpixel color layer,
Wherein, in the direction perpendicular to the first substrate, the orthographic projection of the first supporting structure on the first substrate overlaps the orthographic projection of the first convex part on the first substrate,
Wherein the first sub-pixel color layer has a first thickness H1, the second sub-pixel color layer has a second thickness H2, and H1 is greater than H2.
16. the display panel of claim 14, further comprising a plurality of second support structures disposed between the first substrate and the second substrate, the plurality of second support structures respectively overlapping the first gate lines, and one of the plurality of second support structures overlapping the second subpixel color layer.
17. The display panel of claim 14, further comprising:
A third sub-pixel color layer, a fourth sub-pixel color layer, a fifth sub-pixel color layer and a sixth sub-pixel color layer disposed on one of the first substrate and the second substrate, wherein orthographic projections of the third sub-pixel color layer, the fourth sub-pixel color layer, the fifth sub-pixel color layer and the sixth sub-pixel color layer on the first substrate are located between orthographic projections of the first gate line and the second gate line on the first substrate,
Wherein the fourth sub-pixel color layer is located between the third sub-pixel color layer and the fifth sub-pixel color layer, the fifth sub-pixel color layer is located between the fourth sub-pixel color layer and the sixth sub-pixel color layer,
Wherein the first sub-pixel color layer and the fourth sub-pixel color layer have a first color light, the second sub-pixel color layer and the fifth sub-pixel color layer have a second color light, and the third sub-pixel color layer and the sixth sub-pixel color layer have a third color light,
Wherein the plurality of second support structures overlap the fifth subpixel color layer and the sixth subpixel color layer, respectively.
18. The display panel of claim 17, wherein the third sub-pixel color layer further comprises a third protrusion, the fourth sub-pixel color layer comprises a fourth recess, and the third protrusion is embedded in the fourth recess at the boundary between the third sub-pixel color layer and the fourth sub-pixel color layer, and the second supporting structure overlaps the third protrusion in a direction perpendicular to the first substrate.
19. A display panel having an array of pixels, the display panel comprising:
A first substrate having a plurality of gate lines including a first gate line and a second gate line, a plurality of data lines including a first data line, and a plurality of common electrode lines, the plurality of data lines and the plurality of gate lines being disposed in different directions;
A second substrate arranged opposite to the first substrate and having a first sub-pixel color layer arranged between the first substrate and the second substrate, and a common electrode layer arranged on the second substrate and covering the first sub-pixel color layer; and
A display medium layer disposed between the first substrate and the second substrate; wherein at least some of the pixels include a first sub-pixel region and a second sub-pixel region, the first sub-pixel region has a first pixel electrode disposed on the first substrate and electrically connected to the first data line via a first switch element, the second sub-pixel region has a second pixel electrode disposed on the first substrate and electrically connected to the first data line via a second switch element, the second pixel electrode is further connected to a first capacitor via a third switch element;
The first sub-pixel color layer is provided with a first convex part, a first supporting structure is arranged on the second substrate, and the first supporting structure is overlapped with the first convex part.
20. The display panel of claim 19, wherein the second substrate further has a second sub-pixel color layer disposed on the second substrate, the common electrode layer covers the second sub-pixel color layer, and the second sub-pixel color layer has a second concave portion, wherein the first convex portion is embedded in the second concave portion.
21. The display panel of claim 19, wherein the first switch element has a control terminal electrically connected to the first gate line, the second switch element has a control terminal electrically connected to the first gate line, and the third switch element has a control terminal electrically connected to the second gate line, so as to open or close the corresponding first switch element, the second switch element or the third switch element.
22. The display panel of claim 19, wherein the first data line includes a first opening, the first supporting structure correspondingly overlaps the first opening, and the first data line further includes a first branch and a second branch respectively located at two opposite sides of the first opening, an orthographic projection of the first supporting structure on the first substrate is located between orthographic projections of the first branch and the second branch on the first substrate.
23. The display panel of claim 19, wherein the first gate line includes a second opening, a portion of the first data line overlaps the second opening, and the first data line has a first width W1 in a direction perpendicular to the direction in which the first data line extends, the second opening has a second width W2, and W2> W1.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| US201862771264P | 2018-11-26 | 2018-11-26 | |
| US62/771,264 | 2018-11-26 | ||
| TW108118915A TWI699587B (en) | 2018-11-26 | 2019-05-31 | Display panel |
| TW108118915 | 2019-05-31 |
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| Publication Number | Publication Date |
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| CN110543046A true CN110543046A (en) | 2019-12-06 |
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| CN201910851716.5A Pending CN110543046A (en) | 2018-11-26 | 2019-09-06 | display panel |
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| CN112837617A (en) * | 2020-08-13 | 2021-05-25 | 友达光电股份有限公司 | Display panel |
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