CN112821871A - Doherty power amplifier chip based on current multiplexing drive circuit - Google Patents
Doherty power amplifier chip based on current multiplexing drive circuit Download PDFInfo
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- CN112821871A CN112821871A CN202011606713.4A CN202011606713A CN112821871A CN 112821871 A CN112821871 A CN 112821871A CN 202011606713 A CN202011606713 A CN 202011606713A CN 112821871 A CN112821871 A CN 112821871A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
Abstract
The invention discloses a Doherty power amplifier chip based on a current multiplexing drive circuit, which comprises: the pre-stage driving amplifier A is used for increasing the gain of a signal; and the last-stage Doherty power amplifier B is connected with the preceding-stage drive amplifier A and is used for amplifying the power of the signal after the gain is improved. The invention is realized by using the current multiplexing structure with the series resonance network for the driving circuit of the first two stages, the technology can provide more than 20dB of gain and reduce static power consumption, and the series LC resonance is used for enhancing the frequency band selection capability. The structure is simpler than two-stage cascade, so that the integration on a chip is more favorably realized.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a Doherty power amplifier chip based on a current multiplexing drive circuit.
Background
For today's wireless communication systems, the power amplifier in the transmitter is of vital importance. With the coming of the 5G era, the Sub-6GHz band is used first, and due to the characteristic that the electromagnetic wave coverage capability of the band is weak, people need to establish more small base stations to meet the coverage requirement, so that the requirements on the performance and the size of the power amplifier of the base station transmitter are higher and higher.
In order to ensure the bandwidth utilization rate of a communication system, high-order digital modulation needs to be carried out on signals, the modulated signals often have peak-to-average ratios as high as 10dB, and linear power amplification is needed. The saturation efficiency of a common linear class-B or class-AB amplifier is very high, but the efficiency of the common linear class-B or class-AB amplifier in a power back-off region is rapidly reduced, so that the power consumption of a transmitter and the volume of a radiator are increased, the power amplifier back-off efficiency is improved, the energy efficiency of the transmitter is greatly improved, and a Doherty amplifier is a technology which is widely used in communication and is used for improving the back-off efficiency. Since most applications of the 5G spectrum are focused on the n78 band represented by 3.5GHz, it is necessary to design a power amplifier chip in a Doherty amplifier applied to a small base station.
A conventional Doherty amplifier structure is shown in fig. 1, and its basic structure is composed of a carrier amplifier C and a peak amplifier P, wherein the carrier amplifier C is biased in class AB and the peak amplifier P is biased in class C. The transformation line after the carrier amplifier C performs an impedance transformation, and the compensation line before the peak amplifier P is used for phase compensation. When the high-power work is carried out, the peak amplifier P and the carrier amplifier C are simultaneously started, signals are simultaneously amplified through the carrier and the peak amplifier P by the power divider, and the load of the carrier amplifier C is low impedance; when the peak amplifier P is switched off in low-power operation, the 90-degree impedance transformation line transforms low-load impedance into high impedance, and the rollback efficiency is improved.
The above is only the basic principle of the Doherty amplifier, and the Doherty amplifier in practical application comprises one or two stages of pre-driver circuits, as shown in fig. 2. The two-stage pre-driving circuit is only used for improving the system gain and does not contribute to the output power, and the respective biasing circuits can generate static power consumption to reduce the overall efficiency of the power amplifier, so that the reduction of the static power consumption of the driving circuit is significant.
The circuit architecture can be easily realized by using a traditional radio frequency circuit board, but the circuit architecture is large in size and is not suitable for being used in a small base station, so that a low-power-consumption two-stage driving circuit and a Doherty amplifier are integrated on a chip.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a Doherty power amplifier chip based on a current multiplexing drive circuit, which is used for solving the problem of static power consumption of a preceding stage drive circuit of the Doherty amplifier.
The invention provides a Doherty power amplifier chip based on a current multiplexing drive circuit. The technical problem to be solved by the invention is realized by the following technical scheme:
a Doherty power amplifier chip based on a current multiplexing drive circuit comprises:
the pre-stage driving amplifier A is used for increasing the gain of a signal;
the last-stage Doherty power amplifier B is connected with the preceding-stage drive amplifier A and is used for amplifying the power of the signal after the gain is improved;
the pre-stage driving amplifier A comprises an input matching circuit, an inter-stage matching circuit, a first output matching circuit, two base bias circuits, an inductor L1, an inductor L2, an inductor Ls, a transistor Q1, a transistor Q2, a capacitor C1 and a capacitor Cs, wherein,
the input matching circuit is connected with an input end, the input matching circuit is connected with the base of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected with one end of the inter-stage matching circuit and one end of the inductor L1, the other end of the inter-stage matching circuit is connected with one end of the inductor Ls, the other end of the inductor L1 is connected with the emitter of the transistor Q2 and one end of the capacitor C1, the other end of the inductor Ls is connected with one end of the capacitor Cs, the other end of the capacitor Cs is connected with the base of the transistor Q2, the emitter of the transistor Q2 is connected with one end of the capacitor C1, the other end of the capacitor C1 is grounded, the collector of the transistor Q2 is connected with one end of the inductor L2 and the first output matching circuit, the other end of the inductor L2 is connected with a voltage source Vcc, the first output matching circuit is connected with the final, the base bias circuit is also connected between the input matching circuit and the transistor Q1, and the base bias circuit is also connected between the capacitor Cs and the transistor Q2.
In one embodiment of the present invention, the input matching circuit includes a capacitor C3 and an inductor L3, wherein,
one end of the capacitor C3 is connected to the input end and one end of the inductor L3, the other end of the capacitor C3 is grounded, and the other end of the inductor L3 is connected to the base of the transistor Q1.
In one embodiment of the present invention, the interstage matching circuit comprises a capacitor C4, wherein,
one end of the capacitor C4 is connected to the collector of the transistor Q1 and the inductor Ls, and the other end of the capacitor C4 is grounded.
In one embodiment of the present invention, the first output matching circuit includes a capacitor C5, wherein,
one end of the capacitor C5 is connected with the collector of the transistor Q2 and the final Doherty power amplifier B, and the other end of the capacitor C5 is grounded.
In one embodiment of the present invention, the final Doherty power amplifier B comprises a lumped power divider C, a carrier amplifier D, a peak amplifier E and a second output matching circuit F, wherein,
the input end of the lumped power divider C is connected with the output end of the pre-stage drive amplifier a, the first output end of the lumped power divider C is connected with the input end of the carrier amplifier D, the second output end of the lumped power divider C is connected with the input end of the peak amplifier E, and the output ends of the carrier amplifier D and the peak amplifier E are both connected with the second output matching circuit F.
In one embodiment of the present invention, the lumped power divider C includes a capacitor C6, a capacitor C7, a capacitor C8, an inductor L4, an inductor L5, and a resistor R2, wherein,
one end of the capacitor C6 is connected with the pre-stage driving amplifier A, the other end of the capacitor C6 is connected with one end of the inductor L4, one end of the inductor L5, one end of the capacitor C7 and one end of the capacitor C8, the other end of the inductor L4 and the other end of the inductor L5 are all grounded, the other end of the capacitor C7 is connected with one end of the resistor R2, one end of the capacitor C8 is connected with the other end of the resistor R2, one end of the resistor R2 is connected with the carrier amplifier D, and the other end of the resistor R2 is connected with the peak amplifier E.
In one embodiment of the present invention, the carrier amplifier D includes a compensation line C, a capacitor C9, a capacitor C10, a capacitor C11, a transistor Q3, an inductor L6, an inductor L7, and a base bias circuit, wherein,
one end of the compensation line C is connected to the resistor R2, the other end of the compensation line C is connected to one end of the capacitor C9 and the base of the transistor Q3, the other end of the capacitor C9 is grounded, the capacitor C9 and the transistor Q3 are further connected to one base bias circuit, the emitter of the transistor Q3 is grounded, the collector of the transistor Q3 is connected to one end of the inductor L6 and one end of the inductor L7, the other end of the inductor L6 is connected to the voltage source Vcc, the other end of the inductor L7 is connected to one end of the capacitor C10 and one end of the capacitor C11, the other end of the capacitor C10 is grounded, and the other end of the capacitor C11 is connected to the second output matching circuit F.
In one embodiment of the present invention, the peak amplifier E comprises a compensation line P, a capacitor C12, a transistor Q4, an inductor L8, an inductor L9, an inductor L10, an inductor L11, and a base bias circuit, wherein,
one end of the compensation line P is connected to the resistor R2, the other end of the compensation line P is connected to one end of the inductor L8 and the base of the transistor Q4, the other end of the inductor L8 is grounded, the inductor L8 and the transistor Q4 are also connected to one base bias circuit, the emitter of the transistor Q4 is grounded, the collector of the transistor Q4 is connected to one end of the inductor L9 and one end of the capacitor C12, the other end of the inductor L9 is connected to the voltage source Vcc, the other end of the capacitor C12 is connected to one end of the inductor L10 and one end of the inductor L11, the other end of the inductor L10 is grounded, and the other end of the inductor L11 is connected to the second output matching circuit F.
In one embodiment of the present invention, the second output matching circuit F includes a capacitor C13 and an inductor L12, wherein,
one end of the inductor L12 is connected to the output end of the carrier amplifier D and the output end of the peak amplifier E, the other end of the inductor L12 is connected to one end of the capacitor C13, and the other end of the capacitor C13 is grounded.
In one embodiment of the present invention, the base bias circuit includes a transistor Q5, a transistor Q6, a transistor Q7, a capacitor C2, and a resistor R1, wherein,
the emitter of the transistor Q3 is grounded, the emitter of the transistor Q5 is further connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the collector of the transistor Q6, the base of the transistor Q5 is connected to the collector of the transistor Q5 and the emitter of the transistor Q6, the collector of the transistor Q5 is further connected to the emitter of the transistor Q6, the base of the transistor Q6 is connected to the base of the transistor Q7, the collector of the transistor Q6 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the collector of the transistor Q7.
The invention has the beneficial effects that:
the invention is realized by using the current multiplexing structure with the series resonance network for the driving circuit of the first two stages, the technology can provide more than 20dB of gain and reduce static power consumption, and the series LC resonance is used for enhancing the frequency band selection capability. The structure is simpler than two-stage cascade, so that the integration on a chip is more favorably realized.
The invention combines the current multiplexing technology and the Doherty amplifier, and uses the current multiplexing structure with the series resonance network to improve the front-stage driving circuit, thereby not only reducing the total static power consumption of the system and improving the out-of-band rejection capability, but also providing the gain equivalent to the traditional two-stage driving amplifier.
The invention changes the design of the traditional Doherty power amplifier driving stage circuit, and the integration of the front-stage driving and the last-stage Doherty power amplifier is easier to realize on a GaAs process chip, and the mode has universality and can be applied to other types of compound semiconductor processes.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a structural diagram of a conventional Doherty power amplifier provided in an embodiment of the present invention;
fig. 2 is a diagram of a Doherty structure used in practical application according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a Doherty power amplifier chip based on a current multiplexing driving circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pre-driver amplifier a according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another Doherty power amplifier chip based on a current multiplexing driving circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a base bias circuit according to an embodiment of the present invention;
FIG. 7 is a diagram of a small signal simulation result of current-multiplexed pre-driver employed in an embodiment of the present invention;
fig. 8 is a diagram of simulation results of the efficiency and gain of the Doherty power amplifier chip of the invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 3, fig. 3 is a schematic structural diagram of a Doherty power amplifier chip based on a current multiplexing driving circuit according to an embodiment of the present invention. The embodiment provides a Doherty power amplifier chip based on a current multiplexing drive circuit, which comprises a front-stage drive amplifier A and a final-stage Doherty power amplifier B, wherein the front-stage drive amplifier A is used for increasing the gain of a signal, the final-stage Doherty power amplifier B is connected with the front-stage drive amplifier A, and the final-stage Doherty power amplifier B is used for performing power amplification on the signal after the gain is increased.
In this embodiment, referring to fig. 4, the pre-stage driver amplifier a includes an input matching circuit, an inter-stage matching circuit, a first output matching circuit, two base bias circuits, an inductor L1, an inductor L2, an inductor Ls, a transistor Q1, a transistor Q2, a capacitor C1, and a capacitor Cs, wherein the input matching circuit is connected to an input terminal, the input matching circuit is connected to a base of a transistor Q63 1, an emitter of a transistor Q1 is grounded, a collector of a transistor Q1 is connected to one end of the inter-stage matching circuit and one end of an inductor L1, the other end of the inter-stage matching circuit is connected to one end of an inductor Ls, the other end of an inductor L1 is connected to an emitter of a transistor Q2 and one end of a capacitor C1, the other end of the inductor Ls is connected to one end of a capacitor Cs, the other end of a capacitor Cs is connected to a base of a transistor Q2, an emitter of a, the collector of the transistor Q2 is connected with one end of an inductor L2 and a first output matching circuit, the other end of the inductor L2 is connected with a voltage source Vcc, the first output matching circuit is connected with a final-stage Doherty power amplifier B, a base bias circuit is also connected between the input matching circuit and the transistor Q1, and a base bias circuit is also connected between the capacitor Cs and the transistor Q2.
The Doherty amplifier of the embodiment is composed of two parts, namely a front-stage driver amplifier a and a final-stage Doherty power amplifier B. All transistor base biasing uses current sources.
As shown in fig. 4, the pre-stage driver amplifier a of this embodiment is composed of a two-stage driver transistor Q1 and a transistor Q2, wherein the transistor Q2 is shorted to ground through a capacitor C1, an inductor L1 and an inductor L2 respectively bias the transistor Q1 and the transistor Q2, a collector quiescent current is multiplexed to ground through the inductor L2, the transistor Q2, the inductor L1 and the transistor Q1, and since the transistor Q1 and the transistor Q2 use the same current, their quiescent power consumption is smaller than that when two transistors are respectively biased. The radio frequency signal is output from the collector of the transistor Q1 and is input to the base of the transistor Q1 through an interstage matching circuit, an inductor Ls and a capacitor Cs, wherein the out-of-band rejection capability can be enhanced through a series resonance circuit formed by the inductor Ls and the capacitor Cs.
Further, referring to fig. 5, the input matching circuit includes a capacitor C3 and an inductor L3, wherein one end of the capacitor C3 is connected to the input terminal and one end of the inductor L3, the other end of the capacitor C3 is grounded, and the other end of the inductor L3 is connected to the base of the transistor Q1.
Further, with continued reference to fig. 5, the inter-stage matching circuit includes a capacitor C4, wherein one end of the capacitor C4 is connected to the collector of the transistor Q1 and the inductor Ls, and the other end of the capacitor C4 is grounded.
Further, with continued reference to fig. 5, the first output matching circuit includes a capacitor C5, wherein one end of the capacitor C5 is connected to the collector of the transistor Q2 and the final Doherty power amplifier B, and the other end of the capacitor C5 is grounded.
Further, referring to fig. 6, the base bias circuit of the present embodiment includes a transistor Q5, a transistor Q6, a transistor Q7, a capacitor C2, and a resistor R1, wherein an emitter of the transistor Q3 is grounded, an emitter of the transistor Q5 is further connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to a collector of the transistor Q6, a base of the transistor Q5 is connected to a collector of the transistor Q5 and an emitter of the transistor Q6, a collector of the transistor Q5 is further connected to an emitter of the transistor Q6, a base of the transistor Q6 is connected to a base of the transistor Q7, a collector of the transistor Q6 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to a collector of.
In the present embodiment, the base bias circuit connected between the input matching circuit and the transistor Q1 is a base bias circuit in which the emitter of the transistor Q7 of the base bias circuit is connected between the input matching circuit and the base of the transistor Q1, the emitter of the transistor Q7 of the base bias circuit is connected between the capacitor Cs and the base of the transistor Q2, and the resistors R1 of the base bias circuit are both connected to the power supply.
Referring to fig. 5, the final Doherty power amplifier B includes a lumped power divider C, a carrier amplifier D, a peak amplifier E and a second output matching circuit F, wherein an input terminal of the lumped power divider C is connected to an output terminal of the pre-driver amplifier a, a first output terminal of the lumped power divider C is connected to an input terminal of the carrier amplifier D, a second output terminal of the lumped power divider C is connected to an input terminal of the peak amplifier E, and an output terminal of the carrier amplifier D and an output terminal of the peak amplifier E are both connected to the second output matching circuit F.
Further, the lumped power divider C includes a capacitor C6, a capacitor C7, a capacitor C8, an inductor L4, an inductor L5, and a resistor R2, wherein one end of the capacitor C6 is connected to the capacitor C5 of the pre-driver a and the collector of the transistor Q2, the other end of the capacitor C6 is connected to one end of the inductor L4, one end of the inductor L5, one end of the capacitor C7, and one end of the capacitor C8, the other end of the inductor L4 and the other end of the inductor L5 are both grounded, the other end of the capacitor C7 is connected to one end of the resistor R2, one end of the capacitor C8 is connected to the other end of the resistor R2, one end of the resistor R2 is connected to the carrier amplifier D, and the other end of the resistor R2 is.
Further, the carrier amplifier D includes a compensation line C, a capacitor C9, a capacitor C10, a capacitor C11, a transistor Q3, an inductor L6, an inductor L7, and a base bias circuit, wherein one end of the compensation line C is connected to the resistor R2, the other end of the compensation line C is connected to one end of the capacitor C9 and the base of the transistor Q3, the other end of the capacitor C9 is grounded, a base bias circuit is further connected between the capacitor C9 and the transistor Q3, the emitter of the transistor Q3 is grounded, the collector of the transistor Q3 is connected to one end of the inductor L6 and one end of the inductor L7, the other end of the inductor L6 is connected to the voltage source Vcc, the other end of the inductor L7 is connected to one end of the capacitor C10 and one end of the capacitor C11, the other end of the capacitor C10 is grounded, and the other end of the capacitor C.
Further, the peak amplifier E includes a compensation line P, a capacitor C12, a transistor Q4, an inductor L8, an inductor L9, an inductor L10, an inductor L11, and a base bias circuit, wherein one end of the compensation line P is connected to the resistor R2, the other end of the compensation line P is connected to one end of the inductor L8 and the base of the transistor Q4, the other end of the inductor L8 is grounded, a base bias circuit is further connected between the inductor L8 and the transistor Q4, the emitter of the transistor Q4 is grounded, the collector of the transistor Q4 is connected to one end of the inductor L9 and one end of the capacitor C12, the other end of the inductor L9 is connected to the voltage source Vcc, the other end of the capacitor C12 is connected to one end of the inductor L10 and one end of the inductor L11, the other end of the inductor L10 is grounded, and the other end of the inductor L.
Further, the second output matching circuit F includes a capacitor C13 and an inductor L12, wherein one end of the inductor L12 is connected to the output terminal of the carrier amplifier D and the output terminal of the peak amplifier E, that is, the inductor L12 is connected to the capacitor C11 and the inductor L11, the other end of the inductor L12 is connected to one end of the capacitor C13, and the other end of the capacitor C13 is grounded.
In the present embodiment, the base bias circuit connected between the capacitor C9 and the transistor Q3 is a base bias circuit in which the emitter of the transistor Q7 of the base bias circuit is connected between the capacitor C9 and the base of the transistor Q3, the emitter of the transistor Q7 of the base bias circuit is connected between the inductor L8 and the base of the transistor Q4, and the resistors R1 of the base bias circuit are both connected to the power supply.
The final-stage Doherty power amplifier B of the embodiment uses a symmetric 6dB back-off structure, which includes a lumped power divider C; the carrier amplifier D is formed by a carrier circuit input matching circuit (consisting of a compensation line C and a capacitor C9), a carrier circuit transistor (a transistor Q3) and a carrier circuit output matching circuit (consisting of a capacitor C10, a capacitor C11 and an inductor L7); a peak amplifier E composed of a peak path input matching circuit (composed of a compensation line P and an inductor L8), a peak path transistor (transistor Q4), and a peak path output matching circuit (composed of a capacitor C12, an inductor L10, and an inductor L11); and finally a second output matching circuit F. The compensation line of this embodiment functions to generate a phase shift so that the carrier and peak circuits are phase balanced.
In this embodiment, a specific design scheme of the Doherty power amplifier chip is further provided, which includes:
1. the combined final stage transistor size is selected to meet the power requirements, and for a 6dB back-off structure, the carrier to peak transistor size ratio is selected to be 1, i.e., the size ratio of transistor Q3 to transistor Q4 is 1.
2. And selecting a proper current source circuit as base bias, and biasing the carrier circuit transistor in deep AB class and the peak circuit transistor in C class. And performing load traction simulation on the biased device to obtain an optimal impedance value.
3. And an input matching circuit and an output matching circuit of the carrier wave path and the peak value path are respectively designed according to the impedance values, so that the output matching of the carrier wave path realizes load modulation, the output of the peak value path is matched to high impedance, and the Doherty function can be realized. Before the carrier circuit or the peak circuit is input into the matching circuit, the phase compensation line is used to adjust the phase balance of the two circuits, and simultaneously, a lumped input power divider circuit (i.e., a lumped power divider C) is designed as shown in fig. 5.
4. The current multiplexing driving circuit is designed according to fig. 3, the selected transistor Q1 and the selected transistor Q2 are the same in size, the inductor L1 and the inductor L2 are designed to have the same inductance value and can block in-band signals, and the inductor Ls and the capacitor Cs are designed to resonate in-band to pass useful signals. Transistor Q1 and transistor Q2 are biased in the same class AB. And simulating the small-signal S parameter of the transistor Q1, and designing a matching circuit according to the S parameter to realize maximum gain matching.
5. The drive circuit (namely a front-stage drive amplifier A) and the Doherty power amplifier (namely a final-stage Doherty power amplifier B) are cascaded, and the simulation soft ADS is used for carrying out overall optimization.
In order to make the design scheme and advantages of the present invention clearer, the following will take a 3.5GHz medium-power Doherty amplifier based on GaAs HBT process as an example, and clearly and completely describe the technical scheme in the embodiments of the present invention with reference to the drawings in the present invention.
The following is an implementation scheme of the Doherty power amplifier chip with output power of 2W provided by the embodiment of the invention. Fig. 5 is a schematic diagram of the chip design, and the Doherty power amplifier chip comprises a front-stage driver amplifier a and a final-stage Doherty power amplifier B. The front-stage drive amplifier A is of a current multiplexing structure consisting of a transistor Q1 and a transistor Q2, the last-stage Doherty power amplifier B is composed of a lumped power divider C, a carrier amplifier D, a peak amplifier E and a second output matching circuit F, and the specific implementation scheme is as follows:
1. the carrier transistor Q3 and the peak transistor Q4 were determined to be connected in parallel using 24 HBT dies with emitter junction area of 3 × 20 × 2 μm, respectively, based on the output power of the symmetrical structure of 2W, the carrier transistor Q3 was biased in deep class AB using the current source circuit of fig. 6, the peak transistor Q4 was biased in the off state, and the load pull simulation was performed on the transistor Q3 and the transistor Q4, respectively, to obtain the optimum impedance value.
2. And (3) designing a carrier path output matching circuit according to the impedance value obtained in the step (1), so that the carrier path output matching circuit can realize the matching to 25 omega under low power and 50 omega under high power, and can also realize the function of impedance transformation. The output matching circuit of the peak circuit is designed to realize low power matching to high impedance more than 500 omega and high power matching to 50 omega. The input matching circuits of the carrier and peaking circuits are designed using conjugate matching to achieve maximum gain.
3. And (3) according to the carrier circuit amplifier and the peak circuit amplifier designed in the step (2), simulating and extracting the phase characteristics of large signals of the carrier circuit amplifier and the peak circuit amplifier to obtain a phase difference, and adding a phase compensation line in front of the amplifier with the phase advance according to actual conditions to balance the phase. The lumped power divider C is designed according to fig. 5, and the second output matching circuit F is designed to match 25 Ω to 50 Ω.
4. The pre-driver amplifier a according to fig. 5 uses 8 die with an emitter junction area of 3 x 20 x 3 square microns in parallel as driver transistor Q1 and transistor Q2, both of which are biased in the exact same class AB using the base bias circuit of fig. 6. The designed inductor Ls and the capacitor Cs are connected in series with a resonant network and are optimized in a simulation mode, so that the resonant network resonates in a band. The matching network is designed to achieve maximum gain matching based on the small signal S parameters of transistor Q1 and transistor Q2. Fig. 7 shows the small signal simulation result of the current multiplexing pre-driver, and the gain provided by the improved pre-driver circuit is more than 25 dB.
5. The front-stage drive amplifier A and the last-stage Doherty power amplifier B are cascaded to obtain an integral chip structure, the large signal simulation result of the chip is shown in FIG. 8, and as can be seen from the result, the overall gain of the chip is 37dB, the power of a 1dB compression point is 35dBm, and the 6dB back-off efficiency is 40%.
From the above embodiments, it can be seen that the GaAs HBT Doherty power amplifier chip using the current multiplexing driving circuit designed by the present invention can achieve high gain and high efficiency, and can meet the application scenario of a 5G small cell.
The invention is realized by using the current multiplexing structure with the series resonance network for the driving circuit of the first two stages, the technology can provide more than 20dB of gain and reduce static power consumption, and the series LC resonance is used for enhancing the frequency band selection capability. The structure is simpler than two-stage cascade, so that the integration on a chip is more favorably realized.
The invention combines the current multiplexing technology and the Doherty amplifier, and uses the current multiplexing structure with the series resonance network to improve the front-stage driving circuit, thereby not only reducing the total static power consumption of the system and improving the out-of-band rejection capability, but also providing the gain equivalent to the traditional two-stage driving amplifier.
The invention changes the design of the traditional Doherty power amplifier driving stage circuit, and the integration of the front-stage driving and the last-stage Doherty power amplifier is easier to realize on a GaAs process chip, and the mode has universality and can be applied to other types of compound semiconductor processes.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or data point described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or data points described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A Doherty power amplifier chip based on a current multiplexing drive circuit is characterized by comprising:
the pre-stage driving amplifier A is used for increasing the gain of a signal;
the last-stage Doherty power amplifier B is connected with the preceding-stage drive amplifier A and is used for amplifying the power of the signal after the gain is improved;
the pre-stage driving amplifier A comprises an input matching circuit, an inter-stage matching circuit, a first output matching circuit, two base bias circuits, an inductor L1, an inductor L2, an inductor Ls, a transistor Q1, a transistor Q2, a capacitor C1 and a capacitor Cs, wherein,
the input matching circuit is connected with an input end, the input matching circuit is connected with the base of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected with one end of the inter-stage matching circuit and one end of the inductor L1, the other end of the inter-stage matching circuit is connected with one end of the inductor Ls, the other end of the inductor L1 is connected with the emitter of the transistor Q2 and one end of the capacitor C1, the other end of the inductor Ls is connected with one end of the capacitor Cs, the other end of the capacitor Cs is connected with the base of the transistor Q2, the emitter of the transistor Q2 is connected with one end of the capacitor C1, the other end of the capacitor C1 is grounded, the collector of the transistor Q2 is connected with one end of the inductor L2 and the first output matching circuit, the other end of the inductor L2 is connected with a voltage source Vcc, the first output matching circuit is connected with the final, the base bias circuit is also connected between the input matching circuit and the transistor Q1, and the base bias circuit is also connected between the capacitor Cs and the transistor Q2.
2. The Doherty power amplifier chip of claim 1, wherein the input matching circuit includes a capacitor C3 and an inductor L3, wherein,
one end of the capacitor C3 is connected to the input end and one end of the inductor L3, the other end of the capacitor C3 is grounded, and the other end of the inductor L3 is connected to the base of the transistor Q1.
3. The Doherty power amplifier chip of claim 1, wherein the inter-stage matching circuit includes a capacitor C4, wherein,
one end of the capacitor C4 is connected to the collector of the transistor Q1 and the inductor Ls, and the other end of the capacitor C4 is grounded.
4. The Doherty power amplifier chip of claim 1, wherein the first output matching circuit includes a capacitor C5, wherein,
one end of the capacitor C5 is connected with the collector of the transistor Q2 and the final Doherty power amplifier B, and the other end of the capacitor C5 is grounded.
5. The Doherty power amplifier chip of claim 1, wherein the last-stage Doherty power amplifier B comprises a lumped power divider C, a carrier amplifier D, a peak amplifier E and a second output matching circuit F, wherein,
the input end of the lumped power divider C is connected with the output end of the pre-stage drive amplifier a, the first output end of the lumped power divider C is connected with the input end of the carrier amplifier D, the second output end of the lumped power divider C is connected with the input end of the peak amplifier E, and the output ends of the carrier amplifier D and the peak amplifier E are both connected with the second output matching circuit F.
6. The Doherty power amplifier chip of claim 5, wherein the lumped power divider C comprises a capacitor C6, a capacitor C7, a capacitor C8, an inductor L4, an inductor L5 and a resistor R2, wherein,
one end of the capacitor C6 is connected with the pre-stage driving amplifier A, the other end of the capacitor C6 is connected with one end of the inductor L4, one end of the inductor L5, one end of the capacitor C7 and one end of the capacitor C8, the other end of the inductor L4 and the other end of the inductor L5 are all grounded, the other end of the capacitor C7 is connected with one end of the resistor R2, one end of the capacitor C8 is connected with the other end of the resistor R2, one end of the resistor R2 is connected with the carrier amplifier D, and the other end of the resistor R2 is connected with the peak amplifier E.
7. The Doherty power amplifier chip of claim 6, wherein the carrier amplifier D comprises a compensation line C, a capacitor C9, a capacitor C10, a capacitor C11, a transistor Q3, an inductor L6, an inductor L7 and a base bias circuit, wherein,
one end of the compensation line C is connected to the resistor R2, the other end of the compensation line C is connected to one end of the capacitor C9 and the base of the transistor Q3, the other end of the capacitor C9 is grounded, the capacitor C9 and the transistor Q3 are further connected to one base bias circuit, the emitter of the transistor Q3 is grounded, the collector of the transistor Q3 is connected to one end of the inductor L6 and one end of the inductor L7, the other end of the inductor L6 is connected to the voltage source Vcc, the other end of the inductor L7 is connected to one end of the capacitor C10 and one end of the capacitor C11, the other end of the capacitor C10 is grounded, and the other end of the capacitor C11 is connected to the second output matching circuit F.
8. The Doherty power amplifier chip of claim 6, wherein the peaking amplifier E comprises a compensation line P, a capacitor C12, a transistor Q4, an inductor L8, an inductor L9, an inductor L10, an inductor L11 and a base bias circuit, wherein,
one end of the compensation line P is connected to the resistor R2, the other end of the compensation line P is connected to one end of the inductor L8 and the base of the transistor Q4, the other end of the inductor L8 is grounded, the inductor L8 and the transistor Q4 are also connected to one base bias circuit, the emitter of the transistor Q4 is grounded, the collector of the transistor Q4 is connected to one end of the inductor L9 and one end of the capacitor C12, the other end of the inductor L9 is connected to the voltage source Vcc, the other end of the capacitor C12 is connected to one end of the inductor L10 and one end of the inductor L11, the other end of the inductor L10 is grounded, and the other end of the inductor L11 is connected to the second output matching circuit F.
9. The Doherty power amplifier chip of claim 5, wherein the second output matching circuit F includes a capacitor C13 and an inductor L12, wherein,
one end of the inductor L12 is connected to the output end of the carrier amplifier D and the output end of the peak amplifier E, the other end of the inductor L12 is connected to one end of the capacitor C13, and the other end of the capacitor C13 is grounded.
10. The Doherty power amplifier chip of any one of claims 1, 7 or 8, wherein the base bias circuit includes a transistor Q5, a transistor Q6, a transistor Q7, a capacitor C2 and a resistor R1, wherein,
the emitter of the transistor Q3 is grounded, the emitter of the transistor Q5 is further connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the collector of the transistor Q6, the base of the transistor Q5 is connected to the collector of the transistor Q5 and the emitter of the transistor Q6, the collector of the transistor Q5 is further connected to the emitter of the transistor Q6, the base of the transistor Q6 is connected to the base of the transistor Q7, the collector of the transistor Q6 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the collector of the transistor Q7.
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