CN212210954U - High-stability power amplification integrated circuit - Google Patents
High-stability power amplification integrated circuit Download PDFInfo
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- CN212210954U CN212210954U CN202021251086.2U CN202021251086U CN212210954U CN 212210954 U CN212210954 U CN 212210954U CN 202021251086 U CN202021251086 U CN 202021251086U CN 212210954 U CN212210954 U CN 212210954U
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Abstract
The utility model provides a high-stability power amplification integrated circuit, which comprises a cascaded input matching circuit, a N-stage amplification module and an output matching circuit, and also comprises a plurality of interstage matching power division modules arranged between the amplification modules at all stages; the i-1 th stage amplifying module comprises a parallel 2i‑1An amplifier, a parallel 2 is arranged between the i-1 th stage and the i-th stage amplification modulei‑1Individual stage matching power dividing module, 2i‑12 of individual stage matching power division module and i-1 stage amplification modulei‑1The amplifiers are in one-to-one correspondence; the input matching circuit comprises a 1-path and 2-path power dividing unit and two input matching circuit isolation capacitors; the output matching circuit comprises a 2-stage amplifier moduleNOne is putThe output signals of the amplifiers are combined into a combining module of one path. The N stages of amplification modules are cascaded, each stage can carry out maximum output power matching, and the method has the characteristics of good overall linearity, in-band positive slope gain and good gain flatness; the interstage matching power division module is modularized, and impedance adjustment and matching debugging are facilitated.
Description
Technical Field
The utility model relates to an electronic communication field, concretely relates to high stability power amplification integrated circuit.
Background
The power amplifying circuit is used for a microwave wireless transceiving system to realize signal final-stage power amplification, must meet the signal link power radiation requirement, and is an indispensable important device in the fields of military radars, high-speed satellite communication, military, mobile communication and the like. With the rapid development of satellite mobile internet, 5G mobile communication and other related applications, the millimeter wave power amplifier such as Ka band will play an increasingly important role and have a wide market. With the development of microelectronic technology, Monolithic Microwave Integrated Circuits (MMICs) have the advantages of miniaturization, integration, good stability, strong anti-interference capability and consistent product performance, and are ideal choices for power amplifier development, however, the existing Ka band MMIC power amplifier Circuit still has the problems of poor stability, insufficient in-band gain flatness and the like.
SUMMERY OF THE UTILITY MODEL
In order to overcome the defects existing in the prior art, the utility model aims to provide a high stability power amplification integrated circuit.
In order to achieve the above object of the present invention, the present invention provides a high stability power amplification integrated circuit, which comprises a cascaded input matching circuit, N-stage amplification modules and output matching circuit, and further comprises a plurality of interstage matching power division modules disposed between the amplification modules at each stage; the i-1 th stage amplifying module comprises a parallel 2i-1An amplifier, a parallel 2 is arranged between the i-1 st stage amplification module and the i-th stage amplification modulei-1Individual stage matching power dividing module, said 2i-12 of individual stage matching power division module and i-1 stage amplification modulei-1The amplifiers are in one-to-one correspondence, the output ends of the amplifiers of the i-1 th-stage amplification module are connected with the input ends of the corresponding inter-stage matching power dividing modules, the inter-stage matching power dividing modules divide a received signal into two parts and respectively output the two parts to the input ends of the two amplifiers in the i-th-stage amplification module, i and N are positive integers, and i is more than 1 and less than or equal to N; the input matching circuit comprises a 1-path and 2-path power dividing unit and two input matching circuit isolation capacitors, wherein the input ends of the 1-path and 2-path power dividing unit are connected with an input voltage point, and the two output ends of the 1-path and 2-path power dividing unit are respectively connected with the input ends of two amplifiers of the first-stage amplification module through one input matching circuit isolation capacitor; the output matching circuit comprises a 2-stage amplifier moduleNThe output signal of each amplifier is combined into a combining module of one path, and the output end of the combining module is connected with an output pressure point.
The technical scheme is as follows: the power amplification integrated circuit is formed by cascading N stages of amplification modules, each stage of amplification module can carry out maximum output power matching, an interstage matching power division module is designed, an input/output port of the whole circuit system is matched with 50 ohm standard impedance, and the power amplification integrated circuit has the characteristics of good overall linearity, in-band positive slope gain and good gain flatness; the interstage matching circuits of the amplification modules are combined through the modularized interstage matching power division modules, impedance characteristics are similar, impedance adjustment and matching debugging are facilitated, optimal impedance matching and filtering of the amplification modules at all stages are finally formed, and circuit performance is guaranteed.
In a preferred embodiment of the present invention, the amplifier is a field effect transistor, the source of the field effect transistor is grounded, the gate is used as the input terminal of the amplifier, and the drain is used as the output terminal of the amplifier.
The technical scheme is as follows: and signal amplification is realized.
In a preferred embodiment of the present invention, the field effect transistor is a pseudomorphic modulation doped heterojunction field effect transistor.
The technical scheme is as follows: the field effect transistor has ultrahigh mobility, uniform current density distribution and improved stability.
In a preferred embodiment of the present invention, a gate bias network is connected to the gate of each field effect transistor, the gate bias network includes a gate bias resistor, a gate bias decoupling capacitor and a gate bias voltage point, the first end of the gate bias resistor is connected to the gate bias voltage point and the first end of the gate bias decoupling capacitor, the second end of the gate bias resistor is connected to the gate of the field effect transistor, and the second end of the gate bias decoupling capacitor is connected to ground.
The technical scheme is as follows: the grid voltage is provided through the grid bias resistor, the low-frequency oscillation of the field effect transistor is avoided, high impedance is formed, clutter signals are prevented from entering to a great extent, the low-frequency self-excitation phenomenon is effectively inhibited, and the overall stability of the field effect transistor is guaranteed.
In a preferred embodiment of the present invention, the interstage matching power dividing module includes a first transmission microstrip line of the interstage matching circuit, an isolation capacitor of the interstage matching circuit, a second transmission microstrip line of the interstage matching circuit, a third transmission microstrip line of two interstage matching circuits, a first bypass capacitor of two interstage matching circuits, and a fourth transmission microstrip line of two interstage matching circuits; the first end of the first transmission microstrip line of the interstage matching circuit is connected with the drain electrode of a field effect tube of the preceding stage amplification module, the second end of the first transmission microstrip line of the interstage matching circuit is connected with the first end of the second transmission microstrip line of the interstage matching circuit through an interstage matching circuit isolation capacitor, the second end of the second transmission microstrip line of the interstage matching circuit is connected with the first ends of the third transmission microstrip lines of the two interstage matching circuits respectively, the second end of each third transmission microstrip line of the interstage matching circuit is connected with the first end of a first bypass capacitor of the interstage matching circuit and the first end of a fourth transmission microstrip line of the interstage matching circuit respectively, the second end of each fourth transmission microstrip line of the interstage matching circuit is connected with the gate electrode of a field effect tube of the subsequent stage amplification module, and the second end of the first bypass capacitor of the interstage matching circuit is connected with the ground.
The technical scheme is as follows: the interstage matching power division module adopts a network structure of a 1-division-2 power divider, so that the gain flatness is improved; the interstage matching circuit isolation capacitor can effectively isolate direct current and reduce direct current interference.
In a preferred embodiment of the present invention, the interstage matching power dividing module further includes a drain bias network, the drain bias network includes a first drain bias sub-network and a second drain bias sub-network with the same structure, and the first drain bias sub-network and the second drain bias sub-network are symmetrically connected to the second end of the first transmission microstrip line of the interstage matching circuit; the first drain bias sub-network or the second drain bias sub-network comprises an interstage matching circuit open-circuit short-stub microstrip line, an interstage matching circuit second bypass capacitor and a drain bias voltage point, a first end of the interstage matching circuit open-circuit short-stub microstrip line is connected with a second end of the interstage matching circuit first transmission microstrip line, a second end of the interstage matching circuit open-circuit short-stub microstrip line is respectively connected with a first end of the interstage matching circuit second bypass capacitor and the drain bias voltage point, and a second end of the interstage matching circuit second bypass capacitor is connected with the ground.
The technical scheme is as follows: the low-frequency self-excitation phenomenon can be effectively inhibited, and the stability of the system is further ensured.
In a preferred embodiment of the present invention, the 1-division 2-path power dividing unit includes a first transmission microstrip line of an input matching circuit and two second transmission microstrip lines of the input matching circuit; one end of the first transmission microstrip line of the input matching circuit is connected with the input pressure point, the other end of the first transmission microstrip line of the input matching circuit is respectively connected with the first ends of the second transmission microstrip lines of the two input matching circuits, the second ends of the second transmission microstrip lines of the two input matching circuits are respectively connected with the first ends of the isolation capacitors of the two input matching circuits, and the second ends of the isolation capacitors of the input matching circuits are connected with the input end of the amplifier of the first-stage amplification module.
The technical scheme is as follows: the input pressure point is used for being connected with an external radio frequency input port, and the linearity of the post amplifier and the gain flatness are improved through a network structure similar to a 1-to-2 power divider.
The utility model discloses an in a preferred embodiment, input matching circuit still includes two impedance adjustment networks, impedance adjustment network includes that input matching circuit opens a way stub microstrip line and adjusting resistor, and adjusting resistor's first end ground connection, adjusting resistor's second end and the first end of input matching circuit opening a way stub microstrip line are connected, and input matching circuit opens a way stub microstrip line's second end and is connected with the first end of an input matching circuit isolation capacitance and 1 output that divides 2 way merit to divide the unit respectively.
The technical scheme is as follows: the impedance characteristics of the input matching circuit can be adjusted.
The utility model discloses an in a preferred embodiment, N is 3, amplify module and third level amplification module including first order amplification module, second level, first order amplification module includes two amplifiers, and second level amplification module includes 4 amplifiers, and third level amplification module includes 8 amplifiers, is equipped with parallel 2 interstage matching merit between first order amplification module and the second level amplification module and divides the module, is equipped with parallel 4 interstage matching merit between first order amplification module and the second level amplification module and divides the module.
The technical scheme is as follows: the three-stage amplifier is cascaded, the field effect transistor amplifiers of all stages carry out maximum output power matching, an interstage matching network is designed, the input and output ports of the whole circuit system are matched with 50-ohm standard impedance, and the circuit system has the characteristics of good overall linearity, in-band positive slope gain and good gain flatness.
In a preferred embodiment of the present invention, the combining module includes two 4-in-1-way combining circuits and a 2-in-one-way module, the two 4-in-1-way combining circuits are connected to two input terminals of the 2-in-one-way module after being connected to a drain bias network, respectively, and an output terminal of the 2-in-one-way module is connected to the output pressure point; four input ends of the 4-in-1-path combining circuit are respectively connected with output ends of 4 amplifier modules of the third-stage amplification module, and the output end of the 4-in-1-path combining circuit is also connected with a drain electrode biasing network.
The technical scheme is as follows: the output voltage point of the output matching circuit is used for being connected with an external radio frequency output port, and the effects of improving the linearity of the amplifier and improving the gain flatness are achieved through a network structure similar to a 1-to-8 power divider.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic diagram of a power amplifier integrated circuit according to a preferred embodiment of the present invention;
FIG. 2 is a diagram of an input matching circuit in a preferred embodiment of the present invention;
FIG. 3 is a block diagram of an inter-stage matching power division module in a preferred embodiment of the present invention;
FIG. 4 is a diagram of an output matching circuit in a preferred embodiment of the present invention;
FIG. 5 is a graph of the gain test result of the small signal in an application scenario of the present invention;
fig. 6 is a graph of the test results of VSWR1 and VSWR2 in an application scenario.
Reference numerals:
1, a first-stage amplification module; 2, a second-stage amplification module; 3, a third-stage amplifying module; 4 input matching circuit; 5 a first inter-stage matching circuit; 6 a second inter-stage matching circuit; 7 an output matching circuit; 101 inputting a pressure point; 102 inputting a first transmission microstrip line of the matching circuit; 103 inputting a second transmission microstrip line of the matching circuit; 104 inputting the matching circuit open-circuit short-stub microstrip line; 105 adjusting the resistance; 106 input matching circuit isolation capacitance; 201 interstage matching circuit preamplifier; 202 an interstage matching circuit first transmission microstrip line; 203, an interstage matching circuit is an open-circuit short-stub microstrip line; 204 interstage matching circuit second bypass capacitance; 205 drain bias voltage node; 206 interstage matching circuit isolation capacitance; 207 an interstage matching circuit second transmission microstrip line; 208 interstage matching circuit third transmission microstrip line; 209 first bypass capacitor of interstage matching circuit; 210 an interstage matching circuit, a fourth transmission microstrip line; 211 an interstage matching circuit post-stage amplifier; 301 output matching circuit first transmission microstrip line; 302 output matching circuit second transmission microstrip line; 303 output matching circuit first bypass capacitance; 304 output matching circuit third transmission microstrip line; 305 output a fourth transmission microstrip line of the matching circuit; 306 output matching circuit open short stub microstrip line; 307 output matching circuit bypass filter capacitance; 308 drain voltage node; 309 output matching circuit isolation capacitance; 310 output matching circuit fifth transmission microstrip line; 311 output matching circuit second bypass capacitance; 312 output matching circuit sixth transmission microstrip line; 313 outputting a seventh transmission microstrip line of the matching circuit; 314 output a pressure point.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, unless otherwise specified and limited, it is to be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, mechanically or electrically connected, or may be connected between two elements through an intermediate medium, or may be directly connected or indirectly connected, and specific meanings of the terms may be understood by those skilled in the art according to specific situations.
The utility model discloses a high stability power amplification integrated circuit, in a preferred embodiment, as shown in FIG. 1, this power amplification integrated circuit is including cascaded input matching circuit 4, N level amplification module and output matching circuit 7 to and still including locating the module is divided to a plurality of interstage matching powers between the amplification module at different levels.
The i-1 th stage amplifying module comprises a parallel 2i-1An amplifier, a parallel 2 is arranged between the i-1 st stage amplification module and the i-th stage amplification modulei-1Individual stage matching power dividing module, 2i-12 of individual stage matching power division module and i-1 stage amplification modulei-1The amplifiers are in one-to-one correspondence, the output ends of the amplifiers of the i-1 th-stage amplification module are connected with the input ends of the corresponding inter-stage matching power dividing modules, the inter-stage matching power dividing modules divide a received signal into two parts and respectively output the two parts to the input ends of the two amplifiers in the i-th-stage amplification module, i and N are positive integers, and i is more than 1 and less than or equal to N; the input matching circuit 4 comprises a 1-path and 2-path power dividing unit and two input matching circuit 4 isolation capacitors, the input end of the 1-path and 2-path power dividing unit is connected with the input voltage point 101, and the two output ends of the 1-path and 2-path power dividing unit are respectively connected with the input ends of the two amplifiers of the first-stage amplification module 1 through one input matching circuit 4 isolation capacitor.
The output matching circuit 7 includes a 2-stage amplifier moduleNThe output signals of the amplifiers are combined into a combining module, and the output end of the combining module is connected with the output pressure point 314.
In this embodiment, preferably, as shown in fig. 2, the 1-branch 2-path power dividing unit includes an input matching circuit first transmission microstrip line 102 and two input matching circuit second transmission microstrip lines 103; one end of the first transmission microstrip line 102 of the input matching circuit is connected to the input pressure point 101, the other end of the first transmission microstrip line 102 of the input matching circuit is respectively connected to the first ends of the second transmission microstrip lines 103 of the two input matching circuits, the second ends of the second transmission microstrip lines of the two input matching circuits 4 are respectively connected to the first ends of the isolation capacitors 106 of the two input matching circuits, and the second end of the isolation capacitor 106 of the input matching circuit is connected to the input end of the amplifier of the first-stage amplification module 1. The length and width of the input voltage point 101 is preferably, but not limited to, 100um × 150um, the length and width of the microstrip line of the input matching circuit first transmission microstrip line 102 is preferably, but not limited to, 75um × 60um, the length and width of the microstrip line of the input matching circuit second transmission microstrip line 103 is preferably, but not limited to, 20um × 950um, and the capacitance of the input matching circuit isolation capacitor 106 is preferably, but not limited to, 0.19 pF.
In this embodiment, it is further preferable that, as shown in fig. 2, the input matching circuit 4 further includes two impedance adjusting networks, each impedance adjusting network includes an input matching circuit open-circuited short-stub microstrip line 104 and an adjusting resistor 105, a first end of the adjusting resistor 105 is grounded, a second end of the adjusting resistor 105 is connected to a first end of the input matching circuit open-circuited short-stub microstrip line 104, and a second end of the input matching circuit open-circuited short-stub microstrip line 104 is connected to a first end of one input matching circuit isolation capacitor 106 and one output end of the 1-branch 2-path power dividing unit, respectively. The length and width of the microstrip line of the input matching circuit open-circuit short-stub microstrip line 104 is preferably, but not limited to, 20um × 100um, and the resistance value of the adjusting resistor 105 is preferably, but not limited to, 3 Ω.
In this embodiment, the amplifier is preferably, but not limited to, a field effect transistor or a triode.
In this embodiment, preferably, as shown in fig. 1, N is 3, the power amplification integrated circuit includes a first-stage amplification module 1, a second-stage amplification module 2, and a third-stage amplification module 3, the first-stage amplification module 1 includes two amplifiers, the second-stage amplification module 2 includes 4 amplifiers, the third-stage amplification module 3 includes 8 amplifiers, a first inter-stage matching circuit 5 is disposed between the first-stage amplification module 1 and the second-stage amplification module 2, the first inter-stage matching circuit 5 includes 2 parallel inter-stage matching power division modules, a second inter-stage matching circuit 6 is disposed between the first-stage amplification module 1 and the second-stage amplification module 2, and the second inter-stage matching circuit 6 includes 4 parallel inter-stage matching power division modules.
In a preferred embodiment, the amplifier is a field effect transistor, the source of which is connected to ground, the gate of which serves as the input of the amplifier, and the drain of which serves as the output of the amplifier. Further preferably, the field effect transistor is a modulation-pseudoscopic doped heterojunction field effect transistor, such as a 8x75um size modulation-pseudoscopic doped heterojunction field effect transistor having a 0.15um gallium arsenide die.
In this embodiment, it is preferable that a gate bias network is connected to the gate of each field effect transistor, the gate bias network includes a gate bias resistor, a gate bias decoupling capacitor, and a gate bias voltage node, a first end of the gate bias resistor is connected to the gate bias voltage node and a first end of the gate bias decoupling capacitor, respectively, a second end of the gate bias resistor is connected to the gate of the field effect transistor, and a second end of the gate bias decoupling capacitor is connected to ground. The resistance value of the grid bias resistor is preferably but not limited to 47 omega, the capacitance value of the grid bias decoupling capacitor is preferably but not limited to 2pF, the voltage value of the grid bias voltage pressure point can be-0.75V voltage, the voltage can be realized through an external voltage, the whole input matching circuit effectively inhibits out-of-band stray, and good input voltage standing wave ratio is provided.
In this embodiment, as shown in fig. 3, the inter-stage matching power dividing module preferably includes an inter-stage matching circuit first transmission microstrip line 202, an inter-stage matching circuit isolation capacitor 206, an inter-stage matching circuit second transmission microstrip line 207, two inter-stage matching circuit third transmission microstrip lines 208, two inter-stage matching circuit first bypass capacitors 209, and two inter-stage matching circuit fourth transmission microstrip lines 210; the first end of the first transmission microstrip line 202 of the interstage matching circuit is connected with the drain of a field effect transistor of the preceding stage amplification module, the second end of the first transmission microstrip line 202 of the interstage matching circuit is connected with the first end of the second transmission microstrip line 207 of the interstage matching circuit through an interstage matching circuit isolation capacitor 206, the second end of the second transmission microstrip line 207 of the interstage matching circuit is respectively connected with the first ends of the third transmission microstrip lines 208 of the two interstage matching circuits, the second end of each third transmission microstrip line 208 of the interstage matching circuit is respectively connected with the first end of a first bypass capacitor 209 of the interstage matching circuit and the first end of a fourth transmission microstrip line 210 of the interstage matching circuit, the second end of each fourth transmission microstrip line 210 of the interstage matching circuit is connected with the gate of a field effect transistor of the subsequent stage amplification module, and the second end of the first bypass capacitor 209 of the interstage matching circuit is connected with the ground.
In the present embodiment, the length and width of the transmission microstrip line of the first transmission microstrip line 202 of the inter-stage matching circuit is preferably, but not limited to, 50um × 75um, the capacitance value of the isolation capacitor 206 of the inter-stage matching circuit is preferably, but not limited to, 0.05pF, the length and width of the transmission microstrip line of the second transmission microstrip line 207 of the inter-stage matching circuit is preferably, but not limited to, 25um × 75um, the length and width of the transmission microstrip line of the third transmission microstrip line 208 of the inter-stage matching circuit is preferably, but not limited to, 25um × 200um, the capacitance value of the first bypass capacitor 209 of the inter-stage matching circuit is preferably, but not limited to, 0.18pF, and the length and width of the transmission microstrip line of the fourth transmission microstrip line 210 of the inter.
In this embodiment, a radio frequency signal amplified by a pre-stage amplifier is input through the first transmission microstrip line 202 of the inter-stage matching circuit, and a direct current is isolated through the isolation capacitor 206 of the inter-stage matching circuit; the 1-branch 2-path power divider is formed by the second transmission microstrip line 207 of the interstage matching circuit, the third transmission microstrip line 208 of the interstage matching circuit, the bypass capacitor 209 of the interstage matching circuit and the fourth transmission microstrip line 210 of the interstage matching circuit and is connected with the post-stage amplifier 211, and similarly, the post-stage amplifier simultaneously completes the matching of signals and a post-stage field effect transistor amplifier through a gate bias circuit.
In this embodiment, preferably, as shown in fig. 3, the inter-stage matching power dividing module further includes a drain bias network, where the drain bias network includes a first drain bias sub-network and a second drain bias sub-network with the same structure, and the first drain bias sub-network and the second drain bias sub-network are symmetrically connected to the second end of the first transmission microstrip line 202 of the inter-stage matching circuit; the first drain bias sub-network or the second drain bias sub-network comprises an inter-stage matching circuit open-circuit short-stub microstrip line 203, an inter-stage matching circuit second bypass capacitor 204 and a drain bias voltage point 205, a first end of the inter-stage matching circuit open-circuit short-stub microstrip line 203 is connected with a second end of the inter-stage matching circuit first transmission microstrip line 202, a second end of the inter-stage matching circuit open-circuit short-stub microstrip line 203 is respectively connected with a first end of the inter-stage matching circuit second bypass capacitor 204 and the drain bias voltage point 205, and a second end of the inter-stage matching circuit second bypass capacitor 204 is connected with the ground.
In this embodiment, the length and width of the transmission microstrip line of the inter-stage matching circuit open-circuit short-stub microstrip line 203 is preferably, but not limited to, 50um × 350um, the capacitance value of the bypass filter capacitor 204 is preferably, but not limited to, 2pF, the length and width of the drain voltage node 205 is preferably, but not limited to, 100um × 100um, and the voltage value of the drain bias voltage node 205 is preferably, but not limited to, externally connected to a 6V dc power supply through a bonding wire.
In this embodiment, preferably, when N is 3, the first-stage amplification module 1 includes two pseudomodulation doped heterojunction field effect transistors with a die size of 8x75um, the second-stage amplification module 2 includes four-branch-die-size-8 x75um pseudomodulation doped heterojunction field effect transistors, and the third-stage amplification module 3 includes eight-branch-die-size-8 x75um pseudomodulation doped heterojunction field effect transistors. The first drain bias sub-network or the second drain bias sub-network of the field effect transistor of the first-stage amplification module 1 comprises an inter-stage matching circuit open-circuit short-stub microstrip line 203 and an inter-stage matching circuit second bypass capacitor 204 in the first inter-stage matching circuit 5, and the structure of the first drain bias sub-network or the second drain bias sub-network of the field effect transistor of the second-stage amplification module 2 can be obtained in the same way; as shown in fig. 4, the first drain bias sub-network or the second drain bias sub-network of the field effect transistor of the third-stage amplification module 3 includes an output matching circuit open-circuit short-stub microstrip line 306 and an output matching circuit bypass filter capacitor 307.
In this embodiment, preferably, as shown in fig. 4, the combining module in the output matching circuit 7 includes two 4-in-1-way combining circuits and a 2-in-one-way module, the two 4-in-1-way combining circuits are connected to two input ends of the 2-in-one-way module after being connected to a drain bias network, respectively, and an output end of the 2-in-one-way module is connected to the output pressure point 314; the four input ends of the 4-in-1-path combiner circuit are respectively connected with the output ends of the 4 amplifier modules of the third-stage amplification module 3, and the output end of the 4-in-1-path combiner circuit is also connected with a drain electrode biasing network.
In this embodiment, the rf signal enters the field effect transistor in the third stage amplification module 3 through the second interstage matching circuit 6 for amplification for three times, and is input to the output matching circuit 7 through the first transmission microstrip line 301 of the output matching circuit, where the rf signal is amplified and output by the field effect transistor in the amplification module 3; as shown in fig. 4, a 4-to-1 combiner circuit structure is formed by the 4 output matching circuit first transmission microstrip lines 301, the two output matching circuit second transmission microstrip lines 302, the two output matching circuit first bypass capacitors 303, the two output matching circuit third transmission microstrip lines 304, and the 1 output matching circuit fourth transmission microstrip line 305.
In this embodiment, preferably, as shown in fig. 4, the output matching circuit open stub microstrip line 306 is connected to the drain voltage node 308, a bonding wire is used to externally connect 6V voltage to provide drain voltage for the field effect transistor of the third-stage amplification module 3, and the output matching circuit bypasses the filter capacitor 307 to implement a filtering function; isolating the dc voltage to the output terminal by the output matching circuit isolation capacitor 309; the 2 output matching circuit fifth transmission microstrip lines 310, the 2 output matching circuit second bypass capacitors 311, the 2 output matching circuit sixth transmission microstrip lines 312, and the 1 output matching circuit seventh transmission microstrip line 313 form a 2-in-one module, the 2-in-one module forms a signal and transmits the signal to an output voltage point 314, a radio frequency signal is output, the output matching circuit further filters noise waves and nonlinear products in the signal, output matching is completed simultaneously, and good output voltage standing wave ratio VSWR2 performance is provided. VSWR represents the Voltage Standing wave ratio, Voltage Standard wave ratio.
In the present embodiment, the input matching circuit 4 and the inter-first-stage matching circuit 5 together perform the functions of providing the optimal input and output impedance and oscillation suppression for the field effect transistor of the first-stage amplification module 1, and ensure the gain and stability of the first-stage field effect transistor amplifier; the second-stage matching circuit 6 and the first-stage matching circuit 5 jointly provide the optimal input and output impedance and oscillation suppression of the field effect transistor of the second-stage amplification module 2, and the gain and stability of the field effect transistor amplifier of the second-stage amplification module 2 are ensured.
In the embodiment, the power amplification integrated circuit is formed by cascading three stages of amplification modules, field effect transistors at all stages are subjected to maximum output power matching, an interstage matching network is designed at the interstage, and an input/output port of the whole circuit system is matched with 50-ohm standard impedance, so that the power amplification integrated circuit has the characteristics of good overall linearity, in-band positive slope gain and good gain flatness; the grid bias network of each stage of field effect transistor provides grid voltage through the parallel resistor and the microstrip line, although certain network loss is increased, low-frequency oscillation of the amplifier is avoided, and high impedance is formed, so that clutter signals are prevented from entering to a great extent. The stability of the whole power integrated amplifying circuit is guaranteed; the amplifier interstage matching circuit is combined in a modularized mode, impedance characteristics are similar, impedance adjustment and matching debugging are facilitated, optimal impedance matching and filtering of each stage of amplifier are finally formed, and circuit performance is guaranteed. The input end of the input matching circuit 4 is used for being connected with an external radio frequency input port, and the linearity and the gain flatness of the amplifier are improved through a network structure similar to a 1-to-2 power divider; the output end of the output matching circuit 7 is used for being connected with an external radio frequency output port, and the linearity and the gain flatness of the amplifier are improved through a network structure similar to a 1-to-8 power divider.
In an application scenario of this embodiment, a 0.15um gallium arsenide process is adopted, and the power amplification integrated circuit is absolutely stable under each operating voltage, has an in-band gain positive slope gain, good gain flatness, and good linearity in a wide frequency band, and the actual measurement performance parameters of the power amplification integrated circuit are as follows: the optimal working frequency band is 27.5-30.5GHz, the gain is positive slope gain, the low-frequency gain is 17.5, the high-frequency gain is 18.5dB, and the gain flatness is less than +/-1 dB; the input voltage standing wave ratio and the output voltage standing wave ratio are both less than 2 dB; the output power of the 1dB compression point is 33dBm, and the additional efficiency under the output power is more than or equal to 18 percent. Test gain as shown in fig. 5, test results of the input voltage standing wave ratio VSWR1 and the output voltage standing wave ratio VSWR2 as shown in fig. 6, the test spurious signals are good without self-excitation, and as can be seen from fig. 5 and 6, the power amplification integrated circuit is good in performance.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A high-stability power amplification integrated circuit is characterized by comprising an input matching circuit, an N-stage amplification module and an output matching circuit which are cascaded, and also comprising a plurality of interstage matching power division modules arranged among the amplification modules at each stage;
the i-1 th stage amplifying module comprises a parallel 2i-1An amplifier, a parallel 2 is arranged between the i-1 st stage amplification module and the i-th stage amplification modulei-1Individual stage matching power dividing module, said 2i-12 of individual stage matching power division module and i-1 stage amplification modulei-1The amplifiers are in one-to-one correspondence, the output ends of the amplifiers of the i-1 th-stage amplification module are connected with the input ends of the corresponding inter-stage matching power dividing modules, the inter-stage matching power dividing modules divide a received signal into two parts and respectively output the two parts to the input ends of the two amplifiers in the i-th-stage amplification module, i and N are positive integers, and i is more than 1 and less than or equal to N;
the input matching circuit comprises a 1-path and 2-path power dividing unit and two input matching circuit isolation capacitors, wherein the input ends of the 1-path and 2-path power dividing unit are connected with an input voltage point, and the two output ends of the 1-path and 2-path power dividing unit are respectively connected with the input ends of two amplifiers of the first-stage amplification module through one input matching circuit isolation capacitor;
the output matching circuit comprises a 2-stage amplifier moduleNThe output signal of each amplifier is combined into a combining module of one path, and the output end of the combining module is connected with an output pressure point.
2. The high stability power amplifying integrated circuit of claim 1, wherein the amplifier is a field effect transistor having a source connected to ground, a gate as an input of the amplifier, and a drain as an output of the amplifier.
3. The high stability power amplifying integrated circuit of claim 2, wherein said field effect transistor is a pseudomodulation doped heterojunction field effect transistor.
4. The high stability power amplifying integrated circuit of claim 2, wherein a gate bias network is connected to the gate of each field effect transistor, the gate bias network comprising a gate bias resistor, a gate bias decoupling capacitor and a gate bias voltage node, a first terminal of the gate bias resistor being connected to the gate bias voltage node and a first terminal of the gate bias decoupling capacitor, respectively, a second terminal of the gate bias resistor being connected to the gate of the field effect transistor, and a second terminal of the gate bias decoupling capacitor being connected to ground.
5. The high stability power amplification integrated circuit of claim 2, wherein the inter-stage matching power division module comprises an inter-stage matching circuit first transmission microstrip line, an inter-stage matching circuit isolation capacitor, an inter-stage matching circuit second transmission microstrip line, two inter-stage matching circuit third transmission microstrip lines, two inter-stage matching circuit first bypass capacitors, two inter-stage matching circuit fourth transmission microstrip lines;
the first end of the first transmission microstrip line of the interstage matching circuit is connected with the drain electrode of a field effect tube of the preceding stage amplification module, the second end of the first transmission microstrip line of the interstage matching circuit is connected with the first end of the second transmission microstrip line of the interstage matching circuit through an interstage matching circuit isolation capacitor, the second end of the second transmission microstrip line of the interstage matching circuit is connected with the first ends of the third transmission microstrip lines of the two interstage matching circuits respectively, the second end of each third transmission microstrip line of the interstage matching circuit is connected with the first end of a first bypass capacitor of the interstage matching circuit and the first end of a fourth transmission microstrip line of the interstage matching circuit respectively, the second end of each fourth transmission microstrip line of the interstage matching circuit is connected with the gate electrode of a field effect tube of the subsequent stage amplification module, and the second end of the first bypass capacitor of the interstage matching circuit is connected with the ground.
6. The high stability power amplification integrated circuit of claim 5, wherein the inter-stage matching power division module further comprises a drain bias network, the drain bias network comprises a first drain bias sub-network and a second drain bias sub-network with the same structure, and the first drain bias sub-network and the second drain bias sub-network are symmetrically connected to the second end of the first transmission microstrip line of the inter-stage matching circuit;
the first drain bias sub-network or the second drain bias sub-network comprises an interstage matching circuit open-circuit short-stub microstrip line, an interstage matching circuit second bypass capacitor and a drain bias voltage point, a first end of the interstage matching circuit open-circuit short-stub microstrip line is connected with a second end of the interstage matching circuit first transmission microstrip line, a second end of the interstage matching circuit open-circuit short-stub microstrip line is respectively connected with a first end of the interstage matching circuit second bypass capacitor and the drain bias voltage point, and a second end of the interstage matching circuit second bypass capacitor is connected with the ground.
7. The high stability power amplification integrated circuit of claim 1, wherein the 1-branch 2-path power splitting unit comprises an input matching circuit first transmission microstrip line and two input matching circuit second transmission microstrip lines;
one end of the first transmission microstrip line of the input matching circuit is connected with the input pressure point, the other end of the first transmission microstrip line of the input matching circuit is respectively connected with the first ends of the second transmission microstrip lines of the two input matching circuits, the second ends of the second transmission microstrip lines of the two input matching circuits are respectively connected with the first ends of the isolation capacitors of the two input matching circuits, and the second ends of the isolation capacitors of the input matching circuits are connected with the input end of the amplifier of the first-stage amplification module.
8. The high stability power amplifier ic of claim 1, wherein the input matching circuit further comprises two impedance adjusting networks, the impedance adjusting networks include an input matching circuit open-circuited short-stub microstrip and an adjusting resistor, a first end of the adjusting resistor is grounded, a second end of the adjusting resistor is connected to a first end of the input matching circuit open-circuited short-stub microstrip, and a second end of the input matching circuit open-circuited short-stub microstrip is connected to a first end of an input matching circuit isolation capacitor and an output of the 1-in-2 power dividing unit, respectively.
9. The high stability power amplifier integrated circuit as claimed in one of claims 1 to 8, wherein N is 3, and comprises a first stage amplifier module, a second stage amplifier module and a third stage amplifier module, wherein the first stage amplifier module comprises two amplifiers, the second stage amplifier module comprises 4 amplifiers, the third stage amplifier module comprises 8 amplifiers, 2 parallel stage matching power dividing modules are arranged between the first stage amplifier module and the second stage amplifier module, and 4 parallel stage matching power dividing modules are arranged between the first stage amplifier module and the second stage amplifier module.
10. The high stability power amplifier integrated circuit of claim 9, wherein the combining module comprises two 4-in-1 combining circuits and a 2-in-1 combining module, the two 4-in-1 combining circuits are respectively connected to a drain bias network and then connected to two input terminals of the 2-in-2 combining module, and an output terminal of the 2-in-2 combining module is connected to the output voltage point; four input ends of the 4-in-1-path combining circuit are respectively connected with output ends of 4 amplifier modules of the third-stage amplification module, and the output end of the 4-in-1-path combining circuit is also connected with a drain electrode biasing network.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023065690A1 (en) * | 2021-10-20 | 2023-04-27 | 河北新华北集成电路有限公司 | Ka-band gan mmic power amplifier circuit and amplifier |
| CN116915186A (en) * | 2023-06-09 | 2023-10-20 | 北京无线电测量研究所 | High-frequency high-power amplifier circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023065690A1 (en) * | 2021-10-20 | 2023-04-27 | 河北新华北集成电路有限公司 | Ka-band gan mmic power amplifier circuit and amplifier |
| CN116915186A (en) * | 2023-06-09 | 2023-10-20 | 北京无线电测量研究所 | High-frequency high-power amplifier circuit |
| CN116915186B (en) * | 2023-06-09 | 2024-03-08 | 北京无线电测量研究所 | High-frequency high-power amplifier circuit |
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