CN214480483U - High-efficiency power amplifier circuit topology structure with harmonic matching structure - Google Patents
High-efficiency power amplifier circuit topology structure with harmonic matching structure Download PDFInfo
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- CN214480483U CN214480483U CN202120415185.8U CN202120415185U CN214480483U CN 214480483 U CN214480483 U CN 214480483U CN 202120415185 U CN202120415185 U CN 202120415185U CN 214480483 U CN214480483 U CN 214480483U
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Abstract
The utility model discloses a take high impedance transformation ratio of harmonic matching structure, extremely low last stage matching loss's high efficiency power amplifier circuit topological structure, including the matching unit that connects gradually one, first order field effect transistor Q1, matching unit two, second level field effect transistor Q2, matching unit three, third level field effect transistor Q3, matching unit four. The utility model discloses topological structure adopts 3 grades of enlargies, and the stage grade utilizes high impedance transformation ratio circuit topology to realize exceeding 1: 4's promotion ratio between the senior, and the final stage utilizes ultralow loss circuit topological structure to realize the terminal stage matching loss of utmost point low (theoretical minimum matching loss is less than 0.35dB, and actual final stage matching loss is less than 0.45dB, compares and reduces more than 0.2dB in traditional matching structure loss), under the prerequisite that satisfies power output, can realize super high efficiency performance.
Description
Technical Field
The utility model relates to a take high impedance transformation ratio of harmonic matching structure, extremely low high efficiency power amplifier circuit topological structure of final stage matching loss belongs to high efficiency power amplifier technical field, especially relates to a K-Ka wave band high efficiency GaN power amplifier.
Background
The microwave millimeter wave power amplifier is one of amplifier circuits and is a prominent importance in the whole microwave millimeter wave electronic circuit. With the continuous development and progress of the society and the national economy of China, the solid-state microwave millimeter wave power device has very wide application prospects, such as a microwave millimeter wave power amplifier with high performance cannot be opened in the development direction of the wireless communication of the current stage of fire and heat, such as an automobile anti-collision radar, a test surveying and mapping radar, unmanned driving, 5G mobile communication, satellite internet and the like.
In an MMIC power amplifier, the nature of impedance transformation is a matching network used to achieve a specific performance index of the power amplifier, most commonly maximum transmission power or maximum transmission efficiency, and the best matching effect is often achieved by a combination of capacitors, inductors, and resistors. By designing a high impedance transformation ratio matching circuit network between the stages of the amplifier, the power push ratio between the front stage and the rear stage can be improved, the stage matching loss can be reduced, and meanwhile, the topology of the matching circuit at the final stage is controlled to realize the lowest output matching loss, so that the efficiency and other performances of the amplifier are effectively improved. In the conventional circuit matching topology structure, a topology structure which can meet the high impedance transformation ratio and can effectively realize the lowest final stage matching loss is not found, so that a simple and effective high-efficiency power amplifier circuit topology structure with the high impedance transformation ratio and the low matching loss is required to be designed.
The power amplifier chip is designed by applying the circuit topological structure, so that the impedance transformation ratio can be effectively improved, the power push ratio between the front stage and the rear stage is improved, the interstage matching loss is reduced, the lowest output matching loss is realized, and the power amplifier chip plays a critical special role in improving indexes such as the efficiency of the amplifier chip.
SUMMERY OF THE UTILITY MODEL
The utility model provides a take high impedance transformation ratio of harmonic matching structure, extremely low last stage matching loss's high efficiency power amplifier circuit, the purpose lies in realizing K-Ka wave band narrowband, medium power (2W-6W), undercurrent, high efficiency GaN amplifier index, is particularly useful for the limited application scene of energy supply such as on-vehicle, machine carries, star carries and uses.
The technical solution of the utility model is as follows:
the high-efficiency power amplifier circuit topological structure with the harmonic matching structure comprises a first matching unit, a second matching unit, a third matching unit, a fourth matching unit, a first-stage field effect transistor Q1, a second-stage field effect transistor Q2, a third-stage field effect transistor Q3, a gate bias voltage VG and a drain bias voltage VD, wherein a signal output end of the first matching unit is connected with a gate of the first-stage field effect transistor Q1, a drain of the first-stage field effect transistor Q1 is connected with a signal input end of the second matching unit, a signal output end of the second matching unit is connected with a gate of the second-stage field effect transistor Q2, a drain of the second-stage field effect transistor Q2 is connected with a signal input end of the third matching unit, a signal output end of the third matching unit is connected with a gate of the third-stage field effect transistor Q3, and a drain of the third-stage field effect transistor Q3 is connected with a signal input end of the fourth matching unit; the sources of the first stage field effect transistor Q1, the second stage field effect transistor Q2 and the third stage field effect transistor Q3 are all grounded; the grid of the first stage field effect transistor Q1 is connected with a grid bias voltage VG through a matching unit; the grid of the second stage field effect transistor Q2 is connected with a grid bias voltage VG through a second matching unit; the gate of the third stage field effect transistor Q3 is connected with a gate bias voltage VG through a matching unit three; the drain electrode of the first-stage field effect transistor Q1 is connected with a drain electrode bias voltage VD through a second matching unit; the drain electrode of the second stage field effect transistor Q2 is connected with a drain electrode bias voltage VD through a matching unit III; the drain of the third stage field effect transistor Q3 is connected to a drain bias voltage VD via a matching unit four.
The matching unit I comprises a TL1_1 microstrip line, a capacitor C1_1, a microstrip line TL2_1, a microstrip line TL3_1 and a microstrip line TL4_1 which are sequentially connected in series; a signal input end of the matching unit is connected with the TL1_1 microstrip line; the microstrip line TL5_1 is connected in parallel between the microstrip line TL1_1 and the capacitor C1_ 1; the capacitor C2_1 is connected in parallel between the microstrip line TL2_1 and the microstrip line TL3_ 1; the microstrip line TL6_1, the resistor R1_1 and the capacitor C3_1 form a series branch which is connected in parallel between the microstrip line TL3_1 and the microstrip line TL4_ 1; the other end of the microstrip line TL4_1 is connected with the gate of a first-stage field effect transistor Q1; the common terminal of the resistor R1_1 and the capacitor C3_1 is connected to a gate bias voltage VG.
The matching unit II comprises a microstrip line TL1_2, a capacitor C1_2, a microstrip line TL2_2, a microstrip line TL3_2 and a microstrip line TL4_2 which are sequentially connected in series; the microstrip line TL5_2, the resistor R1_2 and the capacitor C3_2 form a series branch which is connected between the microstrip line TL1_2 and the capacitor C1_2 in parallel; the capacitor C2_2 is connected in parallel between the microstrip line TL2_2 and the microstrip line TL3_ 2; the microstrip line TL6_2, the resistor R2_2 and the capacitor C4_2 form a series branch which is connected in parallel with the microstrip line TL3_2 and the microstrip line TL4_ 2; the other end of the microstrip line TL1_2 is connected with the drain electrode of the first-stage field effect transistor Q1; the other end of the microstrip line TL4_2 is connected with the gate of a second-stage field effect transistor Q2; the common end of the resistor R1_2 and the capacitor C3_2 is connected with the drain bias voltage VD, and the common end of the resistor R2_2 and the capacitor C4_2 is connected with the gate bias voltage VG.
The matching unit III comprises a microstrip line TL1_3, a capacitor C1_3, a capacitor C2_3, a microstrip line TL2_3, a microstrip line TL3_3, a microstrip line TL4_3 and a microstrip line TL7_3 which are sequentially connected in series and connected with a tube cell gate of a third-stage field effect transistor Q3; the microstrip line TL1_3, the capacitor C1_3, the capacitor C2_3, the microstrip line TL2_3, the microstrip line TL3_3, the microstrip line TL4_3 'and the microstrip line TL7_3' which are sequentially connected in series are connected with the grid electrode of the other tube cell of the third-stage field effect transistor Q3; the microstrip line TL5_3 and the capacitor C4_3 form a series branch which is connected between the microstrip line TL1_3 and the capacitor C1_3 in parallel; the microstrip line TL6_3 is connected in parallel between the capacitor C1_3 and the capacitor C2_ 3; the capacitor C3_3 is connected in parallel between the microstrip line TL2_3 and the microstrip line TL3_ 3; the microstrip line TL9_3 and the capacitor C6_3 form a series branch which is connected between the microstrip line TL4_3 and the microstrip line TL7_3 in parallel; the microstrip line TL9_3 'and the capacitor C6_3' form a series branch which is connected in parallel between the microstrip line TL4_3 'and the microstrip line TL7_ 3'; the microstrip line TL8_3, the resistor R1_3 and the capacitor C5_3 form a series branch which is connected in parallel between the microstrip line TL7_3 and the grid electrode of the field effect transistor Q3; the microstrip line TL8_3', the resistor R1_3' and the capacitor C5_3 'form another series branch which is connected in parallel between the microstrip line TL7_3' and the grid of the field effect transistor Q3; the other end of the microstrip line TL1_3 is connected with the drain electrode of a second-stage field effect transistor Q2; the other ends of the microstrip lines TL7_3 and TL7_3' are respectively connected with the gates of two tube cells of the third-stage field effect transistor Q3; microstrip line TL4_3, microstrip line TL7_3, microstrip line TL8_3, microstrip line TL9_3, resistor R1_3, capacitor C5_3 and capacitor C6_3 are equivalent mirror images of microstrip line TL4_3', microstrip line TL7_3' microstrip line TL8_3', microstrip line TL9_3', resistor R1_3', capacitor C5_3' and capacitor C6_3 '; the common end of the microstrip line TL5_3 and the capacitor C4_3 is connected to the drain bias voltage VD, the common end of the capacitor C5_3 of the resistor R1_3 is connected to the gate bias voltage VG, and the common end of the capacitor C5_3 'of the resistor R1_3' is connected to the gate bias voltage VG.
The fourth matching unit comprises a tube cell of a third-stage field effect transistor Q3, which is sequentially connected with microstrip lines TL1_4, TL2_4, TL3_4, TL4_4 and a capacitor C2_4 in series; the other tube cell of the third-stage field effect transistor Q3 is sequentially connected with microstrip lines TL1_4', TL2_4', TL3_4, TL4_4 and a capacitor C2_4 in series; the microstrip line TL5_4 and the capacitor C3_4 form a series branch which is connected between the microstrip line TL1_4 and the microstrip line TL2_4 in parallel; the microstrip line TL5_4 'and the capacitor C3_4' form a series branch which is connected in parallel between the microstrip line TL1_4 'and the TL2_ 4'; the capacitor C1_4 is connected in parallel between the microstrip lines TL3_4 and TL4_ 4; the microstrip line TL1_4 and the microstrip line TL1_4' are connected with the drains of the two tube cells of the third-stage field effect transistor Q3; the capacitor C2_4 is connected with the output end; microstrip lines TL1_4, L5_4 and a capacitor C3_4 are in equal value mirror images with microstrip lines TL1_4', L5_4' and a capacitor C3_4 '; the common end of the microstrip line TL5_4 and the capacitor C3_4 is connected with the drain bias voltage VD, and the common ends of the microstrip line TL5_4 'and the capacitor C3_4' are connected with the drain bias voltage VD.
The utility model has the advantages that:
1. the matching unit of the utility model has a simple structure, is easy to realize perfect impedance matching in the microwave and millimeter wave frequency band, has extremely small matching loss (the theoretical minimum matching loss is less than 0.35dB, the actual final-stage matching loss is less than 0.45dB, and the loss is reduced by more than 0.2dB compared with the traditional matching structure), and can effectively improve the efficiency of the power amplifier;
2. the utility model discloses the topological structure of matching unit three can realize that the high-power promotion of front and back level is than (the promotion is greater than 4: 1) impedance transformation, reaches less interstage matching loss, and in addition, more crucial and important, matching unit three and field effect transistor Q3's grid input end junction contains the resonance of a parallelly connected LC (be TL9_3 and C6_3, TL9_3' and C6_3 ') series resonance branch road in 2f 0I.e. twice the central operating frequencyf 0The energy of the second harmonic wave can be effectively restrained by the resonance unit and amplified by the field effect transistor Q3, so that the power amplifier direct current power consumption is reduced, and the efficiency performance of the power amplifier can be greatly improved.
3. The utility model discloses a tertiary amplification, matching unit four through having minimum matching loss and matching unit three that has the second harmonic control structure can realize high efficiency performance under the requirement that satisfies power amplifier output.
Drawings
Fig. 1 is a signal path structure diagram of the present invention.
Fig. 2 is a schematic diagram of the structure of the matching unit of the present invention.
Fig. 3 is a schematic structural diagram of the matching unit of the present invention.
Fig. 4 is a schematic diagram of the matching unit of the present invention.
Fig. 5 is a schematic diagram of the matching unit of the present invention.
Fig. 6 in the third matching unit of the present invention, LC (i.e. TL9_3 and C6_3, TL9_3 'and C6_ 3') in series resonance branch resonant frequency 2 is connected in parallelf 0Position in the Smith chart.
Fig. 7 is the theoretical minimum matching loss curve and the actual matching loss curve of the four-topology structure of the matching unit of the present invention.
Fig. 8 is a power curve case of the present invention.
Fig. 9 illustrates an efficiency curve case of the present invention.
In the figure all TL are microstrip lines, all C are capacitors, all Q are field effect transistors, all R are resistors, VD is drain bias voltage, VG is gate bias.
Detailed Description
The technical solution of the present invention will be further explained with reference to the accompanying drawings.
Referring to fig. 1, a high-efficiency power amplifier circuit topology structure with a harmonic matching structure and high impedance transformation ratio and extremely low final-stage matching loss comprises a first matching unit, a second matching unit, a third matching unit and a fourth matching unit; the amplifier circuit is characterized in that an input signal Pin sequentially passes through a first matching unit, a first-stage field effect transistor Q1, a second matching unit, a second-stage field effect transistor Q2, a third matching unit, a third-stage field effect transistor Q3 and a fourth matching unit to be amplified and output; the sources of the first stage field effect transistor Q1, the second stage field effect transistor Q2 and the third stage field effect transistor Q3 are all grounded; the grid of the first stage field effect transistor Q1 is connected with VG through a first matching unit; the grid of the second stage field effect transistor Q2 is connected with VG through a second matching unit; the gate of the third stage field effect transistor Q3 is connected with VG through a third matching unit; the drain electrode of the first-stage field effect transistor Q1 is connected with VD through a second matching unit; the drain electrode of the second stage field effect transistor Q2 is connected with VD through a matching unit III; the drain electrode of the third stage field effect transistor Q3 is connected with VD through a matching unit IV
Microstrip lines, capacitors and resistors in the first matching unit, the second matching unit, the third matching unit and the fourth matching unit form a series or parallel relation; each matching unit has different structures, and the impedance matching between the input and the output and each stage of amplifier can be realized by adjusting the length and the width of each section of microstrip line, the size of a capacitor and the size of a resistor, so that the standing wave of the port is reduced.
Referring to fig. 2, the first matching unit includes a microstrip line TL1_1, a capacitor C1_1, a microstrip line TL2_1, a microstrip line TL3_1, and a microstrip line TL4_1, which are connected in series in sequence; the microstrip line TL5_1 is connected in parallel between the microstrip line TL1_1 and the capacitor C1_ 1; the capacitor C2_1 is connected in parallel between the microstrip line TL2_1 and the microstrip line TL3_ 1; the microstrip line TL6_1, the resistor R1_1 and the capacitor C3_1 form a series branch which is connected in parallel between the microstrip line TL3_1 and the microstrip line TL4_ 1; the other end of the microstrip line TL4_1 is connected to the gate of the first stage field effect transistor Q1. The gate bias voltage VG is connected into a matching network between the resistor R1_1 and the capacitor C3_1, and the first matching unit is used for matching the source impedance (50 ohms) of the input port of the system to the input impedance of the first-stage field effect transistor Q1 and isolating a direct current bias signal from the radio frequency signal input port of the system.
Referring to fig. 3, the second matching unit includes a microstrip line TL1_2, a capacitor C1_2, a microstrip line TL2_2, a microstrip line TL3_2, and a microstrip line TL4_2 connected in series in sequence; the microstrip line TL5_2, the resistor R1_2 and the capacitor C3_2 form a series branch which is connected between the microstrip line TL1_2 and the capacitor C1_2 in parallel; the capacitor C2_2 is connected in parallel between the microstrip line TL2_2 and the microstrip line TL3_ 2; the microstrip line TL6_2, the resistor R2_2 and the capacitor C4_2 form a series branch which is connected in parallel with the microstrip line TL3_2 and the microstrip line TL4_ 2; the other end of the microstrip line TL1_2 is connected with the drain electrode of the first-stage field effect transistor Q1; the other end of the microstrip line TL4_2 is connected with the gate of a second-stage field effect transistor Q2; the second matching unit is used for matching the first stage field effect transistor Q1 with the second stage field effect transistor Q2, controlling the gain and the flatness of the first stage amplifying unit, enhancing the stability factor of the system and improving the standing wave ratio of the input port.
Referring to fig. 4, the third matching unit includes a microstrip line TL1_3, a capacitor C1_3, a capacitor C2_3, a microstrip line TL2_3, a microstrip line TL3_3, a microstrip line TL4_3, and a microstrip line TL7_3, which are connected in series in sequence, and is connected to a tube cell gate of the third stage field effect transistor Q3; the microstrip line TL1_3, the capacitor C1_3, the capacitor C2_3, the microstrip line TL2_3, the microstrip line TL3_3, the microstrip line TL4_3 'and the microstrip line TL7_3' which are sequentially connected in series are connected with the grid electrode of the other tube cell of the third-stage field effect transistor Q3; the microstrip line TL5_3 and the capacitor C4_3 form a series branch which is connected between the microstrip line TL1_3 and the capacitor C1_3 in parallel; the microstrip line TL6_3 is connected in parallel between the capacitor C1_3 and the capacitor C2_ 3; the capacitor C3_3 is connected in parallel between the microstrip line TL2_3 and the microstrip line TL3_ 3; the microstrip line TL9_3 and the capacitor C6_3 form a series branch which is connected between the microstrip line TL4_3 and the microstrip line TL7_3 in parallel;the microstrip line TL9_3 'and the capacitor C6_3' form a series branch which is connected in parallel between the microstrip line TL4_3 'and the microstrip line TL7_ 3'; the microstrip line TL8_3, the resistor R1_3 and the capacitor C5_3 form a series branch which is connected in parallel between the microstrip line TL7_3 and the grid electrode of the field effect transistor Q3; the microstrip line TL8_3', the resistor R1_3' and the capacitor C5_3 'form another series branch which is connected in parallel between the microstrip line TL7_3' and the grid of the field effect transistor Q3; the other end of the microstrip line TL1_3 is connected with the drain electrode of a second-stage field effect transistor Q2; the other ends of the microstrip lines TL7_3 and TL7_3' are respectively connected with the gates of two tube cells of the third-stage field effect transistor Q3; the microstrip line TL4_3, the microstrip line TL7_3, the microstrip line TL8_3, the microstrip line TL9_3, the resistor R1_3, the capacitor C5_3 and the capacitor C6_3 are equivalent mirror images of the microstrip line TL4_3', the microstrip line TL7_3', the microstrip line TL8_3', the microstrip line TL9_3', the resistor R1_3', the capacitor C5_3' and the capacitor C6_3 '. For the power amplifier, the working state of the last-stage die has the greatest influence on the performance of the device, so the matching effect of the third matching unit plays a crucial role on the performance of the power amplifier, the third topological structure of the matching unit in this embodiment is to realize the matching of the optimal efficiency load impedance point at the output end of the second-stage field-effect transistor Q2 to the optimal source impedance point at the input end of the third-stage field-effect transistor Q3, and ensure that the output power of the second-stage field-effect transistor Q2 after being matched by the third matching unit is enough to drive the third-stage field-effect transistor Q3 to work in a saturated state under the condition of a front-stage power push ratio of 1:4, and meanwhile, the matching loss of the third matching unit can be controlled in a very small range. Meanwhile, a parallel LC (namely TL9_3 and C6_3, TL9_3 'and C6_ 3') series resonance branch is introduced at the grid input end of the final-stage die and resonates at 2f 0I.e. twice the central operating frequencyf 0The resonant unit can effectively restrain the energy of the second harmonic and amplify the energy by the final-stage field effect transistor Q3, thereby reducing the direct current power consumption of the power amplifier and greatly improving the efficiency index of the power amplifier.
Referring to fig. 5, the fourth matching unit includes a cell of the third stage field effect transistor Q3 serially connected to microstrip lines TL1_4, TL2_4, TL3_4, TL4_4 and a capacitor C2_4 in sequence; the other tube cell of the third-stage field effect transistor Q3 is sequentially connected with microstrip lines TL1_4', TL2_4', TL3_4, TL4_4 and a capacitor C2_4 in series; the microstrip line TL5_4 and the capacitor C3_4 form a series branch which is connected between the microstrip line TL1_4 and the microstrip line TL2_4 in parallel; the microstrip line TL5_4 'and the capacitor C3_4' form a series branch which is connected in parallel between the microstrip line TL1_4 'and the TL2_ 4'; the capacitor C1_4 is connected in parallel between the microstrip lines TL3_4 and TL4_ 4; the microstrip line TL1_4 and the microstrip line TL1_4' are connected with the drains of the two tube cells of the third-stage field effect transistor Q3; the capacitor C2_4 is connected with the output end; the microstrip lines TL1_4, L5_4 and the capacitor C3_4 are equivalent mirror images of the microstrip lines TL1_4', L5_4' and the capacitor C3_4 '. And the matching unit IV is used for realizing the matching from the optimal efficiency impedance point of the output end of the third-stage field effect transistor Q3 to the load impedance (50 ohms) by using the simplest matching circuit topological structure, achieving the minimum matching loss, realizing the design target of higher efficiency and controlling the standing-wave ratio of the output port.
Compare 6-9 in the attached drawing, the utility model discloses four simple structure of matching unit easily realizes the impedance perfect match at the microwave millimeter wave frequency channel, has minimum matching loss simultaneously (theoretical minimum matching loss is less than 0.35dB, and actual final stage matching loss is less than 0.45dB, compares and reduces more than 0.2dB in traditional matching structure loss), can effectively promote power amplifier efficiency. The utility model discloses the topological structure of matching unit three can realize that the high-power promotion of front and back level is than (the promotion is greater than 4: 1) impedance transformation, reaches less interstage matching loss, and in addition, more crucial and important, matching unit three and field effect transistor Q3's grid input end junction contains the resonance of a parallelly connected LC (be TL9_3 and C6_3, TL9_3' and C6_3 ') series resonance branch road in 2f 0I.e. twice the central operating frequencyf 0The energy of the second harmonic wave can be effectively restrained by the resonance unit and amplified by the field effect transistor Q3, so that the power amplifier direct current power consumption is reduced, and the efficiency performance of the power amplifier can be greatly improved.
Claims (5)
1. The high-efficiency power amplifier circuit topology structure with the harmonic matching structure is characterized by comprising a first matching unit, a second matching unit, a third matching unit, a fourth matching unit, a first stage field effect transistor (Q1), a second stage field effect transistor (Q2), a third stage field effect transistor (Q3), a grid bias Voltage (VG) and a drain bias Voltage (VD), the first signal output end of the matching unit is connected with the grid of a first-stage field effect transistor (Q1), the drain of the first-stage field effect transistor (Q1) is connected with the second signal input end of the matching unit, the second signal output end of the matching unit is connected with the grid of a second-stage field effect transistor (Q2), the drain of the second-stage field effect transistor (Q2) is connected with the third signal input end of the matching unit, the third signal output end of the matching unit is connected with the grid of a third-stage field effect transistor (Q3), and the drain of the third-stage field effect transistor (Q3) is connected with the fourth signal input end of the matching unit; the sources of the first stage field effect transistor (Q1), the second stage field effect transistor (Q2) and the third stage field effect transistor (Q3) are all grounded; the grid of the first stage field effect transistor (Q1) is connected with a grid bias Voltage (VG) through a matching unit; the grid of the second stage field effect transistor (Q2) is connected with a grid bias Voltage (VG) through a second matching unit; the grid of the third stage field effect transistor (Q3) is connected with a grid bias Voltage (VG) through a matching unit III; the drain electrode of the first stage field effect transistor (Q1) is connected with a drain electrode bias Voltage (VD) through a second matching unit; the drain electrode of the second stage field effect transistor (Q2) is connected with a drain electrode bias Voltage (VD) through a matching unit III; the drain of the third stage field effect transistor (Q3) is connected to a drain bias Voltage (VD) via a matching unit four.
2. The high efficiency power amplifier circuit topology with the harmonic matching structure of claim 1, wherein the matching unit one comprises a TL1_1 microstrip line, a C1_1 capacitor, a TL2_1 microstrip line, a TL3_1 microstrip line and a TL4_1 microstrip line connected in series in sequence; a signal input end of the matching unit is connected with the TL1_1 microstrip line; the TL5_1 microstrip line is connected in parallel between the TL1_1 microstrip line and the C1_1 capacitor; the C2_1 capacitor is connected in parallel between the TL2_1 microstrip line and the TL3_1 microstrip line; the TL6_1 microstrip line, the R1_1 resistor and the C3_1 capacitor form a series branch which is connected between the TL3_1 microstrip line and the TL4_1 microstrip line in parallel; the other end of the TL4_1 microstrip line is connected with the grid electrode of a first-stage field effect transistor (Q1); the common terminal of the R1_1 resistor and the C3_1 capacitor is connected to a gate bias Voltage (VG).
3. The high efficiency power amplifier circuit topology with the harmonic matching structure of claim 1, wherein the matching unit two comprises TL1_2 microstrip line, C1_2 capacitor, TL2_2 microstrip line, TL3_2 microstrip line, TL4_2 microstrip line connected in series in sequence; the TL5_2 microstrip line, the R1_2 resistor and the C3_2 capacitor form a series branch which is connected between the TL1_2 microstrip line and the C1_2 capacitor in parallel; the C2_2 capacitor is connected in parallel between the TL2_2 microstrip line and the TL3_2 microstrip line; the TL6_2 microstrip line, the R2_2 resistor and the C4_2 capacitor form a series branch which is connected in parallel with the TL3_2 microstrip line and the TL4_2 microstrip line; the other end of the TL1_2 microstrip line is connected with the drain electrode of a first-stage field effect transistor (Q1); the other end of the TL4_2 microstrip line is connected with the grid electrode of a second-stage field effect transistor (Q2); the common end of the R1_2 resistor and the C3_2 capacitor is connected with a drain bias Voltage (VD), and the common end of the R2_2 resistor and the C4_2 capacitor is connected with a gate bias Voltage (VG).
4. The high efficiency power amplifier circuit topology with the harmonic matching structure as claimed in claim 1, wherein the matching unit three comprises TL1_3 microstrip line, C1_3 capacitor, C2_3 capacitor, TL2_3 microstrip line, TL3_3 microstrip line, TL4_3 microstrip line, TL7_3 microstrip line connected in series in turn and connected with one tube cell gate of the third stage field effect transistor (Q3); the TL1_3 microstrip line, the C1_3 capacitor, the C2_3 capacitor, the TL2_3 microstrip line, the TL3_3 microstrip line, the TL4_3 'microstrip line and the TL7_3' microstrip line which are sequentially connected in series are connected with the grid electrode of the other tube cell of the third-stage field effect transistor (Q3); the TL5_3 microstrip line and the C4_3 capacitor form a series branch which is connected between the TL1_3 microstrip line and the C1_3 capacitor in parallel; the TL6_3 microstrip line is connected in parallel between the C1_3 capacitor and the C2_3 capacitor; the C3_3 capacitor is connected in parallel between the TL2_3 microstrip line and the TL3_3 microstrip line; the TL9_3 microstrip line and the C6_3 capacitor form a series branch which is connected between the TL4_3 microstrip line and the TL7_3 microstrip line in parallel; the TL9_3 'microstrip line and the C6_3' capacitor form a series branch which is connected in parallel between the TL4_3 'microstrip line and the TL7_3' microstrip line; the TL8_3 microstrip line, the R1_3 resistor and the C5_3 capacitor form a series branch which is connected between the TL7_3 microstrip line and the gate of the field effect transistor Q3 in parallel; the TL8_3 'microstrip line, the R1_3' resistor and the C5_3 'capacitor form another series branch which is connected between the TL7_3' microstrip line and the gate of the field effect transistor Q3 in parallel; the other end of the TL1_3 microstrip line is connected with the drain electrode of a second-stage field effect transistor (Q2); the other ends of the TL7_3 microstrip line and the TL7_3' microstrip line are respectively connected with the gates of two tube cells of a third-stage field effect transistor (Q3); a TL4_3 microstrip line, a TL7_3 microstrip line, a TL8_3 microstrip line, a TL9_3 microstrip line, an R1_3 resistor, a C5_3 capacitor and a C6_3 capacitor are equivalent mirror images of a TL4_3' microstrip line, a TL7_3' microstrip line, a TL8_3' microstrip line, a TL9_3' microstrip line, an R1_3' resistor, a C5_3' capacitor and a C6_3' capacitor; the common end of the TL5_3 microstrip line and the C4_3 capacitor is connected with a drain bias Voltage (VD), the common end of the R1_3 resistor and the C5_3 capacitor is connected with a gate bias Voltage (VG), and the common end of the R1_3 'resistor and the C5_3' capacitor is connected with the gate bias Voltage (VG).
5. The high efficiency power amplifier circuit topology with the harmonic matching structure as claimed in claim 1, wherein the matching unit four comprises a transistor cell of a third stage field effect transistor (Q3) serially connected in sequence with a TL1_4 microstrip line, a TL2_4 microstrip line, a TL3_4 microstrip line, a TL4_4 microstrip line and a C2_4 capacitor; the other tube cell of the third-stage field effect transistor (Q3) is sequentially connected with a TL1_4 'microstrip line, a TL2_4' microstrip line, a TL3_4 microstrip line, a TL4_4 microstrip line and a C2_4 capacitor in series; the TL5_4 microstrip line and the C3_4 capacitor form a series branch which is connected between the TL1_4 microstrip line and the TL2_4 microstrip line in parallel; the TL5_4 'microstrip line and the C3_4' capacitor form a series branch which is connected in parallel between the TL1_4 'microstrip line and the TL2_4' microstrip line; the C1_4 capacitor is connected in parallel between the TL3_4 microstrip line and the TL4_4 microstrip line; the TL1_4 microstrip line and the TL1_4' microstrip line are connected with the drains of the two tube cells of the third-stage field effect transistor (Q3); the C2_4 capacitor is connected with the output end; equivalent mirror images of TL1_4 microstrip line, TL5_4 microstrip line, C3_4 capacitor, TL1_4' microstrip line, TL5_4' microstrip line and C3_4' capacitor; the common end of the TL5_4 microstrip line and the C3_4 capacitor is connected with a drain bias Voltage (VD), and the common end of the TL5_4 'microstrip line and the C3_4' capacitor is connected with the drain bias Voltage (VD).
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| CN112994627A (en) * | 2021-02-25 | 2021-06-18 | 中电国基南方集团有限公司 | High-efficiency power amplifier circuit topological structure with high impedance transformation ratio and low matching loss |
| CN112994619A (en) * | 2021-02-25 | 2021-06-18 | 中电国基南方集团有限公司 | High-efficiency power amplifier circuit topology structure with harmonic matching structure |
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| CN112994627A (en) * | 2021-02-25 | 2021-06-18 | 中电国基南方集团有限公司 | High-efficiency power amplifier circuit topological structure with high impedance transformation ratio and low matching loss |
| CN112994619A (en) * | 2021-02-25 | 2021-06-18 | 中电国基南方集团有限公司 | High-efficiency power amplifier circuit topology structure with harmonic matching structure |
| CN112994627B (en) * | 2021-02-25 | 2024-02-20 | 中电国基南方集团有限公司 | High-efficiency power amplifier circuit topology structure with high impedance transformation ratio and low matching loss |
| CN112994619B (en) * | 2021-02-25 | 2024-02-20 | 中电国基南方集团有限公司 | High-efficiency power amplifier circuit topology structure with harmonic matching structure |
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