CN112817901B

CN112817901B - Method for realizing single-board ultra-wideband and multi-board multipath synchronous transmission based on FPGA

Info

Publication number: CN112817901B
Application number: CN202110120085.7A
Authority: CN
Inventors: 贾云飞; 石林艳; 周鹤; 陈研; 霍泊帆; 曹志华
Original assignee: Shanghai Institute Of Microwave Equipment 51st Research Institute Of China Electronics Technology Group Corp
Current assignee: Shanghai Institute Of Microwave Equipment 51st Research Institute Of China Electronics Technology Group Corp
Priority date: 2021-01-28
Filing date: 2021-01-28
Publication date: 2022-10-18
Anticipated expiration: 2041-01-28
Also published as: CN112817901A

Abstract

The invention provides a method for realizing single-board ultra wide band and multi-board multi-path synchronous transmission based on FPGA, which comprises a main control module and an auxiliary module; the main control module comprises a PCB (printed circuit board), and the PCB comprises a high-speed acquisition board, a signal processing board, a signal detection board and a time sequence control board; the auxiliary module comprises a power supply module and a case back plate, and the case back plate comprises a data external interface, a synchronous clock interface and a radio frequency clock interface; the high-speed acquisition board comprises an FPGA chip, the FPGA chip is connected with the analog-to-digital converter, and the signal processing board and the signal detection board are connected with the high-speed acquisition board through the chassis back board. The invention adopts the IP core of AURORA64b/66b, designs the sending module and the receiving module around the problem of the accurate synchronous transmission of 24Gb/s data transmission rate, introduces the cross-clock domain problem of the data receiving and sending, the IP core setting problem of AURORA, the constraint problem of XDC files, the problem of the packet head adding of the sending module, the problem of the elimination and verification of the receiving module and the problem of 48Gb/s ultra-wideband transmission in more detail, and has great reference significance.

Description

Method for realizing single-board ultra wide band and multi-board multi-path synchronous transmission based on FPGA

Technical Field

The invention relates to the field of digital signal processing, in particular to a method for realizing single-board ultra wide band and multi-board multi-path synchronous transmission based on an FPGA (field programmable gate array).

Background

With the continuous development of software radio technology and array signal processing technology, the amount of real-time processing data required for signal processing is gradually increasing, which makes precise synchronous transmission of data streams face a greater challenge. In the prior art, a high-speed transmission mode is adopted for transmitting multiple paths of data streams, signals are very difficult to accurately synchronize, and transmitted data are disordered after being combined.

In view of the above-mentioned related art, the inventor considers that there is a bottleneck problem in the connection, and therefore, a technical solution is needed to improve the above technical problem.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method for realizing single-board ultra wide band and multi-board multi-path synchronous transmission based on an FPGA.

The invention provides a method for realizing single-board ultra-wideband and multi-board multi-path synchronous transmission based on FPGA, which comprises a 16-path high-speed GTH transmission system, wherein the 16-path high-speed GTH transmission system comprises a main control module and an auxiliary module;

the main control module comprises a PCB (printed circuit board), and the PCB comprises a high-speed acquisition board, a signal processing board, a signal detection board and a time sequence control board;

the auxiliary module comprises a power module and a case back plate, wherein the case back plate comprises 16 paths of data external interfaces, a 100MHZ synchronous clock interface and a 6GHz radio frequency clock interface;

the high-speed acquisition board comprises an FPGA chip, the FPGA chip is connected with the analog-to-digital converter, and the signal processing board and the signal detection board are connected with the high-speed acquisition board through the chassis back board.

Preferably, the 16-path high-speed GTH transmission system shares a clock module, a common reset module and a common wrapper module, and the GTH transmission of the high-speed acquisition board reduces BUFG.

Preferably, the GTH transmission control method of the signal detection board includes the steps of:

step 1: converting an external clock differential into a single end;

and 2, step: the GTH sets a single-ended clock input;

and 3, step 3: and 8-path GTH transmission of single-clock double-BANK is realized in a wrapper removing mode.

Preferably, the method for performing 16-path high-speed GTH multi-path synchronous alignment by the signal detection board and performing packet header removal and packet header addition transmission by the signal processing board includes the following steps:

s1: receiving ADC data, removing a packet header by adopting a method of detecting a character string by a state machine, and pulling up the data by valid;

s2: carrying out related algorithm processing to obtain new data;

s3: and (5) beating and aligning the new data after the new data is re-coated with the packet head.

Preferably, the ultra-wideband real-time transmission method comprises the following steps:

step S1: receiving ADC data;

step S2: carrying out related algorithm processing to generate a 688-path 8-bit module value;

and step S3: disassembling and sending;

and step S4: and combining and receiving.

Preferably, the 16 ADC data acquisition working signals of the high-speed acquisition board and the 16 channels of data overlay packet header trigger signals are controlled by the same trigger signal.

Preferably, the 16-channel data adaptive alignment method adopts a detection, beating and alignment method to realize 16-channel signal adaptive alignment.

Compared with the prior art, the invention has the following beneficial effects:

1. the logic analyzer is used for analyzing the logic relation of the digital logic system, can observe and measure data streams on a plurality of data lines simultaneously, and is very effective for testing a complex digital system. The VIVADO online logic analyzer utilizes FPGA internal resources to build an IP core and simulates a real logic analyzer to capture signal waveforms, thereby being convenient for verifying whether the design is correct or not. MATLAB carries out big data comparison and also has obvious advantage for excel, and it can carry out the bit width data comparison more than several thousand bits, and this is that excel formula can not do.

2. The invention adopts MATLAB comparison program to compare the primary data transmission and reception, if the data transmission and reception are the same, then the data transmission and reception are called as consistent, and the data transmission and reception are called as consistent for short. If the output values of the test _ cnt1 and the test _ cnt2 signals are fixed numbers and there is no invalid data in the data stream, the data are called continuous, and the data are called continuous for short. And measuring data every half hour, and continuously capturing 24 groups of data to obtain an overall verification result. Practice proves that 24 groups of data have continuous consistency, so that the design can further judge that the synchronous transmission data is correct.

3. The invention adopts an AURORA64b/66b IP core, designs a sending module and a receiving module around the problem of accurate synchronous transmission of 24Gb/s data transmission rate, introduces the related problem of cross clock domain of receiving and sending data, the problem of IP core setting of AURORA, the problem of restraint of XDC files, the problem of packet head adding of the sending module and the problem of elimination and verification of the receiving module in more detail, and has greater reference significance for the research of the transmission problem between higher bandwidth transmission and higher rate boards.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a block diagram of the present invention.

Fig. 2 is a structural diagram of an ultra-wideband transmission transmitting module design according to the present invention.

FIG. 3 is a logic analysis verification diagram of zero error propagation result lines of the sending module and the receiving module according to the present invention.

FIG. 4 is a diagram of the software architecture of the present invention.

FIG. 5 is an architecture diagram of a single FPGA chip transmit module of the present invention.

FIG. 6 is a diagram of an architecture of an individual FPGA chip receive module of the present invention.

Fig. 7 is a diagram of the verification of the complete alignment of 16 data paths using the on-line logic analyzer according to the present invention.

Fig. 8 is a diagram illustrating the verification of whether invalid data exists in the received data according to the present invention.

Fig. 9 is a diagram of a transmission architecture of 16-way high-speed GTH ultra-wideband transmission based on an FPGA according to the present invention.

Fig. 10 is a timing diagram of one channel of ADC data acquisition and simultaneous triggering of a packet header according to the present invention.

Fig. 11 is a flowchart of a GTH transmission control method of a signal detection board according to the present invention.

Fig. 12 is a flowchart of a method for decapsulating and decapsulating transmissions performed by the signal processing board according to the present invention.

Fig. 13 is a flowchart of the ultra-wideband real-time transmission method of the present invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will aid those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any manner. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The invention provides a method for realizing single-board ultra wide band and multi-board multi-path synchronous transmission based on FPGA, which consists of a main control module and an auxiliary module. The main control module comprises nine PCB boards: the system comprises four high-speed acquisition boards, two signal processing boards consisting of four FPGAs, two signal detection boards consisting of four FPGAs and one time sequence control board; the auxiliary module comprises two board cards of a power module and a chassis back plate, wherein the back plate is provided with a 16-path data external interface, a 100MHZ synchronous clock interface and a 6GHZ radio frequency clock interface which are connected with the receiver.

Each high-speed acquisition board is provided with two FPGA chips, the specific model is xc7vx690tffg1927-2, and each chip is connected with two paths of ADC analog-to-digital converters. Thus, each high-speed acquisition board receives 4 paths of ADC data, and four high-speed acquisition boards receive 16 paths of ADC data and 4 paths of FFT-passed mode values with the bit width of 6880.

The signal processing board composed of four FPGAs transmits one path of ADC data to the signal processing board through high-speed GTH transmission, and then the ADC data is processed through a related algorithm to form one path of signal data. Therefore, 8 paths of signal data are formed by one signal processing board consisting of four FPGAs, and 16 paths of signal data are formed by two signal processing boards.

One of the functions of the signal detection board is to receive two groups of 8-path real-time signal data, realize the complete alignment of 16-path signal data and then perform 8-time signal extraction. Let one effect be that four chips receive 688 way module value 8 bit module values simultaneously, and finally four way module values are all transmitted to chip four.

The time sequence control board is used for sending a single-bit trigger signal, the trigger signal is connected with the 16 paths of ADC analog-to-digital converters of the four high-speed acquisition boards and is used as an acquisition switch of the ADC analog-to-digital converters, and therefore data acquired by the 16 paths of ADC analog-to-digital converters are ensured to start from the same time point.

A16-path high-speed GTH synchronous multi-path transmission method based on FPGA comprises the following steps:

the method comprises the following steps: and setting parameters. The invention adopts GTH as AURORA protocol, adopts 64B/66B coding mode, and 4-path transmission is adopted for IPCORE of each AURORA. The IPCORE of AURORA has three modes, namely a single-transmitting mode, a single-receiving mode and a transmitting-receiving integrated mode; the communication interface has two modes, namely a frame mode and a stream mode; the invention adopts a single-sending mode, a single-receiving mode, a frame mode and a small end alignment mode; the technology adopts the transmission rate of 5Gb/s, the DRP clock and the INIT clock of 50M, the GTH reference clock of 125M, does not use K codes and does not use flow control.

Step two: the setting of the command is constrained. The constraint commands include a common constraint command and a special constraint command. Common constraint commands refer to clock frequency constraints, position constraints, level constraints. The invention adopts special constraint command to refer to netlist constraint. For clock pins, the frequency, level and position are constrained; for non-clocked pins, the level and position are constrained. According to the invention, the problem that data captured by ILA is synthesized is solved, and a special command mark _ debug is used for restricting a netlist; for the problem of large-bit-width data wiring failure, the special command max _ fanout is adopted to constrain the netlist, and the special command power card chains is adopted to constrain the netlist, so that the operation number with large bit width is realized by using a lookup table without using a carry chain. Meanwhile, bit files are compressed by adopting special commands, and the program is downloaded quickly.

Step three: and controlling the high-speed acquisition board by using FPGA software. Firstly, single-bit data generated by two analog-to-digital converters ADC1 and ADC2 on a high-speed acquisition board is converted into 128-bit parallel data by setting deserializing factors through an IP core SELECTIO, and the 128-bit data enters two asynchronous FIFOs of FIFO1 and FIFO2, so that the effect of unifying clock domains is achieved; secondly, a packet header is added, encoding is carried out in a barker code mode, and bit width conversion is carried out through an FIFO3 and an FIFO 4; and finally, data are buffered through two FIFOs, namely a FIFO5 and a FIFO6, AXI bus conversion is carried out, and the data are transmitted through an AURORA simplex module. The two chips of each board are operated in this way, and 16 paths of ADC original data are formed. In addition, after data from the select io is subjected to a correlation algorithm, a 688-path 10-bit module value is generated, the module values are overlapped and sent to a signal detection version two through an autonomous error rate (AURORA) simplex module, and data are provided for a frequency measurement algorithm.

Step four: and the signal processing board consisting of the four FPGAs is controlled by FPGA software. Data transmitted by AURORA is processed by a relevant algorithm, finally, each FPGA forms two paths of signal data, the signal data are transmitted to the FPGA1 through the FPGA4, the signal data are transmitted to the FPGA1 through the FPGA3, the signal data are transmitted to the FPGA1 through the FPGA2, 8 paths of ADC original data are matched with frequency measurement data, 8 paths of signal data are formed, and then a mode of removing a packet header and adding the packet header is used, and the signal data are transmitted through an AURORA simplex module.

Step five: and controlling the signal detection board I by using FPGA software. And receiving through an AURORA simplex module, wherein the same GTH clock is used for driving GTH channels of two adjacent BANKs by adopting a method of converting difference into single end. And the received data enters a rejection module for processing, the rejected data enters a verification module for processing, the data enters a self-adaptive alignment module after the verification module displays the data correctly, and the data is output and then is observed in a logic analyzer to judge whether the 16 paths of signal data are aligned. After long-time operation, the data of the 16 signals are completely aligned and represent correct data.

Step six: and controlling the time sequence control board by using FPGA software. The trigger signal is controlled to be converted through the virtual IO, and then the ODDR source language and the single-ended differential source language are converted to realize the starting and the ending of the trigger signal, and the trigger signal can be used as system soft reset.

A single-board single-path ultra-bandwidth transmission method based on FPGA comprises the following steps:

Step two: the setting of the constraint command. The constraint commands include common constraint commands and special constraint commands. Common constraint commands refer to clock frequency constraints, position constraints, level constraints. The invention adopts special constraint command to refer to netlist constraint. For clock pins, the frequency, level and position are constrained; for non-clock pins, the level and position are constrained. According to the invention, the problem that data captured by ILA is synthesized is solved, and a special command mark _ debug is used for restricting a netlist; for the problem of large-bit-width data wiring failure, the special command max _ fanout is adopted to constrain the netlist, and the special command power card chains is adopted to constrain the netlist, so that the operation number with large bit width is realized by using a lookup table without using a carry chain. Meanwhile, bit files are compressed by adopting special commands, and the program is downloaded quickly.

Step three: and controlling the high-speed acquisition board by using FPGA software. Firstly, single-bit data generated by two analog-to-digital converters ADC1 and ADC2 on a high-speed acquisition board is converted into 128-bit parallel data by setting deserializing factors through an IP core SELECTIO, and the 128-bit data is unified in a clock domain; and generating 688-path 10-bit module values after a correlation algorithm, and superposing the module values. And finally, splitting data by a special method, and sending the AURORA simplex module to a signal detection version two.

Step four: and controlling the second detection version by using FPGA software. And receiving the combined data by using a special method through an AURORA simplex module, transmitting the data to a second detection version, and finally restoring 688 channels of 10-bit data in a lossless manner by each FPGA chip of the second detection version.

The logic analyzer is an instrument for analyzing the logic relation of a digital logic system, can observe and measure data streams on a plurality of data lines simultaneously, and is very effective for testing a complex digital system. The VIVADO online logic analyzer utilizes FPGA internal resources to build an IP core and simulates a real logic analyzer to capture signal waveforms, so that whether the design is correct or not is verified conveniently. MATLAB carries out big data comparison and also has obvious advantage compared with excel, and it can carry out the bit width data comparison more than several thousand bits, and this is that excel formula can not do.

As can be seen from fig. 2, the result of the online logic analyzer is that the sending module sends out the packet header 1110010, the receiving module receives the packet header 1110010, which represents that the packet header is correctly transmitted, the following data is derived by ILA, and then whether the sending and receiving are consistent is detected in MATLAB by writing an MATLAB comparison program. If the transmission and the reception are consistent, the data is transmitted with zero error. As can be seen from fig. 7, the output values of the test _ cnt1 and the test _ cnt2 signals are fixed numbers, and the data transmission continuity is verified from another layer. Because the two phenomena exist objectively, the synchronous transmission data is correct.

The invention adopts MATLAB comparison program to compare the primary data transmission and reception, if the data transmission and reception are the same, then the data transmission and reception are called as consistent, and the data transmission and reception are called as consistent for short. If the output values of the test _ cnt1 and the test _ cnt2 signals are fixed numbers and no invalid data exists in the data stream, the data are called continuous, and the data are called continuous for short. And measuring the data every half hour, and continuously capturing 24 groups of data to obtain an overall verification result. Practice proves that 24 groups of data have continuous consistency, so that the design can further judge that the synchronous transmission data is correct.

The invention adopts an AURORA64b/66b IP core, designs a sending module and a receiving module around the problem of accurate synchronous transmission of 24Gb/s data transmission rate, introduces the related problem of cross clock domain of receiving and sending data, the problem of IP core setting of AURORA, the problem of restraint of XDC files, the problem of packet head adding of the sending module and the problem of elimination and verification of the receiving module in more detail, and has greater reference significance for the research of the transmission problem between higher bandwidth transmission and higher rate boards.

The FPGA program of the high-speed acquisition board is compiled by 4 groups of 4-path incoherent accumulation and first-order ultra-wideband transmission methods based on two architecture diagrams shown in the attached drawings 4 and 5 and matched with a dotted line part shown in the attached drawing 1 and an attached drawing 8. And generating an MCS file after the compiling is finished, adjusting a dial switch, and burning the program in the four high-speed acquisition boards.

The two signal processing boards and the two FPGA programs of the signal detection board of the four FPGA chips are compiled based on the two architecture diagrams of the attached drawings 2 and 8 and combined with the attached drawing 9. After the writing is finished, generating an MCS file, adjusting a dial switch, and burning the program in a signal processing board and a signal detection board.

The FPGA program of the time sequence control board is based on the FPGA program and is completed based on the fifth step of the invention content. After the compiling is finished, an MCS file is generated, a dial switch is adjusted, and a program is burned out in a time sequence control board and is used for triggering all ADCs in the four high-speed acquisition boards to work at the same time.

When a trigger switch in the time sequence control board is pulled high to start working, 16 paths of data and continuous consistency and alignment conditions of the signal detection board are verified.

Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. A method for realizing single-board ultra wide band and multi-board multi-path synchronous transmission based on FPGA is characterized by comprising a 16-path high-speed GTH transmission system, wherein the 16-path high-speed GTH transmission system comprises a main control module and an auxiliary module;

the master control module comprises nine PCB boards, and each PCB board comprises four high-speed acquisition boards, two signal processing boards, two signal detection boards and a time sequence control board;

each high-speed acquisition board comprises two FPGA chips, each FPGA chip is connected with two paths of ADC (analog-to-digital converters), each signal processing board and each signal detection board comprise four FPGA chips and are connected with the high-speed acquisition board through a chassis back plate;

the implementation method comprises the following steps:

a transmission control method of single differential clock adjacent double BANK,

the GTH transmission control method of the signal detection board comprises the following steps:

step 1: converting an external clock differential into a single end;

step 2: the GTH sets a single-ended clock input;

and 3, step 3: the method of unwrapper is adopted, and 8-path GTH transmission of single-clock double-BANK is realized;

the 16-path high-speed GTH multi-path synchronous alignment performed by the signal detection board and the packet head removing and adding transmission method performed by the signal processing board comprise the following steps:

s1: receiving ADC data, removing a packet header by adopting a method of detecting a character string by a state machine, and raising data by valid;

s2: carrying out related algorithm processing to obtain new data;

s3: adding a new packet head again and then shooting and aligning;

the ultra-wideband real-time transmission method comprises the following steps:

step S1: receiving ADC data;

and step S3: disassembling and sending;

and step S4: and combining and receiving.

2. The method for implementing FPGA-based single-board ultra-wideband and multi-board multi-path synchronous transmission according to claim 1, wherein the 16-path high-speed GTH transmission system shares a clock module, a reset module and a wrapper module, so that BUFG is greatly reduced in GTH transmission of the high-speed acquisition board.

3. The method for implementing ultra wide band and multi-board multi-path synchronous transmission based on the FPGA single-board, according to claim 1, is characterized in that 16 ADC data acquisition working signals of the four high-speed acquisition boards and 16 trigger signals of data overlay type with packet headers are controlled by the same trigger signal trigger, so as to ensure that 16 data are at the same start time.

4. The method according to claim 1, wherein the 16-channel data is obtained by adaptive alignment of detection, beat and alignment.