CN112802892A - SGT structure and manufacturing method thereof - Google Patents
SGT structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN112802892A CN112802892A CN202110011298.6A CN202110011298A CN112802892A CN 112802892 A CN112802892 A CN 112802892A CN 202110011298 A CN202110011298 A CN 202110011298A CN 112802892 A CN112802892 A CN 112802892A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- polycrystalline silicon
- isolation
- shielding
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 105
- 238000002955 isolation Methods 0.000 claims abstract description 72
- 229920005591 polysilicon Polymers 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
- 230000001590 oxidative effect Effects 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an SGT structure and a manufacturing method thereof. Wherein the structure includes: a trench extending downward from an upper surface of the semiconductor substrate; the inner surface of the lower space of the groove is covered with a shielding dielectric layer, and the shielding dielectric layer surrounds to form a first accommodating space; the source electrode polycrystalline silicon fills the first accommodating space, and the top end of the source electrode polycrystalline silicon is exposed out of the first accommodating space; the first isolation dielectric layer covers the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon; the second isolation medium layer covers the exposed surface of the source electrode polycrystalline silicon and the inner surface of the upper space of the groove; the first isolation medium layer and the second isolation medium layer surround to form a second accommodating space; the grid polysilicon fills the second accommodating space; the manufacturing method is used for manufacturing the SGT structure. The SGT structure and the manufacturing method thereof can reduce parasitic capacitance of a device and reduce power loss of the device.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit manufacturing technologies, and in particular, to a Shielded Gate Trench (SGT) structure and a method for fabricating the SGT structure.
Background
In the related art, the SGT structure is formed by etching a semiconductor substrate to form a trench, and then oxidizing the surface of the semiconductor substrate by a thermal oxidation method to form a shielding dielectric layer, wherein the shielding dielectric layer covers the surface of the trench according to the shape of the trench, so that the trench covered with the shielding dielectric layer forms an accommodating space. And then depositing source polysilicon to fill the source polysilicon in the accommodating space of the trench. And etching the shielding dielectric layer and the source polysilicon to form a gate space in the trench, forming an isolation oxide layer on the exposed source polysilicon, and depositing polysilicon in the gate space, thereby finally forming the SGT structure shown in FIG. 1.
Referring to fig. 1, in the SGT structure, a gate space formed after etching the shield dielectric layer 110 and the source polysilicon 120 overlaps with the top of the source polysilicon 120, so that the formed gate polysilicon 130 and the source polysilicon 120 overlap in the region M shown in fig. 1, which may cause a problem of an increase in parasitic capacitance between a gate source and a gate drain, and increase power loss of the device.
Disclosure of Invention
The application provides an SGT structure and a manufacturing method thereof, which can reduce parasitic capacitance of a device and reduce power loss of the device.
In order to solve the above technical problem, the present application provides an SGT structure, including:
a trench extending downward from an upper surface of the semiconductor substrate; a shielding dielectric layer covers the inner surface of the lower space of the groove, and the shielding dielectric layer surrounds to form a first accommodating space;
the source electrode polycrystalline silicon fills the first containing space, and the top end of the source electrode polycrystalline silicon is exposed out of the first containing space;
the first isolation dielectric layer covers the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon;
the second isolation dielectric layer covers the exposed surface of the source electrode polycrystalline silicon and the inner surface of the upper space of the groove;
the first isolation medium layer and the second isolation medium layer surround to form a second accommodating space;
and the grid polysilicon fills the second accommodating space.
Optionally, the second accommodating space extends downwards at two sides of the exposed portion of the source polysilicon.
Optionally, the second accommodating space extends downward to a depth of 1500 to 3000 angstroms.
Optionally, the thickness of the first isolation dielectric layer is 4000 angstroms to 6000 angstroms.
Optionally, the thickness of the second isolation dielectric layer covering the inner surface of the upper space of the trench is 500 to 1000 angstroms.
Optionally, the thickness of the shielding dielectric layer covering the inner surface of the space under the trench is 4000 to 8000 angstroms.
The application also provides a manufacturing method of the SGT structure, which comprises the following steps:
etching a semiconductor substrate, and forming a groove extending downwards in the semiconductor substrate;
oxidizing the inner surface of the groove to form a shielding dielectric layer, so that the shielding dielectric layer surrounds to form a first accommodating space;
depositing polycrystalline silicon into the first accommodating space;
selectively etching to remove the shielding medium layer and the polycrystalline silicon in the upper space of the groove; forming source electrode polycrystalline silicon by using the residual polycrystalline silicon, wherein the top end of the source electrode polycrystalline silicon is exposed out of the shielding grid dielectric layer;
manufacturing a first isolation dielectric layer to enable the first isolation dielectric layer to cover the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon;
manufacturing a second isolation medium layer to enable the second isolation medium layer to cover the exposed surface of the source electrode polycrystalline silicon and the inner surface of the upper space of the groove;
and depositing polycrystalline silicon into a second accommodating space formed by surrounding the first isolation medium layer and the second isolation medium layer to form grid polycrystalline silicon.
Optionally, the step of oxidizing the inner surface of the trench to form a shielding dielectric layer includes:
and oxidizing the semiconductor substrate through a thermal oxidation process so as to form a shielding dielectric layer on the inner surface of the groove.
Optionally, the step of manufacturing a first isolation dielectric layer so that the first isolation dielectric layer covers the shielding dielectric layers on both sides of the exposed portion of the source polysilicon includes:
depositing a dielectric layer on the selectively etched shielding dielectric layer and the source electrode polysilicon through a high-density plasma process;
and after annealing the dielectric layer, etching the dielectric layer by a wet etching process to form the first isolation dielectric layer, so that the first isolation dielectric layer covers the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon.
The technical scheme at least comprises the following advantages: according to the method, the first isolation dielectric layer covers the shielding dielectric layers on the two sides of the exposed part of the source polycrystalline silicon, the height of the exposed part of the source polycrystalline silicon can be reduced, and the situation that the gate polycrystalline silicon deposited in the second accommodating space is overlapped with the source polycrystalline silicon too much in the second accommodating space at the downward extending position due to the fact that the depth of the downward extending part is too deep at the positions of the two sides of the exposed part of the source polycrystalline silicon in the second accommodating space is avoided, so that parasitic capacitance can be reduced, and power loss of a device is reduced.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 shows a cross-sectional structure of an SGT structure formed by a related art fabrication method;
fig. 2 illustrates an SGT structure provided in an embodiment of the present application, a cross-sectional structure perpendicular to a trench direction;
fig. 3 is a flowchart illustrating a method for manufacturing an SGT structure according to an embodiment of the present application;
fig. 4 illustrates a cross-sectional structure after step S2 in a method for fabricating an SGT structure according to an embodiment of the present application;
fig. 5 illustrates a cross-sectional structure after step S3 in a method for fabricating an SGT structure according to an embodiment of the present application;
fig. 6 illustrates a cross-sectional structure after step S4 in a method for manufacturing an SGT structure according to an embodiment of the present application;
fig. 7 illustrates a cross-sectional structure after step S5 in a method for fabricating an SGT structure according to an embodiment of the present application;
fig. 8 shows a cross-sectional structure after step S6 in a method for manufacturing an SGT structure according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 2 shows a schematic cross-sectional structural diagram perpendicular to a trench direction of an SGT structure provided in an embodiment of the present application, and referring to fig. 2, the SGT structure includes: a trench 200, and a shield gate dielectric layer 210, a source polysilicon 220, a first isolation dielectric layer 230, a second isolation dielectric layer 240 and a gate polysilicon 250 filling the trench 200.
The trench 200 extends downward from the upper surface of the semiconductor silicon substrate, the inner surface of the lower space of the trench 200 is covered with a shielding dielectric layer 210, and the shielding dielectric layer 210 surrounds and forms a first accommodating space 201.
The first accommodating space 201 is filled with the source polysilicon 220, and the top end of the source polysilicon 220 is exposed out of the first accommodating space 201.
The first isolation dielectric layer 230 covers the shielding dielectric layer 210 on both sides of the exposed portion of the source polysilicon 220.
The second isolation dielectric layer 240 covers the exposed surface of the source polysilicon 220 and the inner surface of the upper space of the trench 200. The first isolation dielectric layer 230 and the second isolation dielectric layer 240 surround to form a second accommodating space 202.
In this embodiment, the second accommodating space 202 extends downward at two sides of the exposed portion of the source polysilicon 220. As shown in fig. 2, the depth d1 of the second receiving space 202 extending downward is 1500 a to 3000 a, so that the gate polysilicon 250 filled in the second receiving space 202 extends downward by a depth d1 at two sides of the exposed portion of the source polysilicon 220 according to the shape of the second receiving space 202.
It can be understood that, in the present embodiment, by the first isolation dielectric layer 230, the first isolation dielectric layer 230 covers the shielding dielectric layer 210 on both sides of the exposed portion of the source polysilicon 220, the height of the exposed portion of the source polysilicon 220 can be reduced, and it is avoided that the gate polysilicon 250 deposited therein overlaps the source polysilicon 220 too much in the second receiving space 202 at the position extending downward due to the too deep downward extension depth of the second receiving space 202 at both sides of the exposed portion of the source polysilicon 220, so that the parasitic capacitance can be reduced, and the power loss of the device can be reduced.
The thickness d2 of the first isolation dielectric layer 230 is 4000 to 6000 angstroms, and the thickness of the first isolation dielectric layer 230 does not exceed the exposed portion of the source polysilicon 220. The thickness d3 of the second isolation dielectric layer covering the inner surface of the upper space of the trench is 500 to 1000 angstroms, so that the gate polysilicon 250 filled in the second accommodating space 202 contacts the upper surface of the first isolation dielectric layer 230 at the position where the second accommodating space 202 extends downward. The thickness d4 of the shielding dielectric layer 210 covering the inner surface of the space under the trench 200 is 4000 to 8000 a.
Optionally, the second isolation dielectric layer 240 may be formed by oxidizing the exposed surface of the source polysilicon 220 and the inner surface of the semiconductor silicon substrate in the upper space of the trench 200 through a thermal oxidation process to form the second isolation dielectric layer 240 made of silicon dioxide; and the thickness of the second isolation dielectric layer 240 formed on the inner surface of the semiconductor silicon substrate in the upper space of the trench 200 is thinner than the thickness of the second isolation dielectric layer 240 formed on the surface of the exposed source polysilicon 220.
With continued reference to fig. 2, the gate polysilicon 250 is isolated from the source polysilicon 220 by the first isolation dielectric layer 230 and the second isolation dielectric layer 240.
Fig. 3 shows a flowchart of a method for manufacturing an SGT structure according to an embodiment of the present application, and referring to fig. 3, it can be seen that the method for manufacturing an SGT structure according to the embodiment of the present application includes the following steps:
step S1: and etching the semiconductor substrate, and forming a groove extending downwards in the semiconductor substrate.
The semiconductor substrate can be a semiconductor silicon substrate made of silicon, a groove pattern can be defined on the semiconductor substrate through a photoetching process, and then a groove extending downwards from the surface of the semiconductor substrate is formed through etching according to the groove pattern.
Step S2: and oxidizing the inner surface of the groove to form a shielding dielectric layer, so that the shielding dielectric layer surrounds and forms a first accommodating space.
Referring to fig. 4, which shows a schematic cross-sectional structure of a SGT structure provided in an embodiment of the present invention after step S2 is completed, in an embodiment where the semiconductor substrate is a semiconductor silicon substrate, a thermal oxidation process may be employed to oxidize silicon on the surface of the semiconductor substrate into silicon dioxide, and the silicon dioxide located on the inner surface of the trench 200 is formed as a shielding dielectric layer 210 of the SGT. In this embodiment, the shielding dielectric layer 210 formed by oxidizing the semiconductor substrate has conformality, that is, the profile structure of the formed shielding gate dielectric layer 210 is in accordance with the profile structure of the inner surface of the trench 200, so the formed shielding dielectric layer 210 surrounds and forms the first accommodating space 201.
Step S3: and depositing polycrystalline silicon into the first accommodating space.
Fig. 5 shows a schematic cross-sectional structure of the SGT structure provided in the present application after step S3 is completed, and referring to fig. 5, the deposited polysilicon is located in the first accommodating space 201 formed by surrounding the shielding dielectric layer 210.
Step S4: selectively etching to remove the shielding medium layer and the polycrystalline silicon in the upper space of the groove; and forming source electrode polycrystalline silicon by using the residual polycrystalline silicon, wherein the top end of the source electrode polycrystalline silicon is exposed out of the shielding grid dielectric layer.
Referring to fig. 6, which illustrates a schematic cross-sectional structure of the SGT structure after step S4 is completed in an embodiment of the present invention, the R trench 200 includes an upper space R1 and a lower space R2. After the selective etching is performed to remove the shielding dielectric layer 210 in the space R1 above the trench 200, and after the polysilicon is removed, the remaining shielding dielectric layer 210 and polysilicon are located in the space R2 below the trench 200, and the remaining polysilicon forms the source polysilicon 220, the top of the source polysilicon 220 is exposed to the shielding gate dielectric layer 210, and the portion a shown in fig. 6 is the portion of the source polysilicon 220 exposed to the shielding gate dielectric layer 210.
Step S5: and manufacturing a first isolation dielectric layer to enable the first isolation dielectric layer to cover the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon.
In this embodiment, a dielectric layer may be deposited on the selectively etched shielding dielectric layer and the source polysilicon by a high-density plasma process. And annealing the dielectric layer. And finally, etching the dielectric layer by a wet etching process to form the first isolation dielectric layer, so that the first isolation dielectric layer covers the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon.
Referring to fig. 7, which shows a schematic cross-sectional structure of the SGT structure provided in the present application after step S5 is completed, referring to fig. 7, a first isolation dielectric layer 230 covers the shielding dielectric layer 210 on both sides of the portion of the source polysilicon 220 exposed and shielding the gate dielectric layer 210, i.e., portion a, where the thickness d2 of the first isolation dielectric layer 230 may be 4000 angstroms to 6000 angstroms. In this embodiment, the thickness d2 of the first isolation dielectric layer 230 is less than the height h1 of the portion a, so that the top of the portion a still has an exposed surface after the first isolation dielectric layer 230 is formed.
Step S6: and manufacturing a second isolation dielectric layer so that the second isolation dielectric layer covers the exposed surface of the source electrode polycrystalline silicon and the inner surface of the upper space of the groove.
Referring to fig. 8, which illustrates a cross-sectional structure of the SGT structure after step S6 is completed, a second isolation dielectric layer 240 is formed to cover the exposed surface of the source polysilicon 240 and the inner surface of the upper space of the trench 200 on the first isolation dielectric layer 230 according to an embodiment of the present invention. The exposed surface of the source polysilicon layer 240 and the inner surface of the upper space of the trench 200 may be oxidized by a thermal oxidation process to form a second isolation dielectric layer 240 comprising silicon dioxide.
With continued reference to fig. 8, the first isolation dielectric layer 230 and the second isolation dielectric layer 240 surround and form the second accommodating space 202. The second receiving space 202 extends downward at two sides of the exposed portion of the source polysilicon 220, and the depth d1 of the downward extension is 1500 to 3000 angstroms.
Step S7: and depositing polycrystalline silicon into a second accommodating space formed by surrounding the first isolation medium layer and the second isolation medium layer to form grid polycrystalline silicon.
After step S7 is completed, the SGT structure shown in fig. 2 is formed, and referring to fig. 2, the gate polysilicon 250 filled in the second accommodating space 202 extends downward by a depth d1 at two sides of the exposed portion of the source polysilicon 220 according to the shape of the second accommodating space 202.
In summary, in the present embodiment, the first isolation dielectric layer covers the shielding dielectric layers on the two sides of the exposed portion of the source polysilicon, so that the height of the exposed portion of the source polysilicon can be reduced, and the situation that the gate polysilicon deposited therein overlaps too much with the source polysilicon in the second accommodating space at the position where the gate polysilicon extends downwards due to the too deep depth of the second accommodating space at the two sides of the exposed portion of the source polysilicon is avoided, thereby reducing parasitic capacitance and reducing power loss of the device.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (9)
1. An SGT structure, comprising:
a trench extending downward from an upper surface of the semiconductor substrate; a shielding dielectric layer covers the inner surface of the lower space of the groove, and the shielding dielectric layer surrounds to form a first accommodating space;
the source electrode polycrystalline silicon fills the first containing space, and the top end of the source electrode polycrystalline silicon is exposed out of the first containing space;
the first isolation dielectric layer covers the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon;
the second isolation dielectric layer covers the exposed surface of the source electrode polycrystalline silicon and the inner surface of the upper space of the groove;
the first isolation medium layer and the second isolation medium layer surround to form a second accommodating space;
and the grid polysilicon fills the second accommodating space.
2. The SGT structure as described in claim 1 wherein said second receiving space extends downwardly at locations on either side of said exposed portion of source polysilicon.
3. The SGT structure as described in claim 2 wherein said second receiving volume extends downwardly to a depth of 1500 to 3000 angstroms.
4. The SGT structure of claim 1 wherein the first isolating dielectric layer has a thickness of 4000 to 6000 angstroms.
5. The SGT structure of claim 1 wherein the second insulating dielectric layer overlying the trench headspace inner surface has a thickness in the range of 500 to 1000 angstroms.
6. The SGT structure as described in claim 1 wherein said shield dielectric layer overlying the interior surface of the trench lower space has a thickness in the range of 4000 to 8000 angstroms.
7. A manufacturing method of an SGT structure is characterized by comprising the following steps:
etching a semiconductor substrate, and forming a groove extending downwards in the semiconductor substrate;
oxidizing the inner surface of the groove to form a shielding dielectric layer, so that the shielding dielectric layer surrounds to form a first accommodating space;
depositing polycrystalline silicon into the first accommodating space;
selectively etching to remove the shielding medium layer and the polycrystalline silicon in the upper space of the groove; forming source electrode polycrystalline silicon by using the residual polycrystalline silicon, wherein the top end of the source electrode polycrystalline silicon is exposed out of the shielding grid dielectric layer;
manufacturing a first isolation dielectric layer to enable the first isolation dielectric layer to cover the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon;
manufacturing a second isolation medium layer to enable the second isolation medium layer to cover the exposed surface of the source electrode polycrystalline silicon and the inner surface of the upper space of the groove;
and depositing polycrystalline silicon into a second accommodating space formed by surrounding the first isolation medium layer and the second isolation medium layer to form grid polycrystalline silicon.
8. The method of fabricating an SGT structure according to claim 7, wherein said step of oxidizing an inner surface of said trench to form a shield dielectric layer comprises:
and oxidizing the semiconductor substrate through a thermal oxidation process so as to form a shielding dielectric layer on the inner surface of the groove.
9. The method of fabricating an SGT structure according to claim 7, wherein said step of fabricating a first isolation dielectric layer such that said first isolation dielectric layer overlies said shield dielectric layer on both sides of said exposed portion of source polysilicon comprises:
depositing a dielectric layer on the selectively etched shielding dielectric layer and the source electrode polysilicon through a high-density plasma process;
and after annealing the dielectric layer, etching the dielectric layer by a wet etching process to form the first isolation dielectric layer, so that the first isolation dielectric layer covers the shielding dielectric layers on two sides of the exposed part of the source electrode polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110011298.6A CN112802892A (en) | 2021-01-06 | 2021-01-06 | SGT structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110011298.6A CN112802892A (en) | 2021-01-06 | 2021-01-06 | SGT structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112802892A true CN112802892A (en) | 2021-05-14 |
Family
ID=75808380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110011298.6A Pending CN112802892A (en) | 2021-01-06 | 2021-01-06 | SGT structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112802892A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140287574A1 (en) * | 2013-03-22 | 2014-09-25 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device having field plate electrode |
| CN107068763A (en) * | 2017-03-31 | 2017-08-18 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power device and its manufacture method |
| CN107492486A (en) * | 2017-08-15 | 2017-12-19 | 上海华虹宏力半导体制造有限公司 | The process of groove type double-layer grid MOS dielectric layers |
| CN110034182A (en) * | 2019-03-13 | 2019-07-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of trench-gate device with shield grid |
-
2021
- 2021-01-06 CN CN202110011298.6A patent/CN112802892A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140287574A1 (en) * | 2013-03-22 | 2014-09-25 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device having field plate electrode |
| CN107068763A (en) * | 2017-03-31 | 2017-08-18 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power device and its manufacture method |
| CN107492486A (en) * | 2017-08-15 | 2017-12-19 | 上海华虹宏力半导体制造有限公司 | The process of groove type double-layer grid MOS dielectric layers |
| CN110034182A (en) * | 2019-03-13 | 2019-07-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of trench-gate device with shield grid |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5904540A (en) | Method for manufacturing shallow trench isolation | |
| US6849919B2 (en) | Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device | |
| KR101821413B1 (en) | An isolation structure, an semiconductor device comprising the isolation structure, and method for fabricating the isolation structure thereof | |
| US5918131A (en) | Method of manufacturing a shallow trench isolation structure | |
| CN111696991B (en) | NORD flash memory and manufacturing method thereof | |
| CN112466880B (en) | Three-dimensional memory and preparation method thereof | |
| TWI514577B (en) | Semiconductor device and method for fabricating the same | |
| CN114496755A (en) | Shielding gate MOSFET device and manufacturing method thereof | |
| US7625805B2 (en) | Passivation of deep isolating separating trenches with sunk covering layers | |
| CN111564493B (en) | Trench power transistor and method for fabricating the same | |
| CN112802892A (en) | SGT structure and manufacturing method thereof | |
| CN113506822A (en) | SGT structure and manufacturing method thereof | |
| CN112186041B (en) | SGT device for improving wafer warping and manufacturing method thereof | |
| KR20040110318A (en) | STI structure and processing method | |
| KR20140137222A (en) | Semiconductor apparatus and manufacturing method of the same | |
| CN113224068A (en) | NORD flash memory device structure and manufacturing method thereof | |
| US6855617B1 (en) | Method of filling intervals and fabricating shallow trench isolation structures | |
| CN117677198A (en) | Forming method of split gate type flash memory | |
| CN115548105A (en) | Method for manufacturing shielding trench gate | |
| US11889681B2 (en) | Integrated circuit devices having buried word lines therein | |
| CN114023811B (en) | Shielded gate trench type MOSFET device and manufacturing method thereof | |
| CN115985768A (en) | Gate structure of high-power device and manufacturing method thereof | |
| CN110739273B (en) | Manufacturing method of ultra-thin grid CMOS device | |
| KR102661930B1 (en) | Integrated circuit device | |
| JPWO2008139898A1 (en) | Semiconductor device manufacturing method and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210514 |
|
| RJ01 | Rejection of invention patent application after publication |