CN117677198A - Forming method of split gate type flash memory - Google Patents
Forming method of split gate type flash memory Download PDFInfo
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- CN117677198A CN117677198A CN202311371292.5A CN202311371292A CN117677198A CN 117677198 A CN117677198 A CN 117677198A CN 202311371292 A CN202311371292 A CN 202311371292A CN 117677198 A CN117677198 A CN 117677198A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000002955 isolation Methods 0.000 claims abstract description 149
- 238000005530 etching Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 description 12
- 230000008021 deposition Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a forming method of a split gate type flash memory. The method comprises the following steps: providing a substrate layer, and forming a first isolation medium side wall on the side wall of the hard mask layer in the window of the split gate flash memory device; etching to remove the exposed erasing gate layer at the window of the split gate flash memory device with the first isolation medium side wall; forming a second isolation medium side wall on the side wall of the first isolation medium side wall in the window of the split gate flash memory device, wherein the second isolation medium side wall covers the floating gate layer; forming a third isolation medium side wall on the side wall of the second isolation medium side wall, wherein the third isolation medium side wall covers the side wall of the floating gate layer to play a role in isolating a source line from the floating gate layer; the isolation gate flash memory device window with the first isolation medium side wall, the second isolation medium side wall and the third isolation medium side wall forms a source line filling window; etching to remove the floating gate layer exposed from the source line filling window; ion implantation is performed based on the source line filling window.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a forming method of a split gate type flash memory.
Background
The side wall of the floating gate polysilicon plays a role in defining the length of the floating gate and isolating the erasing gate from the source line, so that the structure of the side wall of the floating gate polysilicon is important.
When the split gate flash memory performs an erase operation, a high voltage needs to be applied to an erase gate above a floating gate. To improve the data erase efficiency, it is desirable to reduce the overlap between the erase gate and the floating gate, i.e., to increase the length of the floating gate. Thicker floating gate poly spacers are typically required to define the length of the floating gate.
However, the thicker floating gate polysilicon side wall is difficult to etch by one etching process, so that the problem of incomplete etching of the floating gate polysilicon side wall easily occurs in the forming method of the split gate type flash memory in the related technology.
Disclosure of Invention
The application provides a forming method of split gate type flash memory, which can solve the problem that the etching of a floating gate polysilicon side wall is incomplete in the related technology.
In order to solve the technical problems described in the background art, the present application provides a method for forming a split gate flash memory, the method for forming the split gate flash memory includes the following steps:
providing a substrate layer, and forming a floating gate layer, an erasing gate layer and a hard mask layer on the substrate layer;
etching the hard mask layer to form a split gate flash memory device window;
forming a first isolation medium side wall on the side wall of the hard mask layer in the window of the split gate flash memory device;
etching to remove the exposed erasing gate layer at the window of the split gate flash memory device with the first isolation medium side wall;
forming a second isolation medium side wall on the side wall of the first isolation medium side wall in the window of the split gate flash memory device, wherein the second isolation medium side wall covers the floating gate layer;
forming a third isolation medium side wall on the side wall of the second isolation medium side wall, wherein the third isolation medium side wall covers the floating gate layer; the isolation gate flash memory device window with the first isolation medium side wall, the second isolation medium side wall and the third isolation medium side wall forms a source line filling window;
etching to remove the floating gate layer exposed from the source line filling window;
performing ion implantation based on the source line filling window, and forming a source doping region in the substrate layer below the source line filling window;
and depositing a fourth isolation medium side wall and a source line polycrystalline silicon structure, wherein the source line polycrystalline silicon structure fills the source line filling window, and the fourth isolation medium side wall is positioned between the source line polycrystalline silicon structure and the side surface of the floating gate layer.
Optionally, the step of forming a first isolation medium sidewall on the sidewall of the hard mask layer in the window of the split gate flash memory device includes:
blanket depositing a first dielectric layer, wherein the first dielectric layer covers the bottom surface and the side surface of the window of the split gate flash memory device and the upper surface of the hard mask layer;
and etching the first dielectric layer by adopting an etching process, and reserving the first dielectric layer positioned on the side wall of the hard mask layer in the window of the split gate flash memory device to form a first isolation dielectric side wall.
Optionally, the step of forming a second isolation medium sidewall on the sidewall of the first isolation medium sidewall in the window of the split gate flash memory device, where the second isolation medium sidewall covers the floating gate layer includes:
a second dielectric layer is blanket deposited, and the second dielectric layer covers the side surface of the first isolation dielectric side wall, the upper surface of the hard mask layer and the floating gate layer exposed from the window of the split gate flash memory device;
and etching the second dielectric layer by adopting an etching process, reserving the second dielectric layer covered on the side surface of the first isolation dielectric side wall to form a second isolation dielectric side wall, wherein the second isolation dielectric side wall is covered on the floating gate layer.
Optionally, the step of forming a third isolation medium sidewall on the sidewall of the second isolation medium sidewall, where the third isolation medium sidewall covers the floating gate layer includes:
a third dielectric layer is deposited in a blanket mode, and the third dielectric layer covers the side face of the second isolation dielectric side wall, the upper surface of the hard mask layer and the exposed floating gate layer;
etching the third dielectric layer by adopting an etching process, and reserving the third dielectric layer covered on the side surface of the second isolation dielectric side wall to form a third isolation dielectric side wall; the isolation gate flash memory device window with the first isolation medium side wall, the second isolation medium side wall and the third isolation medium side wall forms a source line filling window.
Optionally, the second isolation medium sidewall and the third isolation medium sidewall covered on the floating gate layer define an extension portion of the floating gate layer relative to the erase gate layer.
Optionally, the width of the second isolation medium side wall covered on the floating gate layer is 1100A to 1200A.
Optionally, the width of the third isolation medium side wall covered on the floating gate layer is 200A to 300A.
The technical scheme of the application at least comprises the following advantages: the second isolation medium side wall and the third isolation medium side wall are formed through the two deposition processes and the etching process, so that the structures of the second isolation medium side wall and the third isolation medium side wall are steeper, and isolation requirements are met. The extended part of the floating gate layer relative to the erasing gate layer is defined by the second isolation medium side wall and the third isolation medium side wall together, and the second isolation medium side wall and the third isolation medium side wall 322 are respectively formed through deposition and etching processes, so that the problem that the etching is incomplete due to the fact that the extended part is defined only through the deposition and etching processes of a thicker isolation medium layer can be avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart illustrating a method for forming a split gate flash memory according to an embodiment of the present application;
FIG. 2 shows a schematic cross-sectional structure of the device after completion of step S1;
FIG. 3 shows a schematic cross-sectional structure of the device after completion of step S2;
FIG. 4 shows a schematic cross-sectional structure of the device after completion of step S3;
FIG. 5 shows a schematic cross-sectional structure of the device after completion of step S4;
FIG. 6 shows a schematic cross-sectional structure of the device after completion of step S5;
FIG. 7 shows a schematic cross-sectional structure of the device after completion of step S6;
fig. 8 shows a schematic cross-sectional structure of the device after completion of step S7;
fig. 9 shows a schematic cross-sectional structure of the device after completion of step S8;
fig. 10 shows a schematic cross-sectional structure of the device after completion of step S9.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Fig. 1 shows a flowchart of a method for forming a split gate flash memory according to an embodiment of the present application, and as can be seen from fig. 1, the method for forming a split gate flash memory includes the following steps:
step S1: providing a substrate layer, and forming a floating gate layer, an erasing gate layer and a hard mask layer on the substrate layer.
Fig. 2 shows a schematic cross-sectional structure of the device after completion of step S1, and as can be seen from fig. 2, a floating gate layer 110, an erase gate layer 120, and a hard mask layer 130 are sequentially formed on a provided base layer 100. The floating gate layer 110 includes a floating gate dielectric layer 111 located at a lower layer and a floating gate polysilicon layer located on the floating gate dielectric layer 111, and the erase gate layer 120 includes an erase gate dielectric layer 121 located at a lower layer and an erase gate polysilicon layer located on the erase gate dielectric layer 121.
Step S2: and etching the hard mask layer to form a split gate flash memory device window.
Referring to fig. 3, which shows a schematic cross-sectional structure of the device after completion of step S2, as can be seen in fig. 3, the hard mask layer 130 is etched open to form a split gate flash memory device window 200, and the erase gate layer 120 is exposed from the split gate flash memory device window 200.
Step S3: and forming a first isolation medium side wall on the side wall of the hard mask layer in the window of the split gate flash memory device.
Referring to fig. 4, which is a schematic cross-sectional view of the device after the completion of step S3, as can be seen in fig. 4, the first isolation medium sidewall 310 is located on the erase gate layer 120.
The first spacer 310 occupies the width of the erase gate layer 120 to define an erase gate structure that forms a split gate structure in a subsequent step.
Illustratively, the above step S3 may be implemented by the following steps S31 and S32:
step S31: and blanket depositing a first dielectric layer, wherein the first dielectric layer covers the bottom surface and the side surface of the window of the split gate flash memory device and the upper surface of the hard mask layer.
Step S32: and etching the first dielectric layer by adopting an etching process, and reserving the first dielectric layer positioned on the side wall of the hard mask layer in the window of the split gate flash memory device to form a first isolation dielectric side wall.
Step S4: and etching to remove the exposed erasing gate layer at the window of the split gate flash memory device with the first isolation medium side wall.
Referring to fig. 5, a schematic cross-sectional structure of the device after completion of step S4 is shown. As can be seen in fig. 5, after etching to remove the erase gate layer 120 exposed at the split gate flash memory device window 200 with the first isolation medium sidewall 310, the floating gate layer 110 is exposed at the split gate flash memory device window 200.
Step S5: and forming a second isolation medium side wall on the side wall of the first isolation medium side wall in the window of the separation gate flash memory device, wherein the second isolation medium side wall covers the floating gate layer.
Referring to fig. 6, which is a schematic cross-sectional view of the device after the completion of step S5, as can be seen from fig. 6, a second isolation medium sidewall 321 is formed on the sidewall of the first isolation medium sidewall 310 in the split gate flash memory device window 200 shown in fig. 5, the second isolation medium sidewall 321 covers the floating gate layer 110, and the second isolation medium sidewall 321 also covers the side surface of the erase gate layer 120 exposed from the split gate flash memory device window 200.
Illustratively, the above step S5 may be implemented by the following steps S51 and S52:
step S51: and blanket depositing a second dielectric layer, wherein the second dielectric layer covers the side surface of the first isolation dielectric side wall, the upper surface of the hard mask layer and the floating gate layer exposed from the window of the split gate flash memory device.
Step S52: and etching the second dielectric layer by adopting an etching process, reserving the second dielectric layer covered on the side surface of the first isolation dielectric side wall to form a second isolation dielectric side wall, wherein the second isolation dielectric side wall is covered on the floating gate layer.
Step S6: forming a third isolation medium side wall on the side wall of the second isolation medium side wall, wherein the third isolation medium side wall covers the floating gate layer; the isolation gate flash memory device window with the first isolation medium side wall, the second isolation medium side wall and the third isolation medium side wall forms a source line filling window.
Referring to fig. 7, which shows a schematic cross-sectional structure of the device after the completion of step S6, it can be seen from fig. 7 that a third isolation medium sidewall 322 covers a side surface of the second isolation medium sidewall 321, and the second isolation medium sidewall 321 and the third isolation medium sidewall 322 are both located on the floating gate layer 110, so as to perform an isolation function between a source line and the floating gate layer. The third isolation medium sidewall 322 and the second isolation medium sidewall 321 together define an extension of the floating gate layer 110 with respect to the erase gate layer 120.
Preferably, the width of the second isolation medium sidewall 321 covering the floating gate layer 110 is 1100A to 1200A, and the width of the third isolation medium sidewall 322 covering the floating gate layer 110 is 200A to 300A.
In this embodiment, the second isolation medium side wall 321 and the third isolation medium side wall 322 are formed by two deposition processes and etching processes, so that the structures of the second isolation medium side wall 321 and the third isolation medium side wall 322 are steeper, and isolation requirements are met.
The second isolation medium side wall 321 and the third isolation medium side wall 322 jointly define the extension part of the floating gate layer 110 relative to the erase gate layer 120, and the second isolation medium side wall 321 and the third isolation medium side wall 322 are respectively formed through deposition and etching processes, so that the problem that the isolation medium layer is incompletely etched due to excessive thickness when the extension part is defined only through deposition and etching processes of a thicker isolation medium layer can be avoided.
Illustratively, the above step S6 may be implemented by the following steps S61 and S62:
step S61: and blanket depositing a third dielectric layer, wherein the third dielectric layer covers the side surface of the second isolation dielectric side wall, the upper surface of the hard mask layer and the exposed floating gate layer.
Step S62: etching the third dielectric layer by adopting an etching process, and reserving the third dielectric layer covered on the side surface of the second isolation dielectric side wall to form a third isolation dielectric side wall; the isolation gate flash memory device window with the first isolation medium side wall, the second isolation medium side wall and the third isolation medium side wall forms a source line filling window.
Step S7: and etching to remove the floating gate layer exposed from the source line filling window.
Referring to fig. 8, which shows a schematic cross-sectional structure of the device after completion of step S7, it can be seen from fig. 8 that the floating gate layer 110 exposed at the source line filling window 400 is etched away.
Step S8: and performing ion implantation based on the source line filling window, and forming a source doping region in the substrate layer below the source line filling window.
Referring to fig. 9, which shows a schematic cross-sectional structure of the device after completion of step S8, as can be seen from fig. 9, a source doping region VSS is formed in the substrate layer 100 under the source line filling window 400.
Step S9: and depositing a fourth isolation medium side wall and a source line polycrystalline silicon structure, wherein the source line polycrystalline silicon structure fills the source line filling window, and the fourth isolation medium side wall is positioned between the source line polycrystalline silicon structure and the side surface of the floating gate layer.
Referring to fig. 10, which is a schematic cross-sectional view of the device after the completion of step S9, as can be seen from fig. 10, the source line filling window 400 shown in fig. 9 is filled with a source line polysilicon structure 500, and the upper surface of the source line polysilicon structure 500 is planarized after chemical mechanical polishing is performed on the upper surface of the source line polysilicon structure 500. A fourth isolation medium sidewall 330 is formed between the source line polysilicon structure 500 and the side of the floating gate layer 110 exposed from the source line fill window 400.
The fourth isolation dielectric sidewall 330 isolates the source line polysilicon structure 500 from the floating gate layer 110.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (7)
1. The method for forming the split gate flash memory is characterized by comprising the following steps of:
providing a substrate layer, and forming a floating gate layer, an erasing gate layer and a hard mask layer on the substrate layer;
etching the hard mask layer to form a split gate flash memory device window;
forming a first isolation medium side wall on the side wall of the hard mask layer in the window of the split gate flash memory device;
etching to remove the exposed erasing gate layer at the window of the split gate flash memory device with the first isolation medium side wall;
forming a second isolation medium side wall on the side wall of the first isolation medium side wall in the window of the split gate flash memory device, wherein the second isolation medium side wall covers the floating gate layer;
forming a third isolation medium side wall on the side wall of the second isolation medium side wall, wherein the third isolation medium side wall covers the floating gate layer; the isolation gate flash memory device window with the first isolation medium side wall, the second isolation medium side wall and the third isolation medium side wall forms a source line filling window;
etching to remove the floating gate layer exposed from the source line filling window;
performing ion implantation based on the source line filling window, and forming a source doping region in the substrate layer below the source line filling window;
and depositing a fourth isolation medium side wall and a source line polycrystalline silicon structure, wherein the source line polycrystalline silicon structure fills the source line filling window, and the fourth isolation medium side wall is positioned between the source line polycrystalline silicon structure and the side surface of the floating gate layer.
2. The method for forming split gate flash memory as claimed in claim 1, wherein said step of forming a first isolation medium sidewall on a sidewall of said hard mask layer in said split gate flash memory device window comprises:
blanket depositing a first dielectric layer, wherein the first dielectric layer covers the bottom surface and the side surface of the window of the split gate flash memory device and the upper surface of the hard mask layer;
and etching the first dielectric layer by adopting an etching process, and reserving the first dielectric layer positioned on the side wall of the hard mask layer in the window of the split gate flash memory device to form a first isolation dielectric side wall.
3. The method for forming split gate flash memory of claim 1, wherein forming a second isolation medium sidewall on a sidewall of the first isolation medium sidewall in the split gate flash memory device window, the second isolation medium sidewall covering the floating gate layer, comprises:
a second dielectric layer is blanket deposited, and the second dielectric layer covers the side surface of the first isolation dielectric side wall, the upper surface of the hard mask layer and the floating gate layer exposed from the window of the split gate flash memory device;
and etching the second dielectric layer by adopting an etching process, reserving the second dielectric layer covered on the side surface of the first isolation dielectric side wall to form a second isolation dielectric side wall, wherein the second isolation dielectric side wall is covered on the floating gate layer.
4. The method for forming split gate flash memory of claim 1, wherein forming a third isolation medium sidewall on a sidewall of the second isolation medium sidewall, the third isolation medium sidewall covering the floating gate layer, comprises:
a third dielectric layer is deposited in a blanket mode, and the third dielectric layer covers the side face of the second isolation dielectric side wall, the upper surface of the hard mask layer and the exposed floating gate layer;
etching the third dielectric layer by adopting an etching process, and reserving the third dielectric layer covered on the side surface of the second isolation dielectric side wall to form a third isolation dielectric side wall; the isolation gate flash memory device window with the first isolation medium side wall, the second isolation medium side wall and the third isolation medium side wall forms a source line filling window.
5. The method of claim 1, wherein the second isolation dielectric sidewall and the third isolation dielectric sidewall overlying the floating gate layer define an extension of the floating gate layer relative to the erase gate layer.
6. The method of claim 1, wherein the second spacer is formed to cover the floating gate layer with a width of 1100A to 1200A.
7. The method of claim 1, wherein the third isolation medium sidewall covers the floating gate layer with a width of 200A to 300A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311371292.5A CN117677198A (en) | 2023-10-20 | 2023-10-20 | Forming method of split gate type flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311371292.5A CN117677198A (en) | 2023-10-20 | 2023-10-20 | Forming method of split gate type flash memory |
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| Publication Number | Publication Date |
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| CN117677198A true CN117677198A (en) | 2024-03-08 |
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| CN202311371292.5A Pending CN117677198A (en) | 2023-10-20 | 2023-10-20 | Forming method of split gate type flash memory |
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- 2023-10-20 CN CN202311371292.5A patent/CN117677198A/en active Pending
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