CN115985768A - Gate structure of high-power device and manufacturing method thereof - Google Patents

Abstract

The invention provides a grid structure of a high-power device and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate on which a gate oxide layer and a gate electrode are formed; forming a protective layer on the surface of the gate; forming a silicon oxide layer and a silicon nitride layer; forming a side wall structure; removing part of the side wall structures and part of the protective layers on two sides of the grid, and removing the grid oxide layers on two sides of the grid to expose corners of the bottom of the grid; and oxidizing the substrate and the bottom corner of the grid to obtain the grid with the smile appearance. This application is through getting rid of partial side wall structure and partial protective layer of grid both sides earlier in order to expose grid bottom corner, thereby carry out local oxidation to grid bottom corner and carry out the silicon oxide of bodiness grid bottom corner position in order to obtain the grid of smiling appearance, can avoid the wafer warpage when avoiding device electrical properties to change, avoid channel length to shorten, the controllability of grid has been improved, optimize C _j GIDL and non-lineAnd the harmonic performance is improved.

Description

Gate structure of high-power device and manufacturing method thereof

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a grid structure of a high-power device and a manufacturing method thereof.

Background

Gate oxide junction in high power deviceThe smiling face shape is beneficial to optimizing C _j (junction (inter-electrode) capacitance), GIDL (gate induced drain leakage current), and nonlinearity, thereby improving harmonic performance.

At present, the traditional gate oxide thickening method mainly comprises two methods: the first method is to increase the deposition thickness of the gate oxide layer by adjusting the process, but this results in the change of the electrical properties of the high-power device, and the subsequent ion implantation process needs to be adjusted correspondingly, which is complex and uncontrollable to operate; the second is to prolong the re-oxidation time of the polysilicon gate, but the long-time heat treatment will deteriorate the warping rate of the large-size wafer, reduce the yield of the high-power device and sacrifice the gate length, which results in the shortening of the channel length and the reduction of the control capability of the gate, and also results in the change of the electrical performance of the high-power device.

Disclosure of Invention

The application provides a grid structure of a high-power device and a manufacturing method thereof, which can solve the problem that the electrical property of the device is easily changed by the conventional method for preparing the grid oxide structure with the smiling face shape.

In one aspect, an embodiment of the present application provides a method for manufacturing a gate structure of a high power device, including:

providing a substrate, wherein a gate oxide layer covering the surface of the substrate and a gate positioned on the gate oxide layer are formed on the substrate;

oxidizing the grid to form a protective layer on the upper surface and the side surface of the grid;

sequentially forming a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer covers the protective layer and the surface of the gate oxide layer, and the silicon nitride layer covers the silicon oxide layer;

removing the silicon nitride layer and the silicon oxide layer on the substrate far away from the grid to obtain a side wall structure;

removing part of the side wall structure and part of the protective layer on two sides of the grid, and removing the gate oxide layers on two sides of the grid to form a groove, wherein the corner of the bottom of the grid is exposed at the moment;

and oxidizing the substrate and the bottom corners of the grid to respectively obtain a pad oxide layer and a smile-shaped grid, wherein the pad oxide layer covers the surface of the substrate far away from the grid.

Optionally, in the method for manufacturing the gate structure of the high-power device, the step of removing a portion of the sidewall structure and a portion of the protective layer on both sides of the gate to expose corners of the bottom of the gate includes:

and removing part of the side wall structures and part of the protective layer on two sides of the grid electrode by adopting a wet etching process, and removing the gate oxide layers on two sides of the grid electrode to form a groove, wherein the corner at the bottom of the grid electrode is exposed at the moment.

Optionally, in the manufacturing method of the gate structure of the high power device, after the substrate surface and the bottom corner of the gate are oxidized by using a thermal oxidation process to obtain the pad oxide layer and the gate with the smile morphology, respectively, the manufacturing method of the gate structure of the high power device further includes:

and forming a dielectric layer between the bottom of the side wall structure and the liner oxide layer by adopting an LPCVD (low pressure chemical vapor deposition) process so as to fill the groove.

Optionally, in the method for manufacturing the gate structure of the high-power device, in the process of oxidizing the gate to form the protective layer, the oxidation process time is 0s to 200s.

Optionally, in the method for manufacturing the gate structure of the high-power device, the thickness of the protective layer is less than or equal to that of the gate structure

Optionally, in the manufacturing method of the gate structure of the high-power device, a rapid thermal oxidation process is used to oxidize the substrate surface and the bottom corner of the gate to obtain the pad oxide layer and the smile-shaped gate, respectively.

Optionally, in the manufacturing method of the gate structure of the high-power device, in a process of oxidizing the substrate surface and the bottom corner of the gate by using a rapid thermal oxidation process, the oxidation process time is 10min to 30min, and the oxygen flow is 10SLM to 50SLM.

Optionally, in the manufacturing method of the gate structure of the high-power device, in a process of removing a part of the sidewall structure and a part of the protective layer on both sides of the gate by using a wet etching process to form a groove, an etching solution used in the method includes: DHF solution.

Optionally, in the manufacturing method of the gate structure of the high-power device, the substrate is a silicon substrate or a silicon-on-insulator.

On the other hand, the embodiment of the present application further provides a gate structure of a high power device, including:

a substrate;

the gate oxide layer is positioned on the substrate;

a gate overlying the gate oxide layer, wherein the gate has a smile appearance;

a protective layer covering an upper surface and a side surface of the gate electrode;

a silicon oxide layer covering the protective layer;

a silicon nitride layer overlying the silicon oxide layer; the protective layer, the silicon oxide layer and the silicon nitride layer on two sides of the grid electrode form a side wall structure;

the groove is positioned at the bottom of the side wall structure;

and the gasket oxide layer covers the substrate surfaces at two sides of the grid electrode.

The technical scheme at least comprises the following advantages:

this application is through getting rid of earlier the part of grid both sides side wall structure and part the protective layer, and get rid of the grid both sides the gate oxide is in order to expose grid bottom corner, then carry out the silicon oxide of local oxidation bodiness grid bottom corner position to grid bottom corner in order to obtain the grid of smiling appearance, can be avoiding device electricity performance to change with the grid that avoids device electricity performance to changeIn the process, the wafer is prevented from warping, the length of the grid is prevented from being sacrificed, so that the length of a channel is not shortened, the control capability of the grid is improved in a phase-changing manner, the yield of high-power devices is improved, and C is optimized _j GIDL and non-linearity improve harmonic performance.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flow chart of a method of fabricating a gate structure of a high power device of an embodiment of the present invention;

fig. 2-8 are schematic views of semiconductor structures at various process steps for fabricating a gate structure of a high power device according to an embodiment of the present invention;

wherein the reference numerals are as follows:

10-substrate, 11-bottom silicon layer, 12-middle silicon oxide layer, 13-top silicon layer, 20-gate oxide layer, 30-grid, 40-protective layer, 50-silicon oxide layer, 60-silicon nitride layer, 70-groove, 80-side wall structure, 91-pad oxide layer and 92-dielectric layer.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

The embodiment of the present application provides a method for manufacturing a gate structure of a high power device, and with reference to fig. 1 and fig. 2 to 8, fig. 1 is a flowchart of a method for manufacturing a gate structure of a high power device according to an embodiment of the present invention, and fig. 2 to 8 are schematic diagrams of semiconductor structures in various process steps of manufacturing a gate structure of a high power device according to an embodiment of the present invention.

The manufacturing method of the gate structure of the high-power device comprises the following steps:

step S10: as shown in fig. 2, a substrate 10 is provided, and a gate oxide layer 20 covering the surface of the substrate 10 and a gate 30 located on the gate oxide layer 20 are formed on the substrate 10. Specifically, the substrate 10 may be a silicon substrate, or may be a silicon-on-insulator.

In this embodiment, taking the substrate 10 as a silicon-on-insulator as an example, the substrate (silicon-on-insulator) 10 sequentially includes, from bottom to top: a bottom silicon layer 11, an intermediate silicon oxide layer 12 and a top silicon layer 13.

Step S20: as shown in fig. 3, the gate electrode 30 is oxidized to form a protective layer 40 on the upper surface and the side surface of the gate electrode 30. Specifically, the gate electrode 30 is oxidized by a thermal oxidation process, and in the process of oxidizing the gate electrode 30 to form the protective layer 40, the oxidation process time may be 50s to 200s, for example, 100s,150s. Further, the thickness of the protective layer 40 is less than or equal to

E.g. based on->

And so on.

Step S30: as shown in fig. 4, a silicon oxide layer 50 and a silicon nitride layer 60 are sequentially formed, wherein the silicon oxide layer 50 covers the protective layer 40 and the surface of the gate oxide layer 20, and the silicon nitride layer 60 covers the silicon oxide layer 50.

Step S40: as shown in fig. 5, the silicon nitride layer 60 and the silicon oxide layer 50 on the substrate 10 away from the gate 30 are removed to obtain a sidewall structure 80. The sidewall structures 80 are located at two sides of the gate 30.

Preferably, as can be seen from fig. 5, in the process of removing the silicon nitride layer 60 and the silicon oxide layer 50 on the substrate 10 away from the gate 30 to form the sidewall structure 80, the gate oxide layer 20 on the substrate 10 away from the gate 30 is also removed.

Step S50: as shown in fig. 6, removing a portion of the sidewall structure 80 and a portion of the protection layer 40 on the gate oxide layer 20 at two sides of the gate 30, and removing the gate oxide layer 20 at two sides of the gate 30 to form a groove 70, at which a bottom corner of the gate 30 is exposed. Specifically, in this embodiment, a wet etching process is adopted to remove a part of the sidewall structures 80 and a part of the protective layer 40 on both sides of the gate 30, and remove the gate oxide layer 20 on both sides of the gate 30 to form a groove 70, and at this time, the bottom corner of the gate 30 is exposed. That is, a wet etching process is used to remove a part of the sidewall structure 80 and a part of the protective layer 40 at the bottom position of the sidewall structure 80 (the top position of the gate oxide layer 20) on both sides of the gate 30; in addition, in the process of removing part of the sidewall structures 80 and part of the protective layer 40 on both sides of the gate 30 by using a wet etching process, the gate oxide layer 20 at the bottom of the sidewall structures 80 is also etched away.

Further, in the process of removing part of the sidewall structure 80 and part of the protective layer 40 on both sides of the gate 30 and removing the gate oxide layer 20 on both sides of the gate 30 to form the groove 70 by using a wet etching process, the etching solution used includes: DHF solution (diluted hydrofluoric acid solution); the etching solution used may also include SPM and APM, where SPM is H ₂ SO ₄ 、H ₂ O ₂ And H ₂ Mixed solution of O, APM being a proportion of NH ₄ OH solution and H ₂ O ₂ Mixed solution of the solutions.

Step S60: as shown in fig. 7, bottom corners of the substrate 10 and the gate 30 are oxidized to obtain a pad oxide layer 91 and a gate 30 with a smile shape, respectively, wherein the pad oxide layer 91 covers surfaces of the substrate 10 on two sides of the gate 30. The pad oxide layers 91 near both sides of the gate electrode 30 fill a part of the space of the groove 70.

Specifically, in this embodiment, a rapid thermal oxidation process is used to oxidize the surface of the substrate 10 and the bottom corner of the gate 30 to obtain the pad oxide layer 91 and the gate 30 with smile shape, respectively. In this embodiment, the bottom corner of the gate 30 is oxidized to oxidize the polysilicon material at the bottom corner of the gate 30 into a silicon oxide material, so that the silicon oxide at the bottom corner of the gate 30 is thickened, and now the thickness of the silicon oxide at the bottom corner of the gate 30 is the sum of the thickness of the oxidized polysilicon material at the corner and the thickness of the gate oxide layer 20 at the bottom, as can be seen from fig. 7, the oxidized gate at the bottom corner appears in a smiling face shape.

Further, in the process of oxidizing the surface of the substrate 10 and the bottom corner of the gate 30 by using a rapid thermal oxidation process, the oxidation process time may be 10min to 30min, for example, 15min,20min, and the like; the oxygen flow rate is 10SLM to 50SLM, for example, 15SLM,20SLM,30SLM,40SLM, etc.

In the application, the partial side wall structures 80 and the partial protective layer 40 on the two sides of the grid 30 are removed firstly to expose the bottom corners of the grid 30, then the bottom corners of the grid 30 are locally oxidized to thicken the silicon oxide at the bottom corners of the grid 30 so as to obtain the grid 30 with the smile appearance, so that a series of adverse consequences such as wafer warping, grid length narrowing, channel length shortening and the like caused in the traditional grid structure with the smile appearance can be avoided, the electrical performance of a device can be prevented from being changed, the control capability of the grid is improved, the yield of a high-power device is improved, and C is optimized _j GIDL and nonlinearity, improving the harmonic performance of the device.

Preferably, in this embodiment, after the substrate surface and the bottom corners of the gate are oxidized by a thermal oxidation process to obtain a pad oxide layer and a smile-shaped gate, respectively, the method for manufacturing the gate structure of the high power device may further include:

step S70: as shown in fig. 8, a dielectric layer 92 is formed between the bottom of the sidewall structure 80 and the liner oxide layer 91 by LPCVD to fill the recess 70.

Based on the same inventive concept, an embodiment of the present application further provides a gate structure of a high power device, as shown in fig. 7, the gate structure of the high power device includes:

a substrate 10, wherein the substrate 10 includes, in order from bottom to top: a bottom silicon layer 11, an intermediate silicon oxide layer 12, and a top silicon layer 13;

a gate oxide layer 20, wherein the gate oxide layer 20 is positioned on the substrate 10;

a gate 30, wherein the gate 30 covers the gate oxide layer 20, wherein the gate 20 has a smile appearance;

a protective layer 40, the protective layer 40 covering the upper surface and the side surfaces of the gate electrode 30;

a silicon oxide layer 50, the silicon oxide layer 50 covering the protective layer 40;

a silicon nitride layer 60, the silicon nitride layer 60 covering the silicon oxide layer 50; the protective layer 40, the silicon oxide layer 50 and the silicon nitride layer 60 on two sides of the gate 30 form a sidewall structure 80;

a groove 70, wherein the groove 70 is located at the bottom of the sidewall structure 80;

and the pad oxide layer 91, wherein the pad oxide layer 91 covers the surface of the substrate 10 on two sides of the gate 30.

Preferably, the gate structure of the high power device may further include: and a dielectric layer 92, wherein the dielectric layer 92 is located between the sidewall structure 80 and the pad oxide layer 91, and the dielectric layer 92 fills the groove 70.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention are intended to be covered by the present invention.

Claims (10)

1. A method for manufacturing a gate structure of a high-power device is characterized by comprising the following steps:

providing a substrate, wherein a gate oxide layer covering the surface of the substrate and a gate positioned on the gate oxide layer are formed on the substrate;

oxidizing the gate electrode to form a protective layer on the upper surface and the side surface of the gate electrode;

sequentially forming a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer covers the protective layer and the surface of the gate oxide layer, and the silicon nitride layer covers the silicon oxide layer;

removing the silicon nitride layer and the silicon oxide layer on the substrate far away from the grid to obtain a side wall structure;

removing part of the side wall structures and part of the protective layers on the two sides of the grid electrode, and removing the gate oxide layers on the two sides of the grid electrode to form a groove, wherein the corner of the bottom of the grid electrode is exposed at the moment;

and oxidizing the substrate and the bottom corner of the grid to respectively obtain a pad oxide layer and a smile-shaped grid, wherein the pad oxide layer covers the surface of the substrate far away from the grid.

2. The method for manufacturing the gate structure of the high power device according to claim 1, wherein the step of removing a portion of the sidewall structure and a portion of the protection layer on two sides of the gate to expose corners of the bottom of the gate includes:

and removing part of the side wall structures and part of the protective layer on two sides of the grid electrode by adopting a wet etching process, and removing the gate oxide layers on two sides of the grid electrode to form a groove, wherein the corner at the bottom of the grid electrode is exposed at the moment.

3. The method for manufacturing the gate structure of the high power device according to claim 2, wherein after the substrate surface and the bottom corners of the gate are oxidized by a thermal oxidation process to obtain the pad oxide layer and the smile-shaped gate, respectively, the method for manufacturing the gate structure of the high power device further comprises:

and forming a dielectric layer between the bottom of the side wall structure and the liner oxide layer by adopting an LPCVD (low pressure chemical vapor deposition) process so as to fill the groove.

4. The method for manufacturing the gate structure of the high power device according to claim 1, wherein an oxidation process time is 0s to 200s in the process of oxidizing the gate to form the protection layer.

5. The method for manufacturing a gate structure of a high power device according to claim 1, wherein the thickness of the protection layer is less than or equal to

6. The method for manufacturing the gate structure of the high power device according to claim 1, wherein a rapid thermal oxidation process is used to oxidize the substrate surface and the bottom corners of the gate to obtain the pad oxide layer and the smile-shaped gate, respectively.

7. The method for manufacturing the gate structure of the high power device according to claim 6, wherein in the process of oxidizing the substrate surface and the bottom corner of the gate by using a rapid thermal oxidation process, the oxidation process time is 10min to 30min, and the oxygen flow is 10SLM to 50SLM.

8. The method for manufacturing the gate structure of the high power device according to claim 2, wherein in the process of removing part of the sidewall structures and part of the protective layer at two sides of the gate by using a wet etching process to form the groove, an etching solution is used, and the etching solution comprises: DHF solution.

9. The method for manufacturing a gate structure of a high power device according to claim 1, wherein the substrate is a silicon substrate or a silicon-on-insulator.

10. A gate structure of a high power device, comprising:

a substrate;

the gate oxide layer is positioned on the substrate;

a gate overlying the gate oxide layer, wherein the gate has a smile appearance;

a protective layer covering an upper surface and a side surface of the gate electrode;

a silicon oxide layer covering the protective layer;

a silicon nitride layer overlying the silicon oxide layer; the protective layer, the silicon oxide layer and the silicon nitride layer on two sides of the grid electrode form a side wall structure;

the groove is positioned at the bottom of the side wall structure;

and the gasket oxide layer covers the substrate surfaces at two sides of the grid electrode.

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