CN112234024A - Method for rounding top angle of shallow trench isolation structure - Google Patents

Method for rounding top angle of shallow trench isolation structure Download PDF

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Publication number
CN112234024A
CN112234024A CN202011292942.3A CN202011292942A CN112234024A CN 112234024 A CN112234024 A CN 112234024A CN 202011292942 A CN202011292942 A CN 202011292942A CN 112234024 A CN112234024 A CN 112234024A
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Prior art keywords
shallow trench
silicon substrate
semiconductor silicon
groove
layer
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CN202011292942.3A
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Chinese (zh)
Inventor
邱元元
黄鹏
郭振强
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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Priority to CN202011292942.3A priority Critical patent/CN112234024A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a top angle rounding method of a shallow trench isolation structure. The method comprises the following steps: providing a semiconductor silicon substrate, and etching the semiconductor silicon substrate to form a shallow trench structure; forming a first oxide layer on the inner wall of the shallow trench structure; growing a silicon nitride layer on the surface of the first oxide layer of the shallow trench structure; filling an isolation medium layer into the shallow trench isolation structure with the silicon nitride layer; removing the silicon nitride layer positioned on the periphery of the top angle of the shallow trench structure, so that a height difference is formed between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed between the periphery of the top angle of the shallow trench structure and the isolation medium layer; removing the first oxide layer in the groove to expose the surface of the semiconductor silicon substrate in the groove; and reacting the semiconductor silicon substrate exposed in the groove with oxygen through a wet oxygen oxidation process, so that the semiconductor silicon substrate at the top corner of the shallow trench structure is rounded.

Description

Method for rounding top angle of shallow trench isolation structure
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a top angle rounding method of a shallow trench isolation structure.
Background
Due to the rapid development of CMOS technology and processes, CIS (complementary metal oxide semiconductor) chips, i.e., CMOS Image sensors, are widely used in the field of solid-state Image sensors.
In order to meet the requirements of computers, communication and consumer electronics, the performance of CIS products is required to be continuously improved, with the continuous improvement of the integration level of semiconductor integrated circuits, the size requirement of a pixel region of a CIS device is gradually reduced, and CIS products with smaller sizes are more sensitive to device leakage, wherein the cell region leakage can adversely affect the operating voltage and static loss performance of MOS of the CIS products.
Especially for CIS products with a thickness of 55nm or less, the reduction of the pixel region of the CIS products leads to an increase in the density of the active region, and further the Width of the MOS channel becomes small, which easily causes the electric field at the top corner position of the Shallow Trench Isolation (STI) to be concentrated, thereby causing reverse narrow channel Effect (RNWE), and further requiring the top corner position of the STI to be rounded, so as to reduce the problem of electric leakage at the top corner position due to the electric field concentration.
However, In the development process of products with a diameter of 55nm or less, the STI structure is usually formed by filling oxide generated by an In-Situ Steam process (ISSG), but the STI structure manufactured by the ISSG process has an insignificant top angle rounding effect and cannot meet the CIS development requirement of 55 nm.
Disclosure of Invention
The application provides a top angle rounding method of a shallow trench isolation structure, which can solve the problem that the top angle rounding effect is not obvious in the related technology.
The application provides a method for rounding a top angle of a shallow trench isolation structure, which is characterized by comprising the following steps:
providing a semiconductor silicon substrate, and etching the semiconductor silicon substrate to form a shallow trench structure;
forming a first oxidation layer on the inner wall of the shallow trench structure;
growing a silicon nitride layer on the surface of the first oxide layer of the shallow trench structure;
filling an isolation medium layer into the shallow trench isolation structure with the silicon nitride layer;
removing the silicon nitride layer positioned on the periphery of the top angle of the shallow trench structure, so that a height difference is formed between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed between the periphery of the top angle of the shallow trench structure and the isolation medium layer;
removing the first oxide layer in the groove to expose the surface of the semiconductor silicon substrate in the groove;
and reacting the semiconductor silicon substrate exposed in the groove with oxygen through a wet oxygen oxidation process, so that the semiconductor silicon substrate at the top corner of the shallow trench structure is rounded.
Optionally, the silicon nitride layer on the periphery of the top angle of the shallow trench structure is removed, so that a height difference is formed between the top end of the remaining silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed between the periphery of the top angle of the shallow trench structure and the isolation medium layer; the method comprises the following steps:
and etching and removing the silicon nitride layer attached to the periphery of the top angle of the isolation medium layer by using a first wet etching agent, so that a height difference is formed between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed on the periphery of the top angle of the isolation medium layer.
Optionally, the first wet etchant comprises hot phosphoric acid.
Optionally, the step of removing the first oxide layer in the groove to expose the surface of the semiconductor silicon substrate in the groove includes:
and etching the first oxide layer in the groove by using a second wet etching agent so as to expose the surface of the semiconductor silicon substrate in the groove.
Optionally, the second wet etchant comprises hydrofluoric acid.
Optionally, when the first oxide layer located in the groove is etched by using the second wet etchant containing hydrofluoric acid, the first oxide layer located on the surface of the semiconductor silicon substrate is also etched and removed.
Optionally, in the step of making the semiconductor silicon substrate exposed in the groove react with oxygen through a wet oxidation process to round the semiconductor silicon substrate at the top corner of the shallow trench structure, the wet oxidation process includes:
enabling the semiconductor silicon substrate exposed in the groove to react with oxygen by adopting a wet oxygen oxidation process, thereby consuming part of silicon of the semiconductor silicon substrate to form a second oxidation layer; and rounding the semiconductor silicon substrate at the vertex angle position of the shallow trench structure under the action of oxidation reaction to form a smooth vertex angle.
The technical scheme at least comprises the following advantages: removing the silicon nitride layer positioned on the periphery of the top angle of the shallow trench structure to form a height difference between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, so that a groove is formed between the periphery of the top angle of the shallow trench structure and the isolation medium layer; removing the first oxide layer in the groove to expose the surface of the semiconductor silicon substrate in the groove; the semiconductor silicon substrate exposed in the groove is reacted with oxygen through a wet oxygen oxidation process, the semiconductor silicon substrate at the vertex angle position of the shallow trench structure is rounded, and the depth of the groove is controlled, namely the height difference is formed between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, so that the fillet of the shallow trench isolation structure meeting various requirements can be effectively formed
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a flowchart of a method for rounding a top corner of a shallow trench isolation structure according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating a cross-sectional structure of a semiconductor silicon substrate with a shallow trench structure formed after step S1 is completed;
fig. 3 shows a schematic cross-sectional structure of the device after step S2 is completed;
fig. 4 shows a schematic cross-sectional structure of the device after step S3 is completed;
fig. 5 shows a schematic cross-sectional structure of the device after step S4 is completed;
fig. 6 shows a schematic cross-sectional structure of the device after step S5 is completed;
FIG. 6A shows an enlarged schematic view of portion A of FIG. 6;
fig. 7 shows a schematic cross-sectional structure of the device after step S6 is completed;
FIG. 7A is an enlarged schematic view of portion A of FIG. 7;
fig. 8 shows a schematic cross-sectional structure of the device after step S7 is completed;
FIG. 8A is an enlarged schematic view of portion A of FIG. 8;
fig. 9 shows a schematic cross-sectional structure of the device after completion of step S8;
fig. 9A shows an enlarged schematic structure of a portion a in fig. 9.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 schematically illustrates a top corner rounding method of a shallow trench isolation structure according to an embodiment of the present application, and referring to fig. 1, the top corner rounding method of the shallow trench isolation structure includes:
step S1: and providing a semiconductor silicon substrate, and etching the semiconductor silicon substrate to form a shallow trench structure.
Fig. 2 shows a schematic cross-sectional structure of the semiconductor silicon substrate 110 with the shallow trench structures 120 formed after step S1 is completed, the semiconductor silicon substrate 110 including opposite upper and lower surfaces, the shallow trench structures 120 extending downward from the upper surface of the semiconductor silicon substrate 110.
Step S2: and forming a first oxidation layer on the inner wall of the shallow trench structure.
In this embodiment, the surface of the semiconductor silicon substrate 110 shown in fig. 2 may be oxidized by an ISSG process, so that a first oxide layer 130 is formed on the inner wall of the shallow trench structure 120 and the upper surface of the semiconductor silicon substrate 11, thereby forming the cross-sectional structure shown in fig. 3. When the shallow trench structure 120 is formed by etching, the etched surface of the shallow trench structure 120 may be damaged, and if an isolation medium is directly filled in the damaged shallow trench structure 120, the isolation medium may easily fall off.
Step S3: and growing a silicon nitride layer on the surface of the first oxide layer of the shallow trench structure.
In this embodiment, a silicon nitride layer 140 may be deposited on the first oxide layer 130 on the inner wall of the shallow trench structure 120 shown in fig. 3 by a Low Pressure Chemical Vapor Deposition (LPCVD) process. Referring to fig. 4, the first oxide layer 130 formed in step S2 and the silicon nitride layer 140 formed in step S4 are sequentially disposed on the inner wall of the shallow trench structure 120 in fig. 4 after the step S3 is completed
Step S4: and filling an isolation medium layer into the shallow trench isolation structure.
In this embodiment, the material of the shallow trench isolation structure should be an insulating material. Referring to fig. 5, the schematic cross-sectional structure of the device after the step S4 is completed, in fig. 5, the silicon nitride layer 140 is attached between the first oxide layer 130 and the peripheral side of the isolation dielectric layer 150.
Step S5: and removing the silicon nitride layer on the periphery of the vertex angle of the shallow trench structure, so that a height difference is formed between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed between the periphery of the vertex angle of the shallow trench structure and the isolation medium layer.
This embodiment may use hot phosphoric acid as the first wet etchant, dissolve silicon nitride by reacting the hot phosphoric acid with silicon nitride, and control the etching depth by controlling the hot phosphoric acid cleaning time, i.e., the wet etching time, so that a height difference h is formed between the top of the remaining silicon nitride layer and the upper surface of the semiconductor silicon substrate as shown in fig. 6A. Fig. 6 is a schematic cross-sectional view of the device after step S5 is completed, fig. 6A is an enlarged schematic view of a portion a in fig. 6, and as shown in fig. 6A, after step S5 is completed, the silicon nitride layer 140 located on the periphery of the top corner 160 of the shallow trench structure 120 is etched and removed, a height difference h is formed between the top of the remaining silicon nitride layer 140 and the upper surface of the semiconductor silicon substrate 110, and a groove 170 is formed between the periphery of the top corner 160 of the shallow trench structure 120 and the isolation dielectric layer 150.
Step S6: and removing the first oxide layer in the groove to expose the surface of the semiconductor silicon substrate in the groove.
Fig. 7 is a schematic cross-sectional view of the device after step S6 is completed, and fig. 7A is an enlarged view of a portion a in fig. 7, as shown in fig. 7A, after step S6 is completed, the first oxide layer 130 in the recess 170 is removed, so that the surface of the semiconductor silicon substrate 110 in the recess 170 is exposed. As can be seen with reference to fig. 7A and 7, in the process of removing the first oxide layer 130 located in the recess 170, the first oxide layer covering the surface of the semiconductor silicon substrate 110 in fig. 6 and 6A is also etched away.
In this embodiment, hydrofluoric acid may be used as the second wet etchant to etch the first oxide layer in the groove and the first oxide layer covering the surface of the semiconductor silicon substrate, so that the surface of the semiconductor silicon substrate including the semiconductor silicon substrate in the groove is exposed, that is, the surface of the semiconductor silicon substrate at the vertex angle of the shallow trench structure is exposed.
Step S7: and reacting the semiconductor silicon substrate exposed in the groove with oxygen through a wet oxygen oxidation process, so that the semiconductor silicon substrate at the top corner of the shallow trench structure is rounded.
Since the surface of the semiconductor silicon substrate in the groove is exposed after the step S6 is completed, that is, the surface of the semiconductor silicon substrate at the vertex angle of the shallow trench structure is exposed, silicon atoms in the exposed semiconductor silicon substrate actively react with oxygen through a wet oxygen oxidation process, thereby consuming part of silicon to form a second oxide layer, which becomes to include silicon dioxide. Particularly, the semiconductor silicon substrate at the vertex angle position of the shallow trench structure is rounded to form a smooth vertex angle under the action of oxidation reaction.
Fig. 8 is a schematic cross-sectional view of the device after step S7 is completed, and fig. 8A is an enlarged view of a portion a in fig. 8, as shown in fig. 8A, after the wet oxidation process, a second oxide layer 180 is formed on the surface of the exposed semiconductor silicon substrate shown in fig. 7 and 7A, and the semiconductor silicon substrate 110 at the vertex 160 of the shallow trench structure 120 reacts with oxygen to form a rounded vertex 160. Therefore, the rounding of the top angle of the shallow trench isolation structure is realized, the concentration of a grid electric field at the top angle due to a sharp top angle is prevented, and the problem of electric leakage at the edge of the shallow trench isolation structure can be effectively prevented.
After step S7 is completed, step S8 may be performed: and removing the oxide layer formed by the wet oxidation process in the step S7 by wet etching, and forming a gate oxide layer and gate polysilicon on the semiconductor silicon substrate. And an oxide layer formed by a wet-oxygen oxidation process can be removed by cleaning with hydrofluoric acid, and the position of the isolation dielectric layer close to the vertex angle can be etched to form a recess in the process.
Fig. 9 shows a schematic cross-sectional structure of the device after step S8 is completed, and fig. 9A is an enlarged schematic structural view of a portion a in fig. 9. Referring to fig. 9 and 9A, in step S8, after the wet etching is performed to remove the oxide layer formed by the wet oxidation process in step S7, the isolation dielectric layer 150 is etched to form a recess 190 at a position close to the top corner 160, and after the oxide layer is removed, the semiconductor silicon substrate 110 at the top corner 160 of the shallow trench structure 120 is exposed. In the subsequent chemical mechanical polishing step, the recess 190 can be polished to a certain extent, thereby completing the top angle rounding process of the shallow trench isolation structure.
In the embodiment, the silicon nitride layer positioned on the periphery of the top angle of the shallow trench structure is removed firstly, so that a height difference is formed between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed between the periphery of the top angle of the shallow trench structure and the isolation medium layer; removing the first oxide layer in the groove to expose the surface of the semiconductor silicon substrate in the groove; and reacting the semiconductor silicon substrate exposed in the groove with oxygen through a wet oxygen oxidation process to round the semiconductor silicon substrate at the vertex angle position of the shallow trench structure, and controlling the depth of the groove, namely forming a height difference between the top of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, so that a shallow trench isolation structure fillet meeting various requirements can be effectively formed.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (7)

1. The method for rounding the top angle of the shallow trench isolation structure is characterized by comprising the following steps of:
providing a semiconductor silicon substrate, and etching the semiconductor silicon substrate to form a shallow trench structure;
forming a first oxidation layer on the inner wall of the shallow trench structure;
growing a silicon nitride layer on the surface of the first oxide layer of the shallow trench structure;
filling an isolation medium layer into the shallow trench isolation structure with the silicon nitride layer;
removing the silicon nitride layer positioned on the periphery of the top angle of the shallow trench structure, so that a height difference is formed between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed between the periphery of the top angle of the shallow trench structure and the isolation medium layer;
removing the first oxide layer in the groove to expose the surface of the semiconductor silicon substrate in the groove;
and reacting the semiconductor silicon substrate exposed in the groove with oxygen through a wet oxygen oxidation process, so that the semiconductor silicon substrate at the top corner of the shallow trench structure is rounded.
2. The method for rounding the top angle of a shallow trench isolation structure according to claim 1, wherein the silicon nitride layer on the periphery of the top angle of the shallow trench isolation structure is removed, so that a height difference is formed between the top end of the remaining silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed between the periphery of the top angle of the shallow trench isolation structure and the isolation medium layer; the method comprises the following steps:
and etching and removing the silicon nitride layer attached to the periphery of the top angle of the isolation medium layer by using a first wet etching agent, so that a height difference is formed between the top end of the residual silicon nitride layer and the upper surface of the semiconductor silicon substrate, and a groove is formed on the periphery of the top angle of the isolation medium layer.
3. The method for rounding top corner of shallow trench isolation structure of claim 2 wherein said first wet etchant comprises hot phosphoric acid.
4. The method for rounding the top corner of a shallow trench isolation structure of claim 1, wherein the step of removing the first oxide layer in the recess to expose the surface of the semiconductor silicon substrate in the recess comprises:
and etching the first oxide layer in the groove by using a second wet etching agent so as to expose the surface of the semiconductor silicon substrate in the groove.
5. The method for rounding top corner of shallow trench isolation structure of claim 4 wherein said second wet etchant comprises hydrofluoric acid.
6. The method for rounding top corner of shallow trench isolation structure of claim 5 wherein said second wet etchant comprising hydrofluoric acid is used to etch the first oxide layer in said recess, the first oxide layer on the surface of the semiconductor silicon substrate is also etched away.
7. The method for rounding the top corner of a shallow trench isolation structure according to claim 1, wherein the step of rounding the semiconductor silicon substrate at the position of the top corner of the shallow trench isolation structure by reacting the semiconductor silicon substrate exposed in the recess with oxygen through a wet oxidation process comprises:
enabling the semiconductor silicon substrate exposed in the groove to react with oxygen by adopting a wet oxygen oxidation process, thereby consuming part of silicon of the semiconductor silicon substrate to form a second oxidation layer; and rounding the semiconductor silicon substrate at the vertex angle position of the shallow trench structure under the action of oxidation reaction to form a smooth vertex angle.
CN202011292942.3A 2020-11-18 2020-11-18 Method for rounding top angle of shallow trench isolation structure Pending CN112234024A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594085A (en) * 2021-07-12 2021-11-02 长鑫存储技术有限公司 Method for manufacturing semiconductor structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1293452A (en) * 1999-10-12 2001-05-02 三星电子株式会社 Channel isolating structure, semi conductor device possessing said structure and channel isolating method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1293452A (en) * 1999-10-12 2001-05-02 三星电子株式会社 Channel isolating structure, semi conductor device possessing said structure and channel isolating method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594085A (en) * 2021-07-12 2021-11-02 长鑫存储技术有限公司 Method for manufacturing semiconductor structure
WO2023283973A1 (en) * 2021-07-12 2023-01-19 长鑫存储技术有限公司 Method for preparing semiconductor structure
CN113594085B (en) * 2021-07-12 2023-10-03 长鑫存储技术有限公司 Method for manufacturing semiconductor structure

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