CN115548105A - Method for manufacturing shielding trench gate - Google Patents

Method for manufacturing shielding trench gate Download PDF

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Publication number
CN115548105A
CN115548105A CN202211165232.3A CN202211165232A CN115548105A CN 115548105 A CN115548105 A CN 115548105A CN 202211165232 A CN202211165232 A CN 202211165232A CN 115548105 A CN115548105 A CN 115548105A
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China
Prior art keywords
thermal oxidation
layer
etching
dielectric layer
semiconductor substrate
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Pending
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CN202211165232.3A
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Chinese (zh)
Inventor
张蕾
潘嘉
陈正嵘
吴长明
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
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Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp, Hua Hong Semiconductor Wuxi Co Ltd filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202211165232.3A priority Critical patent/CN115548105A/en
Publication of CN115548105A publication Critical patent/CN115548105A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Element Separation (AREA)

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a shielding trench gate. The manufacturing method of the shielding trench gate comprises the following steps: defining a groove pattern on a semiconductor substrate by using an oxide as a mask layer; etching the semiconductor substrate based on the groove pattern, and forming a groove structure in the semiconductor substrate; removing the mask layer to expose the upper surface of the semiconductor substrate; forming a thermal oxidation layer on the surface of the semiconductor substrate by a thermal oxidation process, wherein the thermal oxidation layer covers the inner wall of the groove structure and the exposed upper surface of the semiconductor substrate; filling polycrystalline silicon into the trench structure covered with the thermal oxidation layer; etching to remove the upper part of the polycrystalline silicon, so that the thermal oxidation layer positioned on the upper part of the groove structure is exposed; for the thermal oxidation layer covering the upper part of the groove structure, etching from the inner wall of the thermal oxidation layer to remove part of the thermal oxidation layer; depositing a backfill dielectric layer to fill the upper part of the trench structure; and back-etching the backfill dielectric layer.

Description

Method for manufacturing shielding trench gate
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a shielding trench gate.
Background
In the related art, when a shield trench gate is manufactured, a trench pattern is defined by using an Oxide-Nitride-Oxide (ONO) composite layer as a hard mask, then etching is performed based on the trench pattern to form a shield gate trench, then a shield gate dielectric layer is formed, the shield gate dielectric layer covers the side wall of the shield gate trench and the hard mask positioned at the opening of the shield gate trench, then a polycrystalline silicon layer is filled, and finally the shield trench gate is formed through subsequent etching and backfilling processes.
However, in the manufacturing method of the shield trench gate in the related art, the formed shield gate dielectric layer is easy to form a closed opening at the shield gate trench opening, which is not beneficial to subsequent polysilicon filling and is easy to cause a void problem.
Disclosure of Invention
The application provides a manufacturing method of a shielding groove gate, which can solve the problem that a deposited shielding gate dielectric layer is easy to form a closed opening at an opening of a shielding groove gate in the related technology.
In order to solve the technical problems described in the background art, the present application provides a method for manufacturing a shielded trench gate, including the steps of:
defining a groove pattern on a semiconductor substrate by using an oxide as a mask layer;
etching the semiconductor substrate based on the groove pattern to form a groove structure in the semiconductor substrate;
removing the mask layer to expose the upper surface of the semiconductor substrate;
forming a thermal oxidation layer on the surface of the semiconductor substrate through a thermal oxidation process, wherein the thermal oxidation layer covers the inner wall of the groove structure and the exposed upper surface of the semiconductor substrate;
filling polycrystalline silicon into the trench structure covered with the thermal oxidation layer;
etching and removing the upper part of the polycrystalline silicon to expose the thermal oxidation layer positioned on the upper part of the groove structure;
for the thermal oxidation layer covering the upper part of the groove structure, etching and removing part of the thermal oxidation layer from the inner wall of the thermal oxidation layer;
depositing a backfill dielectric layer to fill the upper part of the trench structure;
and back-etching the backfill dielectric layer.
Optionally, for the thermal oxide layer covering the upper portion of the trench structure, the step of removing a portion of the thermal oxide layer by etching from the inner wall of the thermal oxide layer includes:
and for the thermal oxidation layer covering the upper part of the groove structure, etching and removing part of the thermal oxidation layer from the inner wall of the thermal oxidation layer, and exposing the top of the residual polycrystalline silicon.
Optionally, the step of depositing a backfill dielectric layer to fill the upper portion of the trench structure includes:
depositing a backfill dielectric layer to fill the upper part of the groove structure, wherein the backfill dielectric layer wraps the exposed top of the residual polysilicon.
Optionally, for the thermal oxide layer covering the upper portion of the trench structure, the step of etching away a portion of the thermal oxide layer from the inner wall of the thermal oxide layer includes:
and etching the thermal oxidation layer covering the upper part of the groove structure by a wet etching method to remove part of the thermal oxidation layer from the inner wall of the thermal oxidation layer.
Optionally, the step of depositing a backfill dielectric layer to fill the upper portion of the trench structure includes:
depositing a backfill medium with the thickness of 10000-20000A on the upper part of the trench structure to fill the upper part of the trench structure.
Optionally, the step of back-etching the back-filling dielectric layer includes:
and back-etching the backfill dielectric layer by a wet process, so that the height of the residual backfill dielectric layer higher than the top end of the residual polycrystalline silicon is 2000-4000A, and the residual backfill dielectric layer wraps the exposed top of the residual polycrystalline silicon.
Optionally, the step of depositing a backfill dielectric layer to fill the upper portion of the trench structure includes:
and depositing a backfill dielectric layer to fill the upper part of the trench structure by a high-density plasma deposition process. The technical scheme at least comprises the following advantages: the mask layer made of silicon oxide is removed before the subsequent thermal oxide layer forming process, so that the problem that the polycrystalline silicon deposition is influenced by the closing formed at the opening of the shield gate trench by the subsequent thermal oxide layer can be avoided.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flow chart illustrating a method for manufacturing a shielded trench gate according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of a part of the device after step S4 is completed;
FIG. 3 is a schematic cross-sectional view of the device after step S5 is completed;
FIG. 4 is a schematic cross-sectional structural diagram of the device after step S6 is completed;
FIG. 5 is a schematic cross-sectional structural diagram of the device after step S7 is completed;
FIG. 6 is a schematic cross-sectional structural diagram of the device after step S8 is completed;
fig. 7 shows a schematic cross-sectional structural diagram of the device after step S8 is completed.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 shows a flowchart of a method for manufacturing a shielded trench gate according to an embodiment of the present application, and as can be seen from fig. 1, the method for manufacturing a shielded trench gate includes the following steps S1 to S9 performed in sequence:
step S1: a trench pattern is defined on a semiconductor substrate by using an oxide as a mask layer.
The semiconductor substrate can be a semiconductor silicon substrate made of silicon, wherein silicon oxide with the thickness of 6000-8000A (angstroms) is deposited on the semiconductor substrate to be used as a mask layer, and then the mask layer is etched through a photoetching process, so that a groove pattern is defined on the mask layer.
Step S2: and etching the semiconductor substrate based on the groove pattern to form a groove structure in the semiconductor substrate.
The semiconductor substrate may be dry etched based on the trench pattern to form a trench structure extending downward from the upper surface of the semiconductor substrate at the location of the trench pattern.
And step S3: and removing the mask layer to expose the upper surface of the semiconductor substrate.
The mask layer made of silicon oxide can be removed by wet chemical liquid, so that the upper surface of the semiconductor substrate is exposed.
According to the embodiment, the mask layer made of silicon oxide is removed before the subsequent thermal oxidation layer forming process, so that the problem that polycrystalline silicon deposition is influenced by the closing formed at the opening of the shield gate trench by the subsequent thermal oxidation layer can be avoided.
And step S4: and forming a thermal oxidation layer on the surface of the semiconductor substrate by a thermal oxidation process, wherein the thermal oxidation layer covers the inner wall of the groove structure and the exposed upper surface of the semiconductor substrate.
Referring to fig. 2, which shows a schematic cross-sectional structure of a part of the device after step S4 is completed, it can be seen from fig. 2 that a thermal oxide layer 210 covers the inner wall of the trench structure and the exposed upper surface of the semiconductor substrate 100, so as to form a first accommodating space 211 in the trench structure.
Optionally, the thickness of the thermal oxide layer covering the inner wall of the trench structure may be 4000 to 7500A by a thermal oxidation process.
Step S5: and filling polycrystalline silicon into the trench structure covered with the thermal oxidation layer.
Referring to fig. 3, which shows a schematic cross-sectional structure of the device after step S5 is completed, it can be seen from fig. 3 that the first accommodating space 211 shown in fig. 2 is filled with polysilicon 300.
Step S6: and etching and removing the upper part of the polycrystalline silicon, so that the thermal oxidation layer positioned on the upper part of the groove structure is exposed.
The upper part of the polycrystalline silicon can be etched and removed through a plasma dry etching process, so that the thermal oxidation layer positioned on the upper part of the groove structure is exposed.
Referring to fig. 4, which shows a schematic cross-sectional structure of the device after step S6 is completed, it can be seen from fig. 4 that after step S6 is completed, the upper portion of the polysilicon 300 is etched away, and the thermal oxide layer 210 on the upper portion of the trench structure is exposed.
Step S7: and for the thermal oxidation layer covering the upper part of the trench structure, etching and removing part of the thermal oxidation layer from the inner wall of the thermal oxidation layer.
Referring to fig. 5, which shows a schematic cross-sectional structure of the device after step S7 is completed, as can be seen from fig. 5, the thermal oxide layer 210 covering the upper portion of the trench structure shown in fig. 4 is partially etched away to form the structure shown in fig. 5, a thickness W1 of the remaining thermal oxide layer 210 on the upper portion of the trench structure is 1000 to 3000A, and the remaining thermal oxide layer 210 covers the upper portion of the trench structure, so that the upper sidewall of the trench structure can be protected to prevent the upper sidewall of the trench structure from being damaged by a subsequent process. Meanwhile, the depth-to-width ratio of the filled back filling dielectric layer can be increased.
After step S7 is completed, a second accommodating space 212 is formed at the upper portion of the trench structure, the sidewall of the second accommodating space 212 is covered with the remaining thin thermal oxide layer 210, and the thermal oxide layer 210 at the bottom end of the second accommodating space 212 is lower than the top end of the polysilicon 300, so that the top of the remaining polysilicon 300 in fig. 4 is exposed to form the structure shown in fig. 5.
Optionally, a portion of the thermal oxide layer covering the upper portion of the trench structure may be removed by etching from an inner wall of the thermal oxide layer through a wet etching process.
Step S8: and depositing a backfill dielectric layer to fill the upper part of the trench structure.
A backfill dielectric layer can be deposited through a high-density plasma deposition process to fill the upper portion of the groove structure.
It can be understood that, because the sidewall of the second accommodating space 212 is covered with the remaining thermal oxide layer 210 after the step S7 is completed, when the backfill dielectric layer is deposited by the high-density plasma deposition process, the sidewall of the second accommodating space 212 can be prevented from being damaged by the high-density plasma deposition process, and the deposition process has a larger filling aspect ratio. And the filled backfill dielectric layer wraps the exposed top of the residual polysilicon.
Referring to fig. 6, which shows a schematic cross-sectional structure of the device after step S8 is completed, it can be seen from fig. 6 that the backfill dielectric layer 600 fills the second accommodating space 212, and the backfill dielectric layer 600 wraps the exposed top of the remaining polysilicon 300.
In this embodiment, a backfill medium with a thickness of 10000 to 20000A may be deposited on the upper portion of the trench structure to fill the upper portion of the trench structure.
Step S9: and back-etching the backfill dielectric layer.
In this embodiment, the backfill dielectric layer may be etched back by a wet process, so that the remaining backfill dielectric layer wraps the exposed top of the remaining polysilicon.
Referring to fig. 7, which shows a schematic cross-sectional structure of the device after step S8 is completed, it can be seen that after the backfill dielectric layer 600 is etched back, the remaining backfill dielectric layer 600 wraps the exposed top of the remaining polysilicon, wherein a height h1 of the remaining backfill dielectric layer 600 above the top of the remaining polysilicon 300 may be 2000-4000A.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (7)

1. A manufacturing method of a shielding trench gate is characterized by comprising the following steps:
defining a groove pattern on a semiconductor substrate by using an oxide as a mask layer;
etching the semiconductor substrate based on the groove pattern to form a groove structure in the semiconductor substrate;
removing the mask layer to expose the upper surface of the semiconductor substrate;
forming a thermal oxidation layer on the surface of the semiconductor substrate through a thermal oxidation process, wherein the thermal oxidation layer covers the inner wall of the groove structure and the exposed upper surface of the semiconductor substrate;
filling polycrystalline silicon into the trench structure covered with the thermal oxidation layer;
etching and removing the upper part of the polycrystalline silicon to expose the thermal oxidation layer positioned on the upper part of the groove structure;
for the thermal oxidation layer covering the upper part of the trench structure, etching from the inner wall of the thermal oxidation layer to remove part of the thermal oxidation layer;
depositing a backfill dielectric layer to fill the upper part of the trench structure;
and back-etching the backfill dielectric layer.
2. The method of manufacturing a shielded trench gate as claimed in claim 1 wherein said step of etching away a portion of said thermal oxide layer from an inner wall of said thermal oxide layer for said thermal oxide layer overlying said trench structure comprises:
and for the thermal oxidation layer covering the upper part of the groove structure, etching and removing part of the thermal oxidation layer from the inner wall of the thermal oxidation layer, and exposing the top of the residual polycrystalline silicon.
3. The method of manufacturing a shielded trench gate as claimed in claim 2 wherein said step of depositing a backfill dielectric layer to fill an upper portion of said trench structure comprises:
depositing a backfill dielectric layer to fill the upper part of the groove structure, wherein the backfill dielectric layer wraps the exposed top of the residual polysilicon.
4. The method of manufacturing a shielded trench gate as claimed in claim 1 wherein said step of etching away a portion of said thermal oxide layer from an inner wall of said thermal oxide layer for said thermal oxide layer overlying said trench structure comprises:
and etching the thermal oxidation layer covering the upper part of the groove structure by a wet etching method to remove part of the thermal oxidation layer from the inner wall of the thermal oxidation layer.
5. The method of claim 1, wherein said step of depositing a backfill dielectric layer to fill an upper portion of said trench structure comprises:
depositing a backfill medium with the thickness of 10000-20000A on the upper part of the trench structure to fill the upper part of the trench structure.
6. The method of manufacturing a shielded trench gate as claimed in claim 5 wherein said step of back-etching said back-fill dielectric layer comprises:
and back-etching the backfill dielectric layer by a wet process, so that the height of the residual backfill dielectric layer higher than the top end of the residual polycrystal is 2000-4000A.
7. The method of claim 1, wherein said step of depositing a backfill dielectric layer to fill an upper portion of said trench structure comprises:
and depositing a backfill dielectric layer to fill the upper part of the trench structure by a high-density plasma deposition process.
CN202211165232.3A 2022-09-23 2022-09-23 Method for manufacturing shielding trench gate Pending CN115548105A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211165232.3A CN115548105A (en) 2022-09-23 2022-09-23 Method for manufacturing shielding trench gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211165232.3A CN115548105A (en) 2022-09-23 2022-09-23 Method for manufacturing shielding trench gate

Publications (1)

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CN115548105A true CN115548105A (en) 2022-12-30

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