CN114883243A - Semiconductor memory structure and preparation method - Google Patents

Semiconductor memory structure and preparation method Download PDF

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Publication number
CN114883243A
CN114883243A CN202210427201.4A CN202210427201A CN114883243A CN 114883243 A CN114883243 A CN 114883243A CN 202210427201 A CN202210427201 A CN 202210427201A CN 114883243 A CN114883243 A CN 114883243A
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layer
groove
dielectric layer
dielectric
substrate
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赖惠先
冯立伟
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Fujian Jinhua Integrated Circuit Co Ltd
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Fujian Jinhua Integrated Circuit Co Ltd
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Priority to CN202210427201.4A priority Critical patent/CN114883243A/en
Publication of CN114883243A publication Critical patent/CN114883243A/en
Priority to US18/078,075 priority patent/US20230345724A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application discloses a semiconductor memory structure and a preparation method thereof, which can eliminate grooves generated in the process of filling various material layers in a groove and improve the yield of a semiconductor memory. The semiconductor memory structure includes: a substrate; the first groove is positioned on the upper surface of the substrate, and the edge angle of the top of the first groove is arc-shaped; the first dielectric layer is distributed along the inner wall of the first groove; the second dielectric layer is formed on the surface of the first dielectric layer and fills the first groove; the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate; and the metal filling layer is positioned in the first groove and fills partial space in the first groove.

Description

Semiconductor memory structure and preparation method
Technical Field
The present application relates to the field of semiconductor memory structures, and more particularly, to a semiconductor memory structure and a method for fabricating the same.
Background
In the production process of a semiconductor memory, it is usually necessary to form a trench on the surface of a substrate and fill the trench with other material layers, and during the filling of the material layers, an undesired recess may be formed on the surface of the substrate as shown in fig. 1. Referring to fig. 1, a first material layer 103, a second material layer 104 and a third material layer 105 are sequentially filled in a trench where a shallow trench isolation structure is located, and the top height of the first material layer 103 is lower than the surface height of a substrate 101 and lower than the top height of the second material layer 104, so that a groove 102 is formed between the second material layer 104 and the substrate 101, and the grooves 102 are also difficult to fill and level in the subsequent production process of a semiconductor memory, and are likely to collapse along with the accumulation of the material layers in the subsequent production process of the semiconductor memory, which affects the flatness of the semiconductor memory, thereby affecting the yield of the semiconductor memory.
Disclosure of Invention
In view of this, the present application provides a semiconductor memory structure and a method for manufacturing the same, which can eliminate the recess generated in the process of filling the trench with various material layers, and improve the yield of the semiconductor memory.
The present application provides a semiconductor memory structure comprising: a substrate; the first groove is positioned on the upper surface of the substrate, and the edge angle of the top of the first groove is arc-shaped; the first dielectric layer is distributed along the inner wall of the first groove; the second dielectric layer is formed on the surface of the first dielectric layer and fills the first groove; the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate; and the metal filling layer is positioned in the first groove and fills partial space in the first groove.
Optionally, the method further includes: and the third dielectric layer is positioned above the top of the metal filling layer, positioned in the first groove and filled in the first groove.
Optionally, the second dielectric layer includes a first sub-layer and a second sub-layer, the first sub-layer is formed on the surface of the first dielectric layer, and the second sub-layer is formed on the surface of the first sub-layer and fills the first trench.
Optionally, the first dielectric layer comprises an oxide dielectric layer, and/or the second dielectric layer comprises a nitride dielectric layer.
Optionally, the first sub-layer includes a nitride dielectric layer, and the second sub-layer includes an oxide dielectric layer.
Optionally, the trench structure further includes a fourth dielectric layer, the fourth dielectric layer covers the inner wall of the first trench, and the fourth dielectric layer fills a part of the space of the first trench.
Optionally, the method further includes: an insulating layer formed over the top of the second dielectric layer, over the top of the metal fill layer, and over the upper surface of the substrate.
Optionally, the method further includes: a gate stack structure formed over a top of the substrate, and/or: a load stack structure formed over a top of the second dielectric layer.
Optionally, the gate stack structure at least includes a first polysilicon layer, a first conductive layer, and a first mask layer that are sequentially distributed upward along a direction perpendicular to the upper surface of the substrate, and/or: the load stacking structure comprises a second polycrystalline silicon layer, a second conducting layer and a second mask layer which are sequentially distributed upwards along the direction vertical to the upper surface of the substrate.
Optionally, the preparation material of the metal filling layer is the same as that of the first conductive layer and that of the second conductive layer.
The application provides a preparation method of a semiconductor memory structure, which comprises the following steps: providing a substrate, wherein a first groove is formed on the upper surface of the substrate; sequentially forming a first dielectric material layer and a second dielectric material layer along the inner wall of the first groove; partially removing the first dielectric material layer and the second dielectric material layer to enable the edge angle of the top of the first groove to be in a circular arc shape, and correspondingly forming a first dielectric layer and a second dielectric layer respectively, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate; and forming a metal filling layer in the first groove to partially fill the first groove.
Optionally, after the metal filling layer is formed in the first groove, the method further includes the following steps: and forming a third dielectric layer above the top of the metal filling layer, wherein the third dielectric layer fills the first groove.
Optionally, the partially removing the first dielectric material layer and the second dielectric material layer includes the following steps: and partially removing the first dielectric material layer and the second dielectric material layer by at least one of dry etching or wet etching, wherein the etching rate of the selected etching gas or etching liquid to the first dielectric material layer is higher than that to the second dielectric material layer.
Optionally, the second dielectric layer includes a first sub-layer and a second sub-layer, and forming the second dielectric layer includes: forming the first sub-material layer on the surface of the first dielectric layer; and forming the second sub-material layer on the surface of the first sub-material layer, wherein the first groove is filled with the second sub-material layer.
Optionally, before forming the metal filling layer in the first groove, the method further includes the following steps: and forming a fourth dielectric layer on the inner wall of the first groove.
Optionally, the forming of the metal filling layer in the first groove includes: forming a metal layer in the first groove, above the top of the second dielectric layer and on the upper surface of the substrate, wherein the metal layer at least fills the first groove; and carrying out back etching on the metal layer, and reserving the metal layer in the first groove as the metal filling layer.
Optionally, the forming a third dielectric layer on the upper surface of the metal filling layer includes: forming a dielectric material layer above the top of the metal filling layer, above the top of the second dielectric layer and on the upper surface of the substrate, wherein the dielectric material layer at least fills the first groove; and carrying out back etching on the dielectric material layer, and reserving the dielectric material layer in the first groove as the third dielectric layer.
According to the semiconductor memory structure and the preparation method, the metal filling layer is used for filling the partial space of the first groove, the metal filling layer has high strength and certain ductility, so that after the metal filling layer is used for filling the first groove, the probability of collapse of the first groove in the later semiconductor memory structure preparation process is obviously reduced, the grooves with unexpected upper surfaces of the substrates can be effectively eliminated, the probability of collapse of the filled first groove can be reduced, the better groove filling effect is achieved, and the yield of the semiconductor memory structure is effectively improved.
In addition, as the first groove is filled with the metal material, the metal filling layer can be used for positioning the boundary of the first groove by utilizing the opacity and the good light reflection performance of the metal filling layer in the subsequent process of preparing the semiconductor memory structure, so that the central position of the first groove is determined, and a good film alignment effect is realized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 illustrates a prior art semiconductor memory structure;
FIG. 2 is a flow chart illustrating a method for fabricating a semiconductor memory structure according to an embodiment of the present application;
fig. 3 to 16 are schematic structural diagrams corresponding to steps of a method for manufacturing a semiconductor memory structure according to an embodiment of the present application.
FIG. 17 is a diagram illustrating a semiconductor memory structure according to an embodiment of the present application.
FIG. 18 is a diagram illustrating a semiconductor memory structure according to an embodiment of the present application.
Detailed Description
The semiconductor memory structure and the method for fabricating the same are further described with reference to the drawings and the embodiments.
The present application provides, in a first aspect, a method of fabricating a semiconductor memory structure.
Referring to fig. 2 to 16, fig. 2 is a schematic flow chart illustrating steps of a method for manufacturing a semiconductor memory structure according to an embodiment of the present disclosure, and fig. 3 to 16 are schematic structural diagrams corresponding to the steps of the method for manufacturing a semiconductor memory structure according to the embodiment of the present disclosure.
In this embodiment, the method for manufacturing the semiconductor memory structure includes the following steps: step S101: providing a substrate 201, wherein a first trench 200 is formed on an upper surface of the substrate 201 (see fig. 3); step S102: forming a first dielectric material layer 2031 (see fig. 4) and a second dielectric material layer in sequence along the inner wall of the first trench 200; step S103: partially removing the first dielectric material layer 2031 and the second dielectric material layer to make the edge of the top of the first trench 200 arc, and correspondingly forming a first dielectric layer 203 and a second dielectric layer 204, respectively, and the top of the first dielectric layer 203 is lower than the top of the second dielectric layer 204 and the upper surface of the substrate 201, so as to form a first groove 202 between the second dielectric layer 204 and the substrate 201 (see fig. 7); step S104: a metal filling layer 207 is formed in the first recess 202 to partially fill the first recess 202 (see fig. 10).
In the method for manufacturing the semiconductor memory structure in this embodiment, the metal filling layer 207 is used to fill part of the space of the first groove 202, and since the metal filling layer 207 has high strength and certain ductility, after the metal filling layer 207 is used to fill the first groove 202, the probability of collapse of the first groove 202 in the subsequent manufacturing process of the semiconductor memory structure is significantly reduced, which can effectively eliminate the unexpected groove on the upper surface of the substrate 201, and can also reduce the probability of collapse of the filled first groove 202, thereby having a better groove filling effect, and effectively improving the yield of the semiconductor memory structure.
Moreover, since the first groove 202 is filled with metal, the metal filling layer can be used to position the boundary of the first trench 200 in the subsequent process of manufacturing the semiconductor memory structure by using the opacity and the good light reflection performance of the metal filling layer, so as to determine the center position of the first trench 200, thereby achieving a better film alignment effect.
In some embodiments, after forming the metal filling layer 207 in the first groove 202, the method further includes the following steps: a third dielectric layer 208 is formed over the top of the metal fill layer 207, the third dielectric layer 208 filling the first recess 202 (see fig. 12).
In these embodiments, the third dielectric layer 208 is further used to fill the remaining portion of the first recess 202, which can effectively block the electrical connection between the metal filling layer 207 and other conductive structures, thereby playing a certain insulating role, and preventing the metal filling layer 207 from being shorted with other conductive structures, which results in the damage of the semiconductor memory structure.
In some embodiments, the partially removing the first and second layers of dielectric material 2031 comprises the steps of: at least one of dry etching and wet etching is adopted to partially remove the first dielectric material layer 2031 and the second dielectric material layer, and the etching rate of the selected etching gas or etching liquid to the first dielectric material layer 2031 is higher than that to the second dielectric material layer, so that the top height of the first dielectric layer 203 formed after etching is lower than that of the second dielectric layer 204.
In some embodiments, the partially removing the first and second layers of dielectric material 2031 further comprises the steps of: a third mask layer 208 is formed on the upper surface of the first dielectric layer 203, and the third mask layer 208 is patterned to expose the first dielectric material layer 2031 and the second dielectric material layer filled in the first trench 200 and a part of the first dielectric material layer 2031 at the edge of the first trench 200, so that etching gas or etching liquid can be used to etch only the inside of the first trench 200 and the edge of the first trench 200 to obtain a desired shape, see fig. 6.
In some further embodiments, the etching gas or etching liquid etches the first dielectric material layer 2031 at a higher rate than the substrate 201, so that after etching, the top of the first dielectric layer 203 is formed at a lower height than the upper surface of the substrate 201, as can be seen in fig. 7.
In some embodiments, the second dielectric layer 204 includes a first sub-layer 205 and a second sub-layer 206, and forming the second dielectric layer 204 includes: forming the first sub-material layer 2051 on a surface of the first dielectric layer 203; the second sub-material layer 2061 is formed on the surface of the first sub-material layer 2051, and the second sub-material layer 2061 fills the first trench 200, as shown in fig. 5.
In the embodiment shown in fig. 7, the first dielectric layer 203 comprises an oxide dielectric layer, the first sub-layer 205 comprises a nitride dielectric layer, and the second sub-layer 206 comprises an oxide dielectric layer. After etching, the top of the first sub-layer 205 is higher than the top of the first dielectric layer 203 and also higher than the top of the second sub-layer 206. The central region of the filler in the first trench 200 is recessed.
In the embodiment shown in fig. 18, the second dielectric layer 204 includes only a single dielectric layer and does not include a plurality of individual sub-layers. In some embodiments, the first dielectric layer 203 comprises an oxide dielectric layer and the second dielectric layer 204 comprises a nitride dielectric layer.
Before the metal filling layer 207 is formed in the first groove 202, the method further includes the following steps: a fourth dielectric layer 209 is formed on the inner wall surface of the first recess 202, as shown in fig. 8.
The fourth dielectric layer 209 is partially located between the metal filling layer 207 and the substrate 201, and can be used to isolate the electrical connection between the metal filling layer 207 and the substrate 201, so as to prevent the metal filling layer 207 and the substrate 201 from being short-circuited, thereby preventing the semiconductor memory structure from being electrically damaged due to the metal filling layer 207.
The forming of the metal filling layer 207 in the first groove 202 includes: forming a metal layer 2071 in the first groove 202, on top of the second dielectric layer 204 and on the upper surface of the substrate 201, the metal layer 2071 at least filling the first groove 202, as shown in fig. 9; the metal layer 2071 is etched back, and the metal layer 2071 in the first groove 202 is remained as the metal filling layer 207, as shown in fig. 10.
In some embodiments, the metal layer 2071 is formed in the first groove 202 by at least one of physical vapor deposition, chemical vapor deposition, and the like. And the metal layer 2071 may be etched back by at least one of dry etching or wet etching. Moreover, the adopted back etching method has higher etching selection ratio to the fourth dielectric layer 209 and the metal layer 2071.
The forming of the third dielectric layer 208 on the upper surface of the metal filling layer 207 includes: forming a dielectric material layer 2081 on top of the metal filling layer 207, on top of the second dielectric layer 204, and on the upper surface of the substrate 201, the dielectric material layer 2081 at least filling the first groove 202, as shown in fig. 11; the dielectric material layer 2081 is etched back, and the dielectric material layer 2081 in the first groove 202 is remained as the third dielectric layer 208, as shown in fig. 12.
In some embodiments, the dielectric material layer 2081 is prepared using at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. The dielectric material layer 2081 includes a silicon nitride layer, etc. The third dielectric layer 208 can be used to isolate the metal filling layer 207 from being electrically connected to other conductive structures, thereby playing a certain insulating role, and preventing the metal filling layer 207 from being shorted with other conductive structures, which may result in the damage of the semiconductor memory structure.
In some embodiments, the method further comprises fabricating a gate stack structure 300 on the upper surface of the substrate 201. Referring to fig. 13, a first polysilicon layer 210, a first conductive layer 211 and a first mask layer 212 in the gate stack structure 300 are sequentially formed on the surface of the fourth dielectric layer 209 on the surface of the substrate 201 and on the surface of the third dielectric layer 208. Thereafter, referring to fig. 14, a fourth mask layer 213 is formed on the upper surface of the first mask layer 212, and the patterned fourth mask layer 213 exposes the first mask layer 212 above the first trench 200.
Thereafter, referring to fig. 15, the first mask layer 212, the first conductive layer 211 and the first polysilicon layer 210 are etched in a direction vertical to the first mask layer 212 to expose the fourth dielectric layer 209. Referring to fig. 16, an insulating layer 214 is formed on the exposed upper surface of the fourth dielectric layer 209, thereby completing the fabrication of the gate stack structure 300. The insulating layer 214 comprises a silicon oxide layer.
In some embodiments, the method further includes fabricating a Loading stack structure 301 on top of the second dielectric layer for better etch Loading (Loading) of the gate stack structure 300. When the load stack structure 301 is prepared, a metal filling layer filled in the first groove 202 is also used for positioning.
Specifically, the first mask layer 212 and the second mask layer 2121 are formed by partially removing the same mask material layer, the first conductive layer 211 and the second conductive layer 2111 are formed by partially removing the same conductive material layer, and the first polysilicon layer 210 and the second polysilicon layer 2101 are formed by partially removing the same polysilicon material layer, so that the load stack structure 301 and the gate stack structure 300 can be formed only by forming a patterned mask layer on the uppermost mask material layer and exposing the region corresponding to the position of the metal filling layer mark.
The first patterned photomask needs to expose the area corresponding to the metal filling layer.
In some embodiments, the load stack structure 301 includes a second polysilicon layer, a second conductive layer, and a second mask layer sequentially distributed upward along a direction perpendicular to the upper surface of the substrate. Reference is made here to fig. 17.
The present application provides, in a second aspect, a semiconductor memory structure.
Fig. 12 is a schematic structural diagram of a semiconductor memory structure according to an embodiment of the present application.
In this embodiment, the semiconductor memory structure includes: a substrate 201; at least one first trench 200 located on the upper surface of the substrate 201, and the edge corner of the top of the first trench 200 is arc-shaped; a first dielectric layer 203 distributed along the inner wall of the first trench 200; a second dielectric layer 204 formed on the surface of the first dielectric layer 203 and filling the first trench 200; the top of the first dielectric layer 203 is lower than the top of the second dielectric layer 204 and the upper surface of the substrate 201, so that a first groove 202 is formed between the second dielectric layer 204 and the substrate 201; and a metal filling layer 207 positioned in the first groove 202 and filling a part of the space in the first groove 202.
The semiconductor memory structure of the application adopts the metal filling layer 207 to fill the partial space of the first groove 202, and the metal filling layer 207 has high strength and certain ductility, so that after the metal filling layer 207 is used for filling the first groove 202, the collapse probability of the first groove 202 in the later semiconductor memory structure preparation process is obviously reduced, not only can the unexpected groove on the upper surface of the substrate 201 be effectively eliminated, but also the collapse probability of the filled first groove 202 can be reduced, thereby having better groove filling effect and effectively improving the yield of the semiconductor memory structure.
Moreover, since the first groove 202 is filled with metal, the metal filling layer can be used to position the boundary of the first trench 200 in the subsequent process of manufacturing the semiconductor memory structure by using the opacity and the good light reflection performance of the metal filling layer, so as to determine the center position of the first trench 200, thereby achieving a better film alignment effect.
In some other embodiments, the semiconductor memory structure further comprises: a third dielectric layer 208 is disposed over the top of the metal filling layer 207 and in the first recess 202 to fill the first recess 202.
The third dielectric layer 208 is used for filling the remaining part of the first groove 202, so that the electrical connection between the metal filling layer 207 and other conductive structures can be effectively isolated, a certain insulation effect is achieved, and the semiconductor memory structure is prevented from being damaged due to the fact that the metal filling layer 207 is short-circuited with other conductive structures.
In this embodiment, the reason for forming the first groove 202 is that the edge corner at the top of the first trench 200 needs to be arc-shaped, and not have a sharp corner to be more smooth, so as to reduce the probability of tip discharge at the edge corner of the first trench 200.
In some embodiments, the method of making the edge corner of the top of the first trench 200 arc-shaped comprises: the first trench 200 is formed first, and the first dielectric layer 203 and the second dielectric layer 204 are sequentially formed along the inner wall of the first trench 200, and the first dielectric layer 203 is further laid on the upper surface of the substrate 201. Then, a photomask is formed on the upper surface of the first dielectric layer 203, and the photomask is patterned to expose the filler of the first trench 200 and the first portion of the first dielectric layer 203 disposed on the upper surface of the substrate 201, where the first portion is distributed along the edge angle of the first trench 200. Then, the filling material of the first trench 200 and the first portion of the first dielectric layer 203 disposed on the upper surface of the substrate 201 are partially removed along the exposed region of the patterned photomask, so as to implement an arc-shaped treatment on the edge corner of the first trench 200.
In this embodiment, the materials of the first dielectric layer 203 and the second dielectric layer 204 are different.
In the embodiment shown in fig. 18, the second dielectric layer 204 comprises only a single dielectric layer and does not comprise a plurality of individual sub-layers. In some embodiments, the first dielectric layer 203 comprises an oxide dielectric layer and the second dielectric layer 204 comprises a nitride dielectric layer.
In the process of performing the arc process, since the materials of the first dielectric layer 203 and the second dielectric layer 204 are different, there is also a difference in the etching rate ratio of the etching gas or the etching liquid to the first dielectric layer 203 and the second dielectric layer 204. In the embodiment shown in fig. 3, the etching rate of the selected etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate on the second dielectric layer 204, and the etching rate of the etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate on the substrate 201, after etching, the top height of the first dielectric layer 203 is lower than the top height of the second dielectric layer 204 and lower than the height of the upper surface of the substrate 201.
As shown in fig. 12, the second dielectric layer 204 includes a first sub-layer 205 and a second sub-layer 206, the first sub-layer 205 is formed on the surface of the first dielectric layer 203, and the second sub-layer 206 is formed on the surface of the first sub-layer 205 and fills the first trench 200.
In some embodiments, the first dielectric layer 203 comprises an oxide dielectric layer, the first sub-layer 205 comprises a nitride dielectric layer, and the second sub-layer 206 comprises an oxide dielectric layer. After etching, the top of the first sub-layer 205 is higher than the top of the first dielectric layer 203 and higher than the top of the second sub-layer 206, so that the central region of the filler in the first trench 200 is recessed.
In some other embodiments, the specific material of the second dielectric layer 204 may be set as desired.
The semiconductor memory structure further comprises a fourth dielectric layer 209, wherein the fourth dielectric layer 209 covers the inner wall of the first groove 202 and the upper surface of the substrate 201, and the fourth dielectric layer 209 fills a part of the space of the first groove 202. The fourth dielectric layer 209 is partially located between the metal filling layer 207 and the substrate 201, and can be used to isolate the electrical connection between the metal filling layer 207 and the substrate 201, so as to prevent the metal filling layer 207 and the substrate 201 from being short-circuited, thereby preventing the semiconductor memory structure from being electrically damaged due to the metal filling layer 207.
In some other embodiments, the semiconductor memory structure further comprises: an insulating layer 214 formed over the top of the second dielectric layer 204, over the top of the metal fill layer 207, and over the upper surface of the substrate 201. Specifically, the first trench is distributed on a partial region of the upper surface of the substrate 201 and is disposed close to the first trench 200.
In some other embodiments, a third dielectric layer 208 is also formed over the metal fill layer 207, and the insulating layer 214 is also located over the top of the third dielectric layer 208.
In some embodiments, the semiconductor memory structure further comprises: a gate stack structure 300 formed over the top of the substrate, and/or: a load stack 301 formed over the top of the second dielectric layer.
In some embodiments, the gate stack structure 300 at least includes a first polysilicon layer 210, a first conductive layer 211 and a first mask layer 212 sequentially distributed upward along a direction perpendicular to the upper surface of the substrate 201 for forming a connection line.
In some other embodiments, the load stack 301 comprises a second polysilicon layer 2101, a second conductive layer 2111 and a second mask layer 2121 sequentially distributed upward along a direction perpendicular to the upper surface of the substrate, as shown in fig. 17.
In some embodiments, the first conductive layer 211 and the second conductive layer 2111 include at least one of copper, metal tungsten, titanium nitride, and other conductive material layers. In the embodiment shown in fig. 12, the first conductive layer 211 and/or the second conductive layer 2111 only includes the first conductive layer 211 made of one conductive material, and may be one of a metal tungsten layer, a titanium nitride layer, or a copper layer, in some other embodiments, the first conductive layer 211 and/or the second conductive layer 2111 may further include two adjacent conductive material layers, in some embodiments, the conductive material layer close to the substrate is a metal tungsten layer or a titanium nitride layer, and the conductive material layer far from the substrate is a titanium nitride layer or a metal tungsten layer.
In some embodiments, the top of the first polysilicon layer 210 is flush with the top of the second polysilicon layer 2101, the top of the first conductive layer 211 is flush with the top of the second conductive layer 2111, the top of the first mask layer 212 is flush with the top of the second mask layer 2121.
In some embodiments, the material for preparing the metal filling layer 207 is the same as the material for preparing the first conductive layer 211, so that the same set of metal deposition equipment and metal target can be used for preparing the metal filling layer 207 and the first conductive layer 211, thereby reducing the difficulty in preparation.
In some embodiments, the metal filling layer 207 is made of a conductive material such as titanium, metal tungsten, titanium nitride, or the like. In fact, the specific materials for preparing the first conductive layer 211 and the metal filling layer 207 can also be selected according to the requirement.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.

Claims (17)

1. A semiconductor memory structure, comprising:
a substrate;
the first groove is positioned on the upper surface of the substrate, and the edge angle of the top of the first groove is arc-shaped;
the first dielectric layer is distributed along the inner wall of the first groove;
the second dielectric layer is formed on the surface of the first dielectric layer and fills the first groove;
the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate;
and the metal filling layer is positioned in the first groove and fills partial space in the first groove.
2. The semiconductor memory structure of claim 1, further comprising:
and the third dielectric layer is positioned above the top of the metal filling layer, positioned in the first groove and filled in the first groove.
3. The semiconductor memory structure of claim 1, wherein the second dielectric layer comprises a first sub-layer and a second sub-layer, the first sub-layer is formed on a surface of the first dielectric layer, and the second sub-layer is formed on a surface of the first sub-layer and fills the first trench.
4. The semiconductor memory structure of claim 1, wherein the first dielectric layer comprises an oxide dielectric layer, and/or:
the second dielectric layer comprises a nitride dielectric layer.
5. The semiconductor memory structure of claim 3, wherein the first sublayer comprises a nitride dielectric layer and the second sublayer comprises an oxide dielectric layer.
6. The semiconductor memory structure according to claim 1, further comprising a fourth dielectric layer covering an inner wall of the first recess, wherein the fourth dielectric layer fills a part of the space of the first recess.
7. The semiconductor memory structure of claim 1, further comprising:
an insulating layer formed over the top of the second dielectric layer, over the top of the metal fill layer, and over the upper surface of the substrate.
8. The semiconductor memory structure of claim 1, further comprising:
a gate stack structure formed over a top of the substrate, and/or:
a load stack structure formed over a top of the second dielectric layer.
9. The semiconductor memory structure of claim 8, wherein the gate stack structure comprises at least a first polysilicon layer, a first conductive layer and a first mask layer sequentially distributed upward along a direction vertical to the upper surface of the substrate, and/or: the load stacking structure comprises a second polycrystalline silicon layer, a second conducting layer and a second mask layer which are sequentially distributed upwards along the direction vertical to the upper surface of the substrate.
10. The semiconductor memory structure according to claim 9, wherein a material for forming the metal filling layer is the same as a material for forming the first and second conductive layers.
11. A method for manufacturing a semiconductor memory structure is characterized by comprising the following steps:
providing a substrate, wherein a first groove is formed on the upper surface of the substrate;
sequentially forming a first dielectric material layer and a second dielectric material layer along the inner wall of the first groove;
partially removing the first dielectric material layer and the second dielectric material layer to enable the edge angle of the top of the first groove to be in a circular arc shape, and correspondingly forming a first dielectric layer and a second dielectric layer respectively, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate;
and forming a metal filling layer in the first groove to partially fill the first groove.
12. The method according to claim 11, further comprising the following steps after forming the metal filling layer in the first groove:
and forming a third dielectric layer above the top of the metal filling layer, wherein the third dielectric layer fills the first groove.
13. The method of claim 11, wherein the partially removing the first and second layers of dielectric material comprises:
and partially removing the first dielectric material layer and the second dielectric material layer by at least one of dry etching or wet etching, wherein the etching rate of the selected etching gas or etching liquid to the first dielectric material layer is higher than that to the second dielectric material layer.
14. The method of manufacturing of claim 11, wherein the second dielectric layer comprises a first sub-layer and a second sub-layer, and forming the second dielectric layer comprises:
forming the first sub-material layer on the surface of the first dielectric layer;
and forming the second sub-material layer on the surface of the first sub-material layer, wherein the first groove is filled with the second sub-material layer.
15. The method according to claim 11, further comprising, before forming the metal filling layer in the first groove:
and forming a fourth dielectric layer on the inner wall of the first groove.
16. The method of claim 11, wherein the forming a metal filling layer in the first groove comprises:
forming a metal layer in the first groove, above the top of the second dielectric layer and on the upper surface of the substrate, wherein the metal layer at least fills the first groove;
and carrying out back etching on the metal layer, and reserving the metal layer in the first groove as the metal filling layer.
17. The method of claim 12, wherein the forming a third dielectric layer on the upper surface of the metal filling layer comprises:
forming a dielectric material layer above the top of the metal filling layer, above the top of the second dielectric layer and on the upper surface of the substrate, wherein the dielectric material layer at least fills the first groove;
and carrying out back etching on the dielectric material layer, and reserving the dielectric material layer in the first groove as the third dielectric layer.
CN202210427201.4A 2022-04-21 2022-04-21 Semiconductor memory structure and preparation method Pending CN114883243A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023138228A1 (en) * 2022-01-24 2023-07-27 长鑫存储技术有限公司 Semiconductor structure and preparation method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023138228A1 (en) * 2022-01-24 2023-07-27 长鑫存储技术有限公司 Semiconductor structure and preparation method therefor

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