CN113257783B - Memory device and method of manufacturing the same - Google Patents
Memory device and method of manufacturing the same Download PDFInfo
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- CN113257783B CN113257783B CN202010083988.8A CN202010083988A CN113257783B CN 113257783 B CN113257783 B CN 113257783B CN 202010083988 A CN202010083988 A CN 202010083988A CN 113257783 B CN113257783 B CN 113257783B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000034 method Methods 0.000 description 34
- 230000008569 process Effects 0.000 description 23
- 238000005137 deposition process Methods 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- -1 silicon carbide nitride Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a memory device and a manufacturing method thereof. The embedded word line is disposed in the substrate. The connection structure is disposed on the buried word line. The air gap is disposed on the embedded word line and adjacent to the connection structure. The first dielectric layer is arranged on the connection structure and the air gap, wherein the embedded word line, the connection structure and the first dielectric layer are arranged along the normal direction of the top surface of the substrate.
Description
Technical Field
The present invention relates generally to semiconductor manufacturing technology, and more particularly to a memory device and a method for manufacturing the same.
Background
With the trend toward miniaturization of electronic products, the size of memory devices continues to shrink. In order to meet the above-mentioned needs, memory devices with embedded word lines have been developed to increase the integration and improve the performance. However, the continued reduction in size increases the capacitive coupling between adjacent interconnect structures, metal lines, or other elements and adversely affects the performance of the memory device. Therefore, there is a need for improved methods of manufacturing memory devices to enhance the performance of the memory devices.
Disclosure of Invention
According to some embodiments of the present invention, a memory device is provided. The memory device includes a buried word line disposed within a substrate; a connection structure disposed on the embedded word line; an air gap disposed on the buried word line and adjacent to the connection structure; and a first dielectric layer disposed on the connection structure and the air gap, wherein the buried word line, the connection structure and the first dielectric layer are disposed along a normal direction of the top surface of the substrate.
According to some embodiments of the present invention, methods of manufacturing memory devices are provided. The method includes forming buried word lines in a substrate; forming a sacrificial structure on the embedded word line, wherein the sacrificial structure covers two sides of the embedded word line and exposes a part of the embedded word line; forming a connection structure on the portion of the buried word line; removing the sacrificial structure after forming the connection structure; and forming a first dielectric layer on the connection structure, such that an air gap is formed between the first dielectric layer and the buried word line.
Drawings
Embodiments of the present invention will be described in detail below with reference to the attached drawings. It should be noted that the various features are not drawn to scale and are merely illustrative in accordance with industry standard practices. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to improve the clarity of presentation of the invention.
FIGS. 1A-1B are schematic cross-sectional views illustrating various stages in the fabrication of a memory device, according to some embodiments.
Fig. 2A-2G are cross-sectional schematic diagrams illustrating various stages in the fabrication of a memory device, according to some embodiments.
Reference numerals:
100, 200: memory device
102: Substrate and method for manufacturing the same
104: Mask layer
106: Groove(s)
108, 114, 120: Dielectric layer
110: Lining layer
112: Buried word line
118: Material layer
118': Connection structure
118P: protruding part
122: Air gap
W1, W2, W3: width of (L)
Detailed Description
Memory devices and methods of making the same are described below in accordance with some embodiments of the present invention, and are particularly applicable to memory devices having buried word lines. The invention provides an air gap on the embedded word line to replace a part of dielectric layer, so as to reduce the overall dielectric constant and improve the problems such as capacitive coupling, thereby improving the performance of the memory device.
FIG. 1A is a schematic cross-sectional diagram illustrating a memory device 100 according to some embodiments. As shown in fig. 1A, memory device 100 includes a substrate 102. The substrate 102 is, for example, a silicon wafer, and any desired semiconductor elements may be formed within the substrate 102 and on the substrate 102, but are shown here as a flat substrate 102 for simplicity of illustration. In the context of the present invention, the term "substrate" may include devices already formed on a semiconductor wafer and various coatings overlying the semiconductor wafer.
Then, a mask layer 104 is disposed on the substrate 102, and then an etching process is performed using the mask layer 104 as an etching mask to etch the substrate 102 into the trench 106. The mask layer 104 may comprise a hard mask and be formed, for example, of silicon oxide or similar material. The formation of the masking layer 104 may include a deposition process or other suitable process.
A dielectric layer 108 is then formed within the trench 106. In some embodiments, the method of forming the dielectric layer 108 includes oxidizing a portion of the substrate 102. In other embodiments, the method of forming the dielectric layer 108 includes depositing a dielectric material within the trench 106 by a deposition process. The dielectric material may comprise silicon oxide, silicon nitride, silicon oxynitride, similar materials, or a combination of the foregoing.
Then, according to some embodiments, liner 110 is formed within trench 106. In some embodiments, the material of liner 110 comprises titanium, titanium nitride, or similar materials. The liner 110 may be formed, for example, by an atomic layer deposition process or similar deposition process.
Then, in accordance with some embodiments, buried word lines 112 are formed within the lower portions of the trenches 106. Liner layer 110 is located between buried word line 112 and dielectric layer 108. The formation of buried word line 112 may include forming a conductive material within trench 106 by a deposition process. According to some embodiments, the conductive material comprises doped or undoped polysilicon, metal, similar materials, or combinations of the foregoing. According to some embodiments, the deposition process includes a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
Then, according to some embodiments, as shown in fig. 1B, a dielectric layer 114 is formed in the remaining portion of the trench 106. According to some embodiments, forming the dielectric layer 114 includes forming a dielectric material by a deposition process. Examples of dielectric materials and deposition processes are described above and will not be described in detail. However, the formation of the dielectric layer 114 tends to create capacitive coupling problems for the memory device 100. Accordingly, the present invention provides another embodiment that ameliorates the above-described problems.
Fig. 2A is a process step subsequent to fig. 1A, and for simplicity, like elements will be described below with like reference numerals. The manner and materials of formation of these elements are as described above and will not be repeated here.
Compared to the embodiment of fig. 1B, in which the dielectric layer 114 is directly formed on the buried word line 112, the following embodiment replaces a portion of the dielectric layer 114 with an air gap to reduce the overall dielectric constant and improve the capacitive coupling.
In some embodiments, as shown in FIG. 2A, a buried word line 112 is formed in a lower portion of the trench 106, and then a sacrificial structure 116 is conformally formed (conformally) in an upper portion of the trench 106. According to some embodiments, the method of forming the sacrificial structure 116 includes forming a material of the sacrificial structure 116 by a deposition process. For example, the material of the sacrificial structure 116 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, similar materials, or combinations of the foregoing. Examples of deposition processes are described above and will not be described again.
Then, according to some embodiments, a portion of the material of the sacrificial structure 116 is removed to expose a portion of the buried word line 112. The remaining portion of the sacrificial structure 116 is the location where the subsequent air gap (as shown in fig. 2F) is located, so that the size and/or location of the remaining portion of the sacrificial structure 116 can be adjusted to adjust the size and/or location of the air gap. A portion of the sacrificial structure 116 may be removed by an etching process, and examples of the etching process are described above, and thus are not described in detail.
As shown in fig. 2A, the sacrificial structures 116 cover both sidewalls of the trench 106 and both sides of the buried word line 112, exposing only the middle portion of the buried word line 112 to form an air gap on both sides of the trench 106.
Then, according to some embodiments, a layer of material 118 is formed over the sacrificial structure 116 and over the mask layer 104, as shown in FIG. 2B. According to some embodiments, material layer 118 comprises a conductive material. For example, the conductive material comprises doped or undoped polysilicon, metal, similar materials, or combinations thereof. For example, the metal comprises gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, similar materials, alloys of the foregoing, multilayer structures of the foregoing, or combinations of the foregoing. The method of forming the conductive material may comprise a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, an evaporation process, an electroplating process, the like, or a combination of the foregoing.
In this embodiment, the material layer 118 includes a conductive material to improve the resistance capacitance delay (RC delay), but the invention is not limited thereto. In other embodiments, material layer 118 may comprise other materials, such as dielectric materials. The material of the sacrificial structure 116 and the material of the material layer 118 may be selected to have different etch selectivity ratios such that subsequent processes for removing the sacrificial structure 116 are less prone to damage to the material layer 118 to avoid defects in the memory device 200. For example, the sacrificial structure 116 comprises silicon nitride and the material layer 118 comprises polysilicon.
With continued reference to fig. 2B, during deposition of the material layer 118, a protrusion 118P may be formed. In some cases, the protrusions 118P of the material layer 118 may obstruct the formation of the remaining material layer 118 within the trench 106 such that the interior of the material layer 118 has pores. Thus, according to some embodiments, as shown in fig. 2C, an etching process is performed to remove the protruding portion 118P of the material layer 118. An example of the etching process is as described above, and thus will not be described again.
Then, according to some embodiments, as shown in fig. 2D, the deposition of the material layer 118 is continued on the etched material layer 118 to cover the exposed portions of the buried word line 112. Depending on the aspect ratio (aspect) of the trench 106, the above-described cycle of etching and deposition may be repeated a number of times. In this manner, the size and/or location of the connection structure 118' (shown in FIG. 2E) formed from the material layer 118 may be adjusted without being limited by the aspect ratio of the trench 106.
The foregoing etching process is selective (optional) only. In other embodiments, after the step shown in FIG. 2B, the etching process shown in FIG. 2C may not be performed, but rather the deposition of material layer 118 may be continued to cover the exposed portions of buried word line 112, as shown in FIG. 2D.
Then, according to some embodiments, as shown in fig. 2E, an etching process is performed to remove the upper portion of the material layer 118, and a connection structure 118' is formed to electrically connect the buried word line 112 and other devices. An example of the etching process is as described above, and thus will not be described again. Since the sacrificial structure 116 covers a portion of the top surface of the buried word line 112, the bottom surface of the connection structure 118' is smaller than the top surface of the buried word line 112, as shown in fig. 2E.
As shown in fig. 2E, the top surface of the connection structure 118' is lower than the top surface of the dielectric layer 108. According to some embodiments, the connection structure 118 'comprises a conductive material, so reducing the height of the top surface of the connection structure 118' may distance the connection structure 118 'from subsequently formed elements (e.g., contacts), avoiding the formation of shorts between the connection structure 118' and the elements, thereby improving the reliability of the memory device 200. As previously described, multiple cycles of etching and deposition may be performed to adjust the height of the top surface of the connection structure 118'.
Then, according to some embodiments, an etching process is performed to remove the sacrificial structure 116 and again expose the sidewalls of the trench 106, as shown in fig. 2F. An example of the etching process is as described above, and thus will not be described again.
Then, according to some embodiments, a dielectric layer 120 is formed within the trench 106 to cover the top of the connection structure 118', as shown in fig. 2G. The buried word line 112, the connection structure 118', and the dielectric layer 120 are disposed along a direction normal to the top surface of the substrate 102. The formation of the dielectric layer 120 may be performed by forming a dielectric material within the trench 106 by a deposition process and performing a planarization process, such as a chemical mechanical polishing process, to remove excess portions of the dielectric material. Because the connection structure 118 'on the buried word line 112 increases the aspect ratio of the upper portion of the trench 106, the material of the dielectric layer 120 is less likely to enter the space between the connection structure 118' and the substrate 102, and thus an air gap 122 may be formed.
Compared to the embodiment of fig. 1B, in which the dielectric layer 114 is directly formed on the buried word line 112, the air gap 122 and the connection structure 118' are formed first and then the dielectric layer 120 is formed in the embodiment of fig. 2G, so that the overall dielectric constant value on the buried word line 112 can be reduced, the problem of capacitive coupling can be improved, and the performance of the memory device 200 can be further improved. In addition, the connection structure 118' includes a conductive material, which can improve the resistance-capacitance delay problem, thereby further improving the performance of the memory device 200.
As previously described, since the sacrificial structure 116 is located on both sides of the connection structure 118', the air gaps 122 formed at the locations of the sacrificial structure 116 also abut both sides of the connection structure 118'.
The connection structure 118' directly contacts the buried word line 112 and the dielectric layer 120. As shown in fig. 2G, dielectric layer 120 covers a portion of the top surface and sidewalls of connection structure 118' and extends below the top surface of dielectric layer 108. The width W1 of the dielectric layer 120 is greater than the width W2 of the buried word line 112, and the width W2 of the buried word line 112 is greater than the width W3 of the air gap 122.
Since the top surface of liner 110 is lower than the top surface of buried word line 112, a portion of air gap 122 is located between the sidewalls of buried word line 112 and substrate 102. As shown in fig. 2G, an air gap 122 separates liner 110 from dielectric layer 120 and separates buried word line 112 from dielectric layer 120.
In summary, the memory device provided by the present invention can reduce the overall dielectric constant, improve the capacitive coupling, and further improve the performance of the memory device by replacing a portion of the dielectric material with the air gap and the connection structure.
In addition, in some embodiments, the connection structure includes conductive material to reduce resistance, improve resistance-capacitance delay, and further improve performance of the memory device. In addition, in some embodiments, the cycle of etching and deposition may be repeated to reduce the height of the top surface of the connection structure, avoiding the formation of shorts between subsequently formed elements and the connection structure, thereby improving the reliability of the memory device.
While embodiments of the invention have been described above in terms of various embodiments, these embodiments are not intended to limit the embodiments of the invention. Those skilled in the art should appreciate that they can readily use the disclosed embodiments as a basis for modifying, substituting and/or substituting the disclosed embodiments for those in the art to achieve the same purposes and/or advantages as the various embodiments described herein. Those skilled in the art will also appreciate that such modifications and designs do not depart from the spirit and scope of the embodiments of the invention. Accordingly, the scope of the invention is defined by the appended claims.
Claims (11)
1. A memory device, comprising:
a buried word line including metal disposed in a substrate;
a connection structure comprising polysilicon disposed on the buried word line, wherein the material of the buried word line is different from the material of the connection structure;
An air gap disposed on the buried word line and adjacent to the connection structure, wherein the air gap exposes a top surface of the buried word line and a sidewall of the connection structure; and
And a first dielectric layer arranged on the connection structure and the air gap, wherein the embedded word line, the connection structure and the first dielectric layer are arranged along the normal direction of the top surface of the substrate.
2. The memory device of claim 1, wherein the connection structure comprises a conductive material.
3. The memory device of claim 1, wherein a bottom surface of the connection structure is smaller than the top surface of the buried word line.
4. The memory device of claim 1, wherein the air gap is located on both sides of the connection structure.
5. The memory device of claim 1, wherein a portion of the air gap is located between a sidewall of the buried word line and the substrate.
6. The memory device of claim 1, wherein the connection structure directly contacts the buried word line and the first dielectric layer.
7. The memory device of claim 1, wherein the buried word line, the connection structure and the air gap are disposed in a trench, and further comprising a second dielectric layer disposed on sidewalls of the trench.
8. A method of manufacturing a memory device, comprising:
forming a buried word line comprising metal in a substrate;
Forming a sacrificial structure on the embedded word line, wherein the sacrificial structure covers two sides of the embedded word line and exposes a part of the embedded word line;
Forming a connection structure including polysilicon on the portion of the buried word line, wherein the material of the buried word line is different from the material of the connection structure;
removing the sacrificial structure after forming the connection structure; and
A first dielectric layer is formed over the connection structure such that an air gap is formed between the first dielectric layer and the buried word line, wherein the air gap exposes a top surface of the buried word line and sidewalls of the connection structure.
9. The method of manufacturing a memory device of claim 8, wherein the forming of the connection structure comprises:
Conformally forming a first material layer on the sacrificial structure;
etching a protruding portion of the first material layer;
Forming a second material layer on the etched first material layer to cover the portion of the embedded word line; and
An upper portion of the first material layer and the second material layer is removed to form the connection structure.
10. The method of manufacturing a memory device of claim 9, wherein the first material layer and the second material layer comprise the same conductive material.
11. The method of manufacturing a memory device according to claim 8, further comprising:
forming a trench in the substrate prior to forming the buried word line;
forming the buried word line at a lower portion of the trench; and
The sacrificial structure is conformally formed on an upper portion of the trench to cover both sides of the trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010083988.8A CN113257783B (en) | 2020-02-10 | 2020-02-10 | Memory device and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010083988.8A CN113257783B (en) | 2020-02-10 | 2020-02-10 | Memory device and method of manufacturing the same |
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| CN113257783B true CN113257783B (en) | 2024-05-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017298A (en) * | 2015-12-15 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Field effect transistor |
| CN108074972A (en) * | 2016-11-15 | 2018-05-25 | 格芯公司 | There is the semiconductor device based on transistor of air gap separation part and gate contact above active region |
| US10388770B1 (en) * | 2018-03-19 | 2019-08-20 | Globalfoundries Inc. | Gate and source/drain contact structures positioned above an active region of a transistor device |
| US10529826B1 (en) * | 2018-08-13 | 2020-01-07 | Globalfoundries Inc. | Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9331072B2 (en) * | 2014-01-28 | 2016-05-03 | Samsung Electronics Co., Ltd. | Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same |
| KR102527904B1 (en) * | 2016-11-18 | 2023-04-28 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| US11038059B2 (en) * | 2018-07-31 | 2021-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
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2020
- 2020-02-10 CN CN202010083988.8A patent/CN113257783B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017298A (en) * | 2015-12-15 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Field effect transistor |
| CN108074972A (en) * | 2016-11-15 | 2018-05-25 | 格芯公司 | There is the semiconductor device based on transistor of air gap separation part and gate contact above active region |
| US10388770B1 (en) * | 2018-03-19 | 2019-08-20 | Globalfoundries Inc. | Gate and source/drain contact structures positioned above an active region of a transistor device |
| US10529826B1 (en) * | 2018-08-13 | 2020-01-07 | Globalfoundries Inc. | Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices |
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| CN113257783A (en) | 2021-08-13 |
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