CN113257783A - Memory device and method of manufacturing the same - Google Patents
Memory device and method of manufacturing the same Download PDFInfo
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- CN113257783A CN113257783A CN202010083988.8A CN202010083988A CN113257783A CN 113257783 A CN113257783 A CN 113257783A CN 202010083988 A CN202010083988 A CN 202010083988A CN 113257783 A CN113257783 A CN 113257783A
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- word line
- buried word
- memory device
- forming
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 11
- 230000008569 process Effects 0.000 description 24
- 238000005137 deposition process Methods 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 9
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- -1 silicon carbide nitride Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
Abstract
The invention provides a memory device and a manufacturing method thereof. The embedded word lines are disposed in the substrate. The connection structure is disposed on the embedded word line. The air gap is disposed on the embedded word line and adjacent to the connection structure. The first dielectric layer is disposed on the connection structure and the air gap, wherein the embedded word line, the connection structure and the first dielectric layer are disposed along a normal direction of the top surface of the substrate.
Description
Technical Field
The present invention relates generally to semiconductor manufacturing technology, and more particularly to memory devices and methods of manufacturing the same.
Background
With the trend of miniaturization of electronic products, the size of memory devices is also continuously shrinking. In order to meet the above requirements, memory devices with embedded word lines have been developed to increase the integration and improve the performance. However, the continued reduction in size has resulted in increased capacitive coupling between adjacent interconnect structures, metal lines, or other elements, and adversely affects the performance of the memory device. Therefore, there is a need for an improved method for manufacturing a memory device to improve the performance of the memory device.
Disclosure of Invention
According to some embodiments of the invention, a memory device is provided. The memory device comprises a buried word line disposed in a substrate; a connection structure disposed on the embedded word line; an air gap disposed on the embedded word line and adjacent to the connection structure; and a first dielectric layer disposed on the connection structure and the air gap, wherein the buried word line, the connection structure, and the first dielectric layer are disposed along a normal direction of the top surface of the substrate.
According to some embodiments of the present invention, methods of manufacturing memory devices are provided. The method includes forming buried word lines in a substrate; forming a sacrificial structure on the embedded word line, wherein the sacrificial structure covers two sides of the embedded word line and exposes a part of the embedded word line; forming a connection structure on the portion of the buried word line; after forming the connection structure, removing the sacrificial structure; and forming a first dielectric layer on the connection structure such that an air gap is formed between the first dielectric layer and the buried word line.
Drawings
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the present invention.
Fig. 1A-1B are schematic cross-sectional views depicting various stages in the fabrication of a memory device, according to some embodiments.
Fig. 2A-2G are schematic cross-sectional views depicting various stages in the fabrication of a memory device, according to some embodiments.
Reference numerals:
100, 200: memory device
102: substrate
104: mask layer
106: groove
108, 114, 120: dielectric layer
110: liner layer
112: buried word line
118: material layer
118': connection structure
118P: projection part
122: air gap
W1, W2, W3: width of
Detailed Description
Memory devices and methods of fabricating memory devices, particularly memory devices having buried word lines, are described in accordance with some embodiments of the present invention. The invention arranges air gaps on the embedded word lines to replace partial dielectric layer, so as to reduce the overall dielectric constant and improve the problems such as capacitance coupling, thereby improving the performance of the memory device.
Fig. 1A is a cross-sectional schematic diagram showing a memory device 100, according to some embodiments. As shown in fig. 1A, the memory device 100 includes a substrate 102. The substrate 102 is, for example, a silicon wafer, and any required semiconductor elements may be formed in and on the substrate 102, although only the planar substrate 102 is shown here for simplicity of the drawing. In the context of the present invention, the term "substrate" may include devices already formed on a semiconductor wafer as well as various coatings that may be applied to a semiconductor wafer.
Then, a mask layer 104 is disposed on the substrate 102, and an etching process is performed using the mask layer 104 as an etching mask to etch the substrate 102 into a trench 106. The mask layer 104 may comprise a hard mask and may be formed, for example, of silicon oxide or similar material. The formation of the masking layer 104 may include a deposition process or other suitable process.
A dielectric layer 108 is then formed within the trench 106. In some embodiments, the method of forming the dielectric layer 108 includes oxidizing a portion of the substrate 102. In other embodiments, the dielectric layer 108 is formed by depositing a dielectric material in the trench 106 by a deposition process. The dielectric material may comprise silicon oxide, silicon nitride, silicon oxynitride, similar materials, or combinations of the foregoing.
Then, according to some embodiments, buried word lines 112 are formed in the lower portion of the trenches 106. The liner layer 110 is located between the buried word lines 112 and the dielectric layer 108. The method of forming the buried word lines 112 may include forming a conductive material in the trenches 106 by a deposition process. According to some embodiments, the conductive material comprises doped or undoped polysilicon, a metal, a similar material, or a combination of the foregoing. According to some embodiments, the deposition process comprises a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
Then, according to some embodiments, a dielectric layer 114 is formed in the remaining portion of the trench 106, as shown in fig. 1B. According to some embodiments, the forming of the dielectric layer 114 includes forming a dielectric material by a deposition process. Examples of dielectric materials and deposition processes are described above and will not be described further. However, the formation of the dielectric layer 114 tends to create capacitive coupling problems with the memory device 100. Therefore, the present invention provides another embodiment to improve the above-mentioned problems.
Fig. 2A is a sequence of the process steps of fig. 1A, and for simplicity, like elements will be described with like reference numerals. The manner and materials of formation of these elements are as previously described and will not be repeated here.
Compared to fig. 1B, in which the dielectric layer 114 is directly formed on the buried word lines 112, the following embodiments replace a portion of the dielectric layer 114 with an air gap to reduce the overall dielectric constant and improve the capacitive coupling problem.
In some embodiments, as shown in fig. 2A, the buried word line 112 is formed in a lower portion of the trench 106, and then the sacrificial structure 116 is conformally formed in an upper portion of the trench 106. According to some embodiments, the method of forming the sacrificial structure 116 includes forming the material of the sacrificial structure 116 by a deposition process. For example, the material of the sacrificial structure 116 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, similar materials, or a combination thereof. The deposition process is as described above and thus is not described in detail.
Then, according to some embodiments, a portion of the material of the sacrificial structure 116 is removed to expose a portion of the buried word line 112. The remaining portion of the sacrificial structure 116 is the location where the subsequent air gap (as shown in fig. 2F) is disposed, and thus the size and/or location of the remaining portion of the sacrificial structure 116 can be adjusted to adjust the size and/or location of the air gap. A portion of the sacrificial structure 116 may be removed by an etching process, and the etching process is exemplary as described above, and thus is not described herein.
As shown in fig. 2A, the sacrificial structure 116 covers two sidewalls of the trench 106 and two sides of the buried word line 112, and only exposes a middle portion of the buried word line 112, so as to form an air gap on two sides of the trench 106.
Then, according to some embodiments, as shown in FIG. 2B, a material layer 118 is formed on the sacrificial structure 116 and on the masking layer 104. According to some embodiments, the material layer 118 comprises a conductive material. For example, the conductive material comprises doped or undoped polysilicon, a metal, similar materials, or combinations of the foregoing. For example, the metal comprises gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, similar materials, alloys of the foregoing, multilayer structures of the foregoing, or combinations of the foregoing. The method of forming the conductive material may include a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, an evaporation process, an electroplating process, a similar process, or a combination of the foregoing.
In this embodiment, the material layer 118 including the conductive material may improve the problem of the RC delay, but the present invention is not limited thereto. In other embodiments, the material layer 118 may comprise other materials, such as a dielectric material. The material of the sacrificial structure 116 and the material of the material layer 118 may be selected to have different etch selectivity ratios such that subsequent processes of removing the sacrificial structure 116 are less likely to damage the material layer 118 to avoid defects in the memory device 200. For example, sacrificial structure 116 comprises silicon nitride and material layer 118 comprises polysilicon.
With continued reference to fig. 2B, during the deposition of the material layer 118, a protrusion 118P may be formed. In some cases, the protrusion 118P of the material layer 118 may prevent the remaining material layer 118 from forming within the trench 106 such that the interior of the material layer 118 has voids. Thus, according to some embodiments, an etching process is performed to remove the protrusion 118P of the material layer 118, as shown in fig. 2C. The example of the etching process is as described above, and thus is not described again.
Then, according to some embodiments, as shown in fig. 2D, the material layer 118 is continuously deposited on the etched material layer 118 to cover the exposed portions of the buried word lines 112. The above-described cycle of etching and deposition may be repeated a number of times depending on the aspect ratio (aspect ratio) of the trench 106. As such, the size and/or location of the connection structure 118' (as shown in fig. 2E) formed by the material layer 118 may be adjusted without being limited by the aspect ratio of the trench 106.
The aforementioned etching process is only selective. In other embodiments, after the step shown in fig. 2B, the etching process shown in fig. 2C may not be performed, and the deposition of the material layer 118 may be continued to cover the exposed portions of the buried word lines 112, as shown in fig. 2D.
Then, according to some embodiments, as shown in fig. 2E, an etching process is performed to remove an upper portion of the material layer 118 and form a connection structure 118' to electrically connect the buried word line 112 and other devices. The example of the etching process is as described above, and thus is not described again. Since the sacrificial structure 116 covers a portion of the top surface of the buried word line 112, the bottom surface of the connection structure 118' is smaller than the top surface of the buried word line 112, as shown in fig. 2E.
As shown in fig. 2E, the top surface of the connection structure 118' is lower than the top surface of the dielectric layer 108. According to some embodiments, the connection structure 118 'comprises a conductive material, such that lowering the height of the top surface of the connection structure 118' can move the connection structure 118 'away from a subsequently formed element (e.g., a contact), thereby preventing a short circuit from being formed between the connection structure 118' and the element, and improving the reliability of the memory device 200. As previously described, multiple cycles of etching and deposition may be performed to adjust the height of the top surface of the connection structure 118'.
Then, according to some embodiments, an etching process is performed to remove sacrificial structures 116 and to again expose the sidewalls of trenches 106, as shown in fig. 2F. The example of the etching process is as described above, and thus is not described again.
Then, according to some embodiments, as shown in fig. 2G, a dielectric layer 120 is formed within the trench 106 to cover the top of the connection structure 118'. The buried word lines 112, the connecting structures 118' and the dielectric layer 120 are disposed along a normal direction of the top surface of the substrate 102. The dielectric layer 120 may be formed by forming a dielectric material within the trench 106 by a deposition process and performing a planarization process, such as a chemical mechanical polishing process, to remove excess portions of the dielectric material. Since the connection structure 118 'on the buried word line 112 increases the aspect ratio of the upper portion of the trench 106, the material of the dielectric layer 120 is not easy to enter the space between the connection structure 118' and the substrate 102, and thus the air gap 122 can be formed.
Compared to fig. 1B in which the dielectric layer 114 is directly formed on the buried word lines 112, in the embodiment of fig. 2G, the air gaps 122 and the connecting structures 118' are formed first, and then the dielectric layer 120 is formed, so that the overall dielectric constant value on the buried word lines 112 can be reduced, the problem of capacitive coupling can be improved, and the performance of the memory device 200 can be improved. In addition, the connection structure 118' includes a conductive material, which can improve the rc delay problem and further enhance the performance of the memory device 200.
As previously described, since the sacrificial structures 116 are located on both sides of the connection structure 118 ', the air gaps 122 formed at the location of the sacrificial structures 116 also abut both sides of the connection structure 118'.
The connecting structure 118' directly contacts the buried word line 112 and the dielectric layer 120. As shown in fig. 2G, the dielectric layer 120 covers a portion of the top surface and sidewalls of the connection structure 118' and extends below the top surface of the dielectric layer 108. The width W1 of the dielectric layer 120 is greater than the width W2 of the buried word line 112, and the width W2 of the buried word line 112 is greater than the width W3 of the air gap 122.
Since the top surface of the liner layer 110 is lower than the top surface of the buried word line 112, a portion of the air gap 122 is located between the sidewall of the buried word line 112 and the substrate 102. As shown in fig. 2G, the air gap 122 separates the liner layer 110 from the dielectric layer 120, and separates the buried word line 112 from the dielectric layer 120.
In summary, the memory device provided by the invention can reduce the overall dielectric constant and improve the capacitive coupling by replacing a part of the dielectric material with the air gap and the connection structure, thereby improving the performance of the memory device.
In addition, in some embodiments, the connection structure includes a conductive material to reduce resistance, improve rc delay, and further improve performance of the memory device. In addition, in some embodiments, the etching and deposition cycles may be repeated to reduce the height of the top surface of the connection structure, thereby preventing formation of short circuits between subsequently formed elements and the connection structure, thereby improving reliability of the memory device.
Although the embodiments of the present invention have been described above with reference to a plurality of embodiments, these embodiments are not intended to limit the embodiments of the present invention. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for modifying or replacing various features and advantages of the present disclosure to achieve various objectives and/or advantages similar to those achieved through the use of the present disclosure. Those skilled in the art to which the invention relates will also appreciate that such modifications or arrangements do not depart from the spirit and scope of the embodiments of the invention. Therefore, the protection scope of the present invention is subject to the limitations defined by the appended claims.
Claims (11)
1. A memory device, comprising:
a buried word line disposed in a substrate;
a connection structure disposed on the embedded word line;
an air gap disposed on the embedded word line and adjacent to the connection structure; and
a first dielectric layer disposed on the connecting structure and the air gap, wherein the buried word line, the connecting structure and the first dielectric layer are disposed along a normal direction of the top surface of the substrate.
2. The memory device of claim 1, wherein the connection structure comprises a conductive material.
3. The memory device of claim 1, wherein a bottom surface of the connecting structure is smaller than a top surface of the buried word line.
4. The memory device of claim 1, wherein the air gaps are located on both sides of the connecting structure.
5. The memory device of claim 1, wherein a portion of the air gap is between a sidewall of the buried word line and the substrate.
6. The memory device of claim 1, wherein the connecting structure directly contacts the buried word line and the first dielectric layer.
7. The memory device of claim 1, wherein the buried word line, the connecting structure and the air gap are disposed in a trench, and further comprising a second dielectric layer disposed on sidewalls of the trench.
8. A method of manufacturing a memory device, comprising:
forming a buried word line in a substrate;
forming a sacrificial structure on the buried word line, wherein the sacrificial structure covers two sides of the buried word line and exposes a part of the buried word line;
forming a connection structure on the portion of the buried word line;
removing the sacrificial structure after forming the connection structure; and
a first dielectric layer is formed over the interconnect structure such that an air gap is formed between the first dielectric layer and the buried word lines.
9. The method of claim 8, wherein the forming of the connection structure comprises:
conformably forming a first layer of material over the sacrificial structure;
etching a protrusion of the first material layer;
forming a second material layer on the etched first material layer to cover the portion of the embedded word line; and
removing an upper portion of the first material layer and the second material layer to form the connecting structure.
10. The method of claim 9, wherein the first material layer and the second material layer comprise a same conductive material.
11. The method of manufacturing a memory device according to claim 8, further comprising:
forming a trench in the substrate before forming the buried word line;
forming the buried word line at a lower portion of the trench; and
the sacrificial structure is conformally formed on an upper portion of the trench to cover both sides of the trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010083988.8A CN113257783A (en) | 2020-02-10 | 2020-02-10 | Memory device and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010083988.8A CN113257783A (en) | 2020-02-10 | 2020-02-10 | Memory device and method of manufacturing the same |
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| CN202010083988.8A Pending CN113257783A (en) | 2020-02-10 | 2020-02-10 | Memory device and method of manufacturing the same |
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| US20150214220A1 (en) * | 2014-01-28 | 2015-07-30 | Kang-ill Seo | Integrated circuit devices having air-gap spacers and methods of manufacturing the same |
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| US20180145080A1 (en) * | 2016-11-18 | 2018-05-24 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN108074972A (en) * | 2016-11-15 | 2018-05-25 | 格芯公司 | There is the semiconductor device based on transistor of air gap separation part and gate contact above active region |
| US10388770B1 (en) * | 2018-03-19 | 2019-08-20 | Globalfoundries Inc. | Gate and source/drain contact structures positioned above an active region of a transistor device |
| US10529826B1 (en) * | 2018-08-13 | 2020-01-07 | Globalfoundries Inc. | Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices |
| US20200044074A1 (en) * | 2018-07-31 | 2020-02-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of forming the same |
-
2020
- 2020-02-10 CN CN202010083988.8A patent/CN113257783A/en active Pending
Patent Citations (7)
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| US20150214220A1 (en) * | 2014-01-28 | 2015-07-30 | Kang-ill Seo | Integrated circuit devices having air-gap spacers and methods of manufacturing the same |
| CN107017298A (en) * | 2015-12-15 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Field effect transistor |
| CN108074972A (en) * | 2016-11-15 | 2018-05-25 | 格芯公司 | There is the semiconductor device based on transistor of air gap separation part and gate contact above active region |
| US20180145080A1 (en) * | 2016-11-18 | 2018-05-24 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
| US10388770B1 (en) * | 2018-03-19 | 2019-08-20 | Globalfoundries Inc. | Gate and source/drain contact structures positioned above an active region of a transistor device |
| US20200044074A1 (en) * | 2018-07-31 | 2020-02-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of forming the same |
| US10529826B1 (en) * | 2018-08-13 | 2020-01-07 | Globalfoundries Inc. | Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices |
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