CN110931485B - Semiconductor memory capacitor connecting wire structure and preparation method thereof - Google Patents
Semiconductor memory capacitor connecting wire structure and preparation method thereof Download PDFInfo
- Publication number
- CN110931485B CN110931485B CN201811100903.1A CN201811100903A CN110931485B CN 110931485 B CN110931485 B CN 110931485B CN 201811100903 A CN201811100903 A CN 201811100903A CN 110931485 B CN110931485 B CN 110931485B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- forming
- capacitor
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 171
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 370
- 238000002955 isolation Methods 0.000 claims abstract description 95
- 239000011229 interlayer Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000011049 filling Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 39
- 230000004888 barrier function Effects 0.000 claims description 23
- 238000001312 dry etching Methods 0.000 claims description 21
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 10
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 239000010937 tungsten Substances 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000002131 composite material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a semiconductor memory capacitor connecting wire structure and a preparation method thereof, wherein the preparation method comprises the following steps: 1) Providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a plurality of active areas and a plurality of bit lines; 2) Forming an interlayer dielectric layer on a semiconductor substrate; 3) Forming a first capacitor connecting hole in the interlayer dielectric layer; 4) Forming a sacrificial dielectric layer in the first capacitor connecting hole, and at least filling the first capacitor connecting hole; 5) Forming a second capacitance connecting hole in the interlayer dielectric layer and separating the second capacitance connecting hole from the first capacitance connecting hole through the interlayer dielectric layer; 6) And removing the sacrificial dielectric layer, and filling the conductive layer in the first capacitor connecting hole and the second capacitor connecting hole. The capacitor connecting wire structure obtained by the preparation method can ensure that the capacitor connecting wire structure has good appearance and electrical property, can also strengthen the isolation effect of the capacitor connecting wire structure and a bit line, and reduces parasitic capacitance.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor memory capacitor connecting wire structure and a preparation method thereof.
Background
At present, in the manufacturing process of a semiconductor memory, when a capacitor connecting line structure is formed, a dielectric layer is filled first, the capacitor connecting line structure is formed in the dielectric layer, and then the capacitor structure is prepared on the capacitor connecting line structure, so that the conduction between the capacitor structure and an active region is realized. However, the existing technology for forming the capacitor connecting wire structure cannot adapt to the size of the capacitor hole which is reduced along with the reduction of the size of the device, and for the etching of the capacitor hole with nanoscale and larger depth-to-width ratio, the situation that the appearance of the capacitor hole is poor due to etching is very easy to occur; on the other hand, parasitic capacitance is often generated between the capacitor hole and the bit line due to poor isolation performance. All the above conditions can lead to device failure and influence the product yield.
Therefore, there is a need for a new semiconductor memory capacitor connection structure and a method for fabricating the same, which solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a semiconductor memory capacitor connecting line structure and a manufacturing method thereof, which are used for solving the problems of poor appearance of the capacitor connecting line structure and easy generation of parasitic capacitance with a bit line in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a capacitor connection line structure of a semiconductor memory, comprising:
1) Providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a plurality of active areas which are arranged at intervals, and a plurality of bit lines connected with the active areas are formed on the semiconductor substrate;
2) Forming an interlayer dielectric layer on the semiconductor substrate, wherein the interlayer dielectric layer fills up gaps among the bit lines and the outer side areas of the bit lines;
3) Forming first capacitance connecting holes in the interlayer dielectric layer, wherein the first capacitance connecting holes are distributed on part of the active area between the bit lines and expose part of the active area;
4) Forming a sacrificial dielectric layer in the first capacitance connecting hole, wherein the sacrificial dielectric layer at least fills the first capacitance connecting hole;
5) Forming second capacitance connecting holes in the interlayer dielectric layer, wherein the second capacitance connecting holes are distributed on part of the active area between the bit lines, expose part of the active area and are separated from the first capacitance connecting holes through the interlayer dielectric layer; and
6) And removing the sacrificial dielectric layer, forming a conductive layer in the first capacitance connecting hole and the second capacitance connecting hole, and filling the first capacitance connecting hole and the second capacitance connecting hole with the conductive layer to form a first capacitance connecting wire structure and a second capacitance connecting wire structure respectively.
In a preferred embodiment of the present invention, in step 6), before forming the conductive layer in the first capacitor connection hole and the second capacitor connection hole, the method further includes a step of forming an isolation dielectric layer on sidewall surfaces of the first capacitor connection hole and the second capacitor connection hole.
As a preferable mode of the present invention, the isolation dielectric layer formed in the step 6) includes at least a first isolation dielectric layer formed on sidewall surfaces of the first capacitor connection hole and the second capacitor connection hole and a second isolation dielectric layer formed on a surface of the first isolation dielectric layer.
In a preferred embodiment of the present invention, in step 3), the method for forming the first capacitor connection hole includes forming a patterned etching barrier layer over the interlayer dielectric layer and the bit line, and forming the first capacitor connection hole by dry etching using the etching barrier layer as an etching mask.
In a preferred embodiment of the present invention, in step 5), the method for forming the second capacitor connection hole includes forming a patterned etching barrier layer over the interlayer dielectric layer, the bit line and the sacrificial dielectric layer, and forming the second capacitor connection hole by dry etching using the etching barrier layer as an etching mask.
As a preferable mode of the present invention, the sacrificial dielectric layer formed in the step 4) is distributed on the surface of the interlayer dielectric layer in addition to filling the first capacitor connection hole; in step 5), when the second capacitor connection hole is formed by dry etching, the patterned etching barrier layer is formed on the surface of the sacrificial dielectric layer, and the exposed part of the sacrificial dielectric layer is removed by dry etching.
As a preferred embodiment of the present invention, the conductive layer formed in step 6) includes at least a first conductive layer and a second conductive layer, the first conductive layer being located above the active region, and the second conductive layer being located above the first conductive layer.
In a preferred embodiment of the present invention, in step 1), before the bit line is formed on the semiconductor substrate, the method further includes a step of sequentially forming a shallow trench isolation structure and a buried word line in the semiconductor substrate, wherein the plurality of active regions are isolated by the shallow trench isolation structure.
The invention also provides a semiconductor memory capacitor connecting wire structure, which comprises:
The surface of the semiconductor substrate comprises a plurality of active areas which are distributed at intervals;
a plurality of bit lines on the semiconductor substrate and connected to the active region;
An interlayer dielectric layer filled in the gaps between the bit lines and the bit line outer area;
The first capacitor connecting hole is formed in the interlayer dielectric layer and is positioned on part of the active area between the bit lines;
The second capacitance connecting hole is formed in the interlayer dielectric layer, is positioned on part of the active area between the bit lines, and is separated from the first capacitance connecting hole through the interlayer dielectric layer;
the conductive layer is filled in the first capacitance connecting hole and the second capacitance connecting hole to respectively form a first capacitance connecting wire structure and a second capacitance connecting wire structure, and the lower part of the conductive layer is connected with the active region; and
And the isolation medium layer is covered on the side wall of the conductive layer.
As a preferable mode of the present invention, the isolation dielectric layer at least includes a first isolation dielectric layer and a second isolation dielectric layer, the first isolation dielectric layer is formed on the side wall surfaces of the first capacitor connection hole and the second capacitor connection hole, and the second isolation dielectric layer is formed on the surface of the first isolation dielectric layer.
As a preferred embodiment of the present invention, the conductive layer includes at least a first conductive layer and a second conductive layer, the first conductive layer is located above the active region, and the second conductive layer is located above the first conductive layer.
As a preferred embodiment of the present invention, the semiconductor memory capacitor connection line structure further includes a shallow trench isolation structure formed in the semiconductor substrate and a buried word line, and the plurality of active regions are isolated by the shallow trench isolation structure.
As described above, the invention provides a semiconductor memory capacitor connecting wire structure and a preparation method thereof, which have the following beneficial effects: the method for sequentially forming the first capacitor connecting hole and the second capacitor connecting hole by introducing two times of photoetching and etching avoids the problem of poor resistance of the capacitor connecting wire caused by poor appearance of the capacitor connecting hole after etching.
Drawings
Fig. 1 is a schematic plan view of a prior art structure for forming a capacitor connection line.
Fig. 2 is a schematic cross-sectional view of a prior art capacitor connection structure at AA' in fig. 1.
Fig. 3 is a partial cross-sectional view of the prior art at AA' of fig. 1 showing an ideal trench profile formed after etching a conductive layer.
Fig. 4 is a partial cross-sectional view of the prior art at AA' of fig. 1 showing the occurrence of an etch stop trench after etching the conductive layer.
Fig. 5 is a partial cross-sectional view of the prior art at AA' of fig. 1 showing the presence of a drum-shaped sidewall trench after etching the conductive layer.
Fig. 6 is a flowchart of a method for manufacturing a capacitor connection line structure of a semiconductor memory according to a first embodiment of the invention.
Fig. 7 is a schematic plan view of a capacitor connecting line structure according to a first embodiment of the present invention, wherein fig. 7 (a) also shows a coverage area of the first coverage area in step 3), and fig. 7 (B) also shows a coverage area of the second coverage area in step 5).
Fig. 8 is a schematic cross-sectional view of a capacitor connecting line structure according to an embodiment of the present invention after forming an interlayer dielectric layer, a hard mask layer and a first photoresist barrier layer in steps 1) to 3), wherein fig. 8 (a) is a schematic cross-sectional view of AA ' in fig. 7, fig. 8 (B) is a schematic cross-sectional view of BB ' in fig. 7, and fig. 8 (C) is a schematic cross-sectional view of CC ' in fig. 7.
Fig. 9 is a schematic cross-sectional structure of a first capacitor connecting hole formed in step 3) in a method for forming a capacitor connecting wire structure according to a first embodiment of the present invention, wherein fig. 9 (a) is a schematic cross-sectional view of AA ' in fig. 7, fig. 9 (B) is a schematic cross-sectional view of BB ' in fig. 7, and fig. 9 (C) is a schematic cross-sectional view of CC ' in fig. 7.
Fig. 10 is a schematic cross-sectional structure of a method for forming a capacitor connecting line structure according to the first embodiment of the present invention after removing the hard mask layer in step 3), wherein fig. 10 (a) is a schematic cross-sectional view at AA ' in fig. 7, fig. 10 (B) is a schematic cross-sectional view at BB ' in fig. 7, and fig. 10 (C) is a schematic cross-sectional view at CC ' in fig. 7.
Fig. 11 is a schematic cross-sectional view of a capacitor connecting line structure according to a first embodiment of the present invention after forming the sacrificial dielectric layer and the second photoresist barrier layer in steps 4) to 5), wherein fig. 11 (a) is a schematic cross-sectional view of AA ' in fig. 7, fig. 11 (B) is a schematic cross-sectional view of BB ' in fig. 7, and fig. 11 (C) is a schematic cross-sectional view of CC ' in fig. 7.
Fig. 12 is a schematic cross-sectional structure of a first embodiment of the present invention after forming a second capacitor connection hole in step 5) of the method for forming a capacitor connection line structure, where fig. 12 (a) is a schematic cross-sectional view of AA ' in fig. 7, fig. 12 (B) is a schematic cross-sectional view of BB ' in fig. 7, and fig. 12 (C) is a schematic cross-sectional view of CC ' in fig. 7.
Fig. 13 is a schematic cross-sectional structure of the first embodiment of the present invention after the sacrificial dielectric layer is removed in step 6) of the method for forming the capacitor connecting line structure, where fig. 13 (a) is a schematic cross-sectional view at AA ' in fig. 7, fig. 13 (B) is a schematic cross-sectional view at BB ' in fig. 7, and fig. 13 (C) is a schematic cross-sectional view at CC ' in fig. 7.
Fig. 14 is a schematic cross-sectional structure of a first insulating dielectric layer deposited in step 6) of a method for forming a capacitor connection line structure according to a first embodiment of the present invention, where fig. 14 (a) is a schematic cross-sectional view at AA ' in fig. 7, fig. 14 (B) is a schematic cross-sectional view at BB ' in fig. 7, and fig. 14 (C) is a schematic cross-sectional view at CC ' in fig. 7.
Fig. 15 is a schematic cross-sectional structure of a first isolation dielectric layer etched in step 6) in a method for forming a capacitor connection line structure according to a first embodiment of the present invention, where fig. 15 (a) is a schematic cross-sectional view at AA ' in fig. 7, fig. 15 (B) is a schematic cross-sectional view at BB ' in fig. 7, and fig. 15 (C) is a schematic cross-sectional view at CC ' in fig. 7.
Fig. 16 is a schematic cross-sectional structure of a capacitor connecting line structure according to a first embodiment of the present invention after depositing the second isolation dielectric layer in step 6), wherein fig. 16 (a) is a schematic cross-sectional view of AA ' in fig. 7, fig. 16 (B) is a schematic cross-sectional view of BB ' in fig. 7, and fig. 16 (C) is a schematic cross-sectional view of CC ' in fig. 7.
Fig. 17 is a schematic cross-sectional structure of a second isolation dielectric layer etched in step 6) in a method for forming a capacitor connection line structure according to a first embodiment of the present invention, where fig. 17 (a) is a schematic cross-sectional view at AA ' in fig. 7, fig. 17 (B) is a schematic cross-sectional view at BB ' in fig. 7, and fig. 17 (C) is a schematic cross-sectional view at CC ' in fig. 7.
Fig. 18 is a schematic cross-sectional structure of a first conductive layer deposited in step 6) of a method for forming a capacitor connection structure according to a first embodiment of the present invention, wherein fig. 18 (a) is a schematic cross-sectional view of AA ' in fig. 7, fig. 18 (B) is a schematic cross-sectional view of BB ' in fig. 7, and fig. 18 (C) is a schematic cross-sectional view of CC ' in fig. 7.
Fig. 19 is a schematic cross-sectional structure of a first conductive layer etched back in step 6) of the method for forming a capacitor connection line structure according to the first embodiment of the present invention, wherein fig. 19 (a) is a schematic cross-sectional view at AA ' in fig. 7, fig. 19 (B) is a schematic cross-sectional view at BB ' in fig. 7, and fig. 19 (C) is a schematic cross-sectional view at CC ' in fig. 7.
Fig. 20 is a schematic cross-sectional structure of a first embodiment of the present invention after depositing the second conductive layer in step 6) of the method for forming the capacitor connection line structure, wherein fig. 20 (a) is a schematic cross-sectional view of AA ' in fig. 7, fig. 20 (B) is a schematic cross-sectional view of BB ' in fig. 7, and fig. 20 (C) is a schematic cross-sectional view of CC ' in fig. 7.
Fig. 21 is a schematic cross-sectional structure of a second conductive layer after chemical mechanical polishing in step 6) in a method for forming a capacitor connection line structure according to a first embodiment of the present invention, wherein fig. 21 (a) is a schematic cross-sectional view at AA ' in fig. 7, fig. 21 (B) is a schematic cross-sectional view at BB ' in fig. 7, and fig. 21 (C) is a schematic cross-sectional view at CC ' in fig. 7.
Description of element reference numerals
101. Semiconductor substrate
102. Active region
103. Buried word line
104. Bit line
105. Shallow trench isolation structure
106. Capacitor connecting wire structure
107. A first dielectric layer
107A occlusion region
107B conductive layer etched region
108. Conductive layer
109. A second dielectric layer
201. Semiconductor substrate
201A active region
202. Shallow trench isolation structure
203. Buried word line
203A word line isolation layer
203B conductive material layer
203C gate dielectric layer
204. Bit line
204A top dielectric layer
204B wire body layer
204C isolation insulating layer
204D side wall structure
205. Interlayer dielectric layer
205A first capacitor connecting hole
205B second capacitor connecting hole
206. Hard mask layer
207. First photoresist barrier layer
207A first anti-reflection layer
207B first coverage area
208. Sacrificial dielectric layer
209. Second photoresist barrier layer
209A second anti-reflection layer
209B second coverage area
210. First isolation dielectric layer
211. Second isolation dielectric layer
212. Conductive layer
212A first conductive layer
212B second conductive layer
213. Capacitor connecting wire structure
213A first capacitor connecting line structure
213B second capacitor connecting line structure
S1-S6 Steps 1) -6)
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 21. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
In the prior art for forming a capacitor connecting line structure, poor electrical property of capacitor connection is often caused by poor appearance of a capacitor hole. In addition, the poor isolation effect of the isolation dielectric layer around the capacitor connecting wire structure is easy to cause the increase of parasitic capacitance between wires, thereby causing the performance degradation of the device.
Fig. 1 is a top view of a prior art solution for forming a capacitor connection structure, and fig. 2 is a schematic cross-sectional view at AA' in fig. 1. A plurality of active regions 102 and buried word lines 103 have been formed within a semiconductor substrate 101, a plurality of bit lines 104 are formed on the semiconductor substrate 101 and connect the active regions 102, the active regions 102 are isolated by shallow trench isolation structures 105. When the capacitor connecting line structure 106 is prepared on the semiconductor substrate 101, a first dielectric layer 107 is filled between the bit lines 104, then a photoresist-covered shielding region 107a is formed on the first dielectric layer 107 by photolithography, and the first dielectric layer 107 in the region except the shielding region 107a is removed by dry etching. After etching, filling a conductive layer 108 in the area where the dielectric layer is removed, removing the conductive layer 108 in the conductive layer etching area 107b by photoetching and dry etching, and filling a second dielectric layer 109 to realize isolation, thereby finally forming the capacitor connecting line structure 106. It should be noted that the oval capacitor connection line structure 106 is only for marking the design position of the structure, and the actual shape of the capacitor connection line structure 106 is commonly defined by the photoresist and the bit line 104; for simplicity of illustration, the active regions are not labeled in fig. 2.
In the prior art solution described above, etching of the conductive layer 108 is an important process step. Fig. 3 is a partial cross-sectional view of the conductive layer 108 at AA' after etching, and the desired topography of the conductive layer trench 108a after etching should be a vertical trench with vertical sidewalls that can completely isolate the conductive layer 108 on both sides. However, in the prior art, the conductive layer 108 is generally made of a polysilicon material, and the morphology of the conductive layer trench 108a is easily poor due to the unstable etching process during the etching process of the polysilicon material. As shown in fig. 4, when an etch stop (etch stop) defect occurs in the bottom region during etching, the etch stop trench 108b cannot completely block the conductive layers 108 on both sides, so that a short circuit occurs between the capacitor connection line structures 106 formed on both sides. As shown in fig. 5, when a drum-shaped sidewall (bowing profile) defect occurs during the etching process due to poor sidewall deposition protection, the resistance of the capacitor connecting line structure 106 formed on both sides is uneven, and the local resistance is too high or even is broken.
Referring to fig. 6 to 21, the present invention provides a method for manufacturing a capacitor connection line structure of a semiconductor memory, which includes the following steps:
1) Providing a semiconductor substrate 201, wherein the surface of the semiconductor substrate 201 comprises a plurality of active areas 201a which are arranged at intervals, and a plurality of bit lines 204 connected with the active areas 201a are formed on the semiconductor substrate 201;
2) Forming an interlayer dielectric layer 205 on the semiconductor substrate 201, wherein the interlayer dielectric layer 205 fills the gaps between the bit lines 204 and the outside area of the bit lines 204;
3) Forming first capacitance connection holes 205a in the interlayer dielectric layer 205, wherein the first capacitance connection holes 205a are distributed on part of the active region 201a between the bit lines 204 and expose part of the active region 201a;
4) Forming a sacrificial dielectric layer 208 in the first capacitance connecting hole 205a, wherein the sacrificial dielectric layer 208 at least fills the first capacitance connecting hole 205a;
5) Forming second capacitance connection holes 205b in the interlayer dielectric layer 205, wherein the second capacitance connection holes 205b are distributed on a part of the active region 201a between the bit lines 204, and expose a part of the active region 201a, and are separated from the first capacitance connection holes 205a by the interlayer dielectric layer 205; and
6) The sacrificial dielectric layer 208 is removed, and a conductive layer 212 is formed in the first capacitor connection hole 205a and the second capacitor connection hole 205b, and the conductive layer 212 fills the first capacitor connection hole 205a and the second capacitor connection hole 205b, thereby forming a first capacitor connection line structure 213a and a second capacitor connection line 213b structure, respectively.
In step 1), referring to step S1 of fig. 6, fig. 7 (a) and fig. 8 (a) - (C), a semiconductor substrate 201 is provided, wherein a surface of the semiconductor substrate 201 includes a plurality of active regions 201a arranged at intervals, and a plurality of bit lines 204 connected to the active regions 201a are formed on the semiconductor substrate 201. Optionally, before forming the bit line 204 on the semiconductor substrate 201, a step of sequentially forming a shallow trench isolation structure 202 and a buried word line 203 in the semiconductor substrate is further included, where the plurality of active regions 201a are isolated by the shallow trench isolation structure 202. The buried word line 203 is formed in the trench of the semiconductor substrate 201, and includes a gate dielectric layer 203c, a conductive material layer 203b, and a word line isolation layer 203a. The gate dielectric layer 203c is formed at the bottom and on the side wall of the trench, the conductive material layer 203b is formed in the trench, the word line isolation layer 203a is located above the conductive material layer 203b, and wraps the conductive material layer 203b together with the gate dielectric layer 203c, and the conductive material layer 203b is connected with the active region 201a through the gate dielectric layer 203 c. The bit line 204 includes a stacked structure and a sidewall structure 204d covering the periphery of the stacked structure, where the stacked structure includes an isolation insulating layer 204c, a conductive line main body layer 204b, and a top dielectric layer 204a stacked in sequence from bottom to top. The material constituting the conductive line body layer 204b includes tungsten or a tungsten composite, and the materials of the isolation insulating layer 204c, the top dielectric layer 204a and the sidewall structure 204d include silicon nitride. The bit line 204 is connected to the active region 201a via the bit line contact 204e, and the material forming the bit line contact 204e comprises tungsten or polysilicon. It should be noted that, for simplicity and convenience of labeling, the active areas are not labeled in the cross-sectional views corresponding to the plane structure diagrams in the embodiment; fig. 8 (a) is a schematic cross-sectional view at AA ' in fig. 7 (a), fig. 8 (B) is a schematic cross-sectional view at BB ' in fig. 7 (a), fig. 8 (C) is a schematic cross-sectional view at CC ' in fig. 7 (a), and the correspondence relationships of (a) to (C) in fig. 9 to 21 are the same as described in fig. 8.
In step 2), referring to step S2 of fig. 6, fig. 7 (a) and fig. 8 (a) - (C), an interlayer dielectric layer 205 is formed on the semiconductor substrate 201, and the interlayer dielectric layer 205 fills the gaps between the bit lines 204 and the outer regions of the bit lines 204. Optionally, the interlayer dielectric layer 205 comprises a silicon dioxide layer formed from spin-on dielectric (SOD, spin on dielectric) silicon dioxide obtained by spin-on methods. In this embodiment, the upper surface of the interlayer dielectric layer 205 is flush with the upper surface of the bit line 204.
In step 3), referring to step S3 of fig. 6, in fig. 7 (a) and fig. 8 (a) - (C) to fig. 10 (a) - (C), a first capacitor connection hole 205a is formed in the interlayer dielectric layer 205, and the first capacitor connection hole 205a is distributed on a portion of the active region 201a between the bit lines 204 and exposes a portion of the active region 201a. Optionally, the method for forming the first capacitor connection hole 205a includes forming a patterned etching barrier layer above the interlayer dielectric layer 205 and the bit line 204, and forming the first capacitor connection hole 205a by dry etching with the etching barrier layer as an etching mask. In this embodiment, a hard mask layer 206 is deposited on the interlayer dielectric layer 205 and the upper surface of the bit line 204. The hard mask layer 206 comprises a Spin On Carbon (SOC) layer. A first anti-reflection layer 207a and a first photoresist barrier layer 207 are coated on the upper surface of the hard mask layer 206, and the patterned first photoresist barrier layer 207 is obtained by exposure and development, as shown in fig. 8 (a) to (C). As shown in fig. 7 (a), the coverage of the patterned first photoresist barrier 207 is shown as a first coverage area 207 b. The first anti-reflection layer 207a includes a silicon oxynitride layer. The first capacitor connection hole 205a is obtained by dry etching using the first photoresist barrier layer 207 as an etching mask. Since the first photoresist barrier layer 207 is thinner, when it is depleted during etching, the etching process is continued instead with the hard mask layer 206 of its lower layer as an etching mask. Optionally, the dry etching pressure range is 30-50 mT, the 3Mhz rf power range is 2000-4000W, the 40Mhz rf power range is 1000-3000W, the etching gas contains C 4F6/C4F8/O2/Ar, CHF-based gases such as CHF 3 are doped in the etching gas when the first anti-reflective layer 207a made of silicon oxynitride is etched, so as to increase the etching rate of the silicon oxynitride layer, and CHF-based gases such as CHF 3 are not doped when the interlayer dielectric layer 205 is etched, to improve the selectivity to silicon nitride and reduce the damage to the sidewall structure 204d and the top dielectric layer 204a in the bit line 204. Finally, the first capacitor connection hole 205a is obtained after the dry etching, as shown in fig. 9 (a) to (C). The hard mask layer 206 remaining after etching is removed by ashing (PLASMA ASHING), as shown in fig. 10 (a) to (C).
In step 4), referring to step S4 of fig. 6, in fig. 7 (a) and fig. 11 (a) - (C), a sacrificial dielectric layer 208 is formed in the first capacitor connection hole 205a, and the sacrificial dielectric layer 208 at least fills the first capacitor connection hole 205a. Optionally, the sacrificial dielectric layer 208 is spin-coated with a carbon material layer (SOC), and the sacrificial dielectric layer 208 also covers the interlayer dielectric layer 205 and the upper surface of the bit line 204, where the upper surface of the sacrificial dielectric layer 208 is higher than the upper surface of the bit line 204 by 200-400 nm, and in this embodiment, preferably 300nm.
In step 5), referring to step S5 of fig. 6, in fig. 7 (a), (B) and fig. 11 (a) - (C) to fig. 12 (a) - (C), a second capacitor connection hole 205B is formed in the interlayer dielectric layer 205, and the second capacitor connection hole 205B is distributed on a portion of the active region 201a between the bit lines 204, and exposes a portion of the active region 201a, and is separated from the first capacitor connection hole 205a by the interlayer dielectric layer 205. Optionally, the method for forming the second capacitor connection hole 205b includes forming a patterned etching barrier layer above the interlayer dielectric layer 205, the bit line 204 and the sacrificial dielectric layer 208, and forming the second capacitor connection hole 205b by dry etching with the etching barrier layer as an etching mask. In this embodiment, a second anti-reflection layer 209a and a second photoresist barrier layer 209 are coated on the upper surface of the sacrificial dielectric layer 208, and the patterned second photoresist barrier layer 209 is obtained by exposing and developing, as shown in fig. 11 (a) to (C). As shown in fig. 7 (B), the coverage of the patterned second photoresist barrier 209 is shown as a second coverage area 209B. The second capacitance connection hole 205b is obtained by dry etching, as shown in fig. 12 (a) to (C). Since the second photoresist barrier 209 is thinner, when it is depleted during etching, the etching process is continued instead with the sacrificial dielectric layer 208 underneath as an etching mask. Optionally, the dry etching pressure ranges from 30 to 50mt, the 3Mhz power ranges from 2000 to 4000W, the 40Mhz power ranges from 1000 to 3000W, the etching gas contains C 4F6/C4F8/O2/Ar, and when the first anti-reflective layer 207a is etched, the etching gas may be doped with CHF 3 to increase the etching rate of the silicon oxynitride layer, and when the interlayer dielectric layer 205 is etched, CHF 3 or other CHF-based gas is not doped, so as to increase the selectivity ratio of silicon nitride and reduce the damage to the sidewall structures 204d and the top dielectric layer 204a in the bit line 204.
In step 6), referring to step S6 of fig. 6, in fig. 7 (a) and fig. 12 (a) - (C) to fig. 21 (a) - (C), the sacrificial dielectric layer 208 is removed, and a conductive layer 212 is formed in the first capacitor connection hole 205a and the second capacitor connection hole 205b, and the conductive layer 212 fills the first capacitor connection hole 205a and the second capacitor connection hole 205b, thereby forming a first capacitor connection line structure 213a and a second capacitor connection line 213b structure, respectively. Alternatively, the sacrificial dielectric layer 208 is removed by ashing, exposing the first capacitor connection hole 205a, as shown in fig. 13 (a) to (C). As shown in fig. 7 (a), in the present invention, the capacitor connection line structure 213 is divided into a first capacitor connection line structure 213a and a second capacitor connection line structure 213b, and the conductive layer 212 is filled in the first capacitor connection hole 205a and the second capacitor connection hole 205b, respectively.
As an example, before forming the conductive layer in the first and second capacitance connection holes 205a and 205b, a step of forming an isolation dielectric layer on sidewall surfaces of the first and second capacitance connection holes 205a and 205b is further included. The isolation dielectric layer at least comprises a first isolation dielectric layer 210 and a second isolation dielectric layer 211, the first isolation dielectric layer 210 is formed on the side wall surfaces of the first capacitor connection hole 205a and the second capacitor connection hole 205b, and the second isolation dielectric layer 211 is formed on the surface of the first isolation dielectric layer 210. Optionally, in forming the first isolation dielectric layer 210, atomic layer deposition (ALD, atomic layer deposition) is used to deposit the first isolation dielectric layer 210 on the upper surface of the bit line 204, the upper surface of the interlayer dielectric layer 205, and the sidewalls and bottoms of the first capacitor connection hole 205a and the second capacitor connection hole 205b, where the first isolation dielectric layer 210 includes a silicon dioxide layer, as shown in fig. 14 (a) - (C). The upper surface of the bit line 204, the upper surface of the interlayer dielectric layer 205, and the first isolation dielectric layer 210 deposited at the bottoms of the first and second capacitance connection holes 205a and 205b are removed by dry etching, as shown in fig. 15 (a) to (C). The dry etching pressure range is 5-50 mT, the TCP power range is 500-800W, the bias voltage range is 100-500V, and the etching gas comprises CF 4/C4F8/CHF3/O2/Ar. After etching, the second isolation dielectric layer 211 is deposited on the upper surface of the bit line 204, the upper surface of the interlayer dielectric layer 205, the surface of the first isolation dielectric layer 210, and the bottoms of the first capacitor connection hole 205a and the second capacitor connection hole 205b by using an atomic layer, where the second isolation dielectric layer 211 includes a silicon nitride layer, as shown in fig. 16 (a) - (C). The upper surface of the bit line 204, the upper surface of the interlayer dielectric layer 205, and the second isolation dielectric layer 211 deposited at the bottoms of the first and second capacitance connection holes 205a and 205b are removed by dry etching, as shown in fig. 17 (a) to (C). The dry etching pressure range is 5-50 mT, the TCP power range is 500-800W, the bias voltage range is 100-500V, and the etching gas comprises CF 4/CHF3/O2/Ar. After etching, the second isolation dielectric layer 211 covers only the surface of the first isolation dielectric layer 210. By forming the first isolation dielectric layer 210 and the second isolation dielectric layer 211, the sidewall structure 204d formed by a silicon nitride layer on the sidewall of the bit line 204 is added, and a composite layer isolation structure of silicon nitride-silicon oxide-silicon nitride (N-O-N) is formed between the bit line 204 and the capacitor connection hole, as shown in fig. 17 (a) - (C).
As an example, the conductive layer 212 is formed to include at least a first conductive layer 212a and a second conductive layer 212b, the first conductive layer 212a being located above the active region, the second conductive layer 212b being located above the first conductive layer 212 a. Optionally, the first conductive layer 212a includes a polysilicon layer, and the first conductive layer 212a is deposited in the first capacitor connection hole 205a and the second capacitor connection hole 205b by chemical vapor deposition, and in this embodiment, the first conductive layer 212a is also deposited on the upper surfaces of the bit line 204 and the interlayer dielectric layer 205, as shown in fig. 18 (a) - (C). The first conductive layer 212a is etched back such that the upper surface of the first conductive layer 212a is lower than the upper surface of the bit line 204, as shown in fig. 19 (a) to (C). The second conductive layer 212b is deposited on the upper surface of the first conductive layer 212a within the first and second capacitive connection holes 205a and 205b, and the second conductive layer 212b includes tungsten or a tungsten composite. In this embodiment, the second conductive layer 212b is also deposited on the upper surfaces of the bit line 204 and the interlayer dielectric layer 205, as shown in fig. 20 (a) to (C). The second conductive layer 212b is polished by Chemical Mechanical Polishing (CMP) and exposes the tops of the underlying bit lines 204, the interlayer dielectric layer 205, the first isolation dielectric layer 210, and the second isolation dielectric layer 211 so that the entire top surface is flush. The conductive layer 212 is filled in the first capacitor connection hole 205a and the second capacitor connection hole 205b, and the first capacitor connection line structure 213a and the second capacitor connection line structure 213b are formed, respectively, as shown in fig. 21 (a) to (C).
Example two
Referring to fig. 7 (a), fig. 8 (a) to (C), fig. 13 (a) to (C), fig. 17 (a) to (C), and fig. 21 (a) to (C), the present invention further provides a semiconductor memory capacitor connecting line structure, including:
The surface of the semiconductor substrate 201 comprises a plurality of active areas 201a which are arranged at intervals;
A plurality of bit lines 204 on the semiconductor substrate 201 and connected to the active regions 201 a;
an interlayer dielectric layer 205 filling the gaps between the bit lines 204 and the outside regions of the bit lines 204;
a first capacitance connection hole 205a formed in the interlayer dielectric layer 205 and located on a portion of the active region 201a between the bit lines 204;
A second capacitance connection hole 205b formed in the interlayer dielectric layer 205, and located on a portion of the active region 201a between the bit lines 204, and separated from the first capacitance connection hole 205a by the interlayer dielectric layer 205;
A conductive layer 212 filled in the first capacitor connection hole 205a and the second capacitor connection hole 205b to form a first capacitor connection line structure 213a and a second capacitor connection line structure 213b, respectively, and connected to the active region 201a below; and
And an isolation dielectric layer covering the sidewalls of the conductive layer 212.
As shown in fig. 7 (a) and fig. 21 (a) - (C), a semiconductor substrate 201 including a plurality of active regions 201a arranged at intervals is provided, and a plurality of bit lines 204 are disposed on the semiconductor substrate 201, and the bit lines 204 are connected to the active regions 201 a. An interlayer dielectric layer 205 is filled in the gap between the bit lines 204 and the region outside the bit lines 204, and a first capacitor connection hole 205a and a second capacitor connection hole 205b are formed in the interlayer dielectric layer 205, as shown in fig. 13 (a) to (C). The first capacitor connection hole 205a and the second capacitor connection hole 205b are filled with a conductive layer 212, and a first capacitor connection line structure 213a and a second capacitor connection line structure 213b are formed, respectively, as shown in fig. 21 (a) to (C). The sidewalls of the conductive layer 212 are also formed with an isolation dielectric layer. The bit line 204 includes a stacked structure and a sidewall structure 204d covering the periphery of the stacked structure, where the stacked structure includes an isolation insulating layer 204c, a conductive line main body layer 204b, and a top dielectric layer 204a stacked in sequence from bottom to top. The material constituting the conductive line body layer 204b includes tungsten or a tungsten composite, and the materials of the isolation insulating layer 204c, the top dielectric layer 204a and the sidewall structure 204d include silicon nitride. The bit line 204 is connected to the active region 201a via the bit line contact 204e, and the material forming the bit line contact 204e includes tungsten or polysilicon, as shown in fig. 8 (a) to (C).
As an example, the isolation dielectric layer at least includes a first isolation dielectric layer 210 and a second isolation dielectric layer 211, the first isolation dielectric layer 210 is formed on the sidewall surfaces of the first capacitor connection hole 205a and the second capacitor connection hole 205b, and the second isolation dielectric layer 211 is formed on the surface of the first isolation dielectric layer 210. As shown in fig. 17 (a) to (C), the first isolation dielectric layer 210 and the second isolation dielectric layer 211 are sequentially formed on the sidewalls of the first capacitor connection hole 205a and the second capacitor connection hole 205 b. Optionally, the first isolation dielectric layer 210 includes a silicon dioxide layer, and the second isolation dielectric layer 211 includes a silicon nitride layer.
As an example, the conductive layer 212 includes at least a first conductive layer 212a and a second conductive layer 212b, the first conductive layer 212a being located above the active region 201a, and the second conductive layer 212b being located above the first conductive layer 212 a. Optionally, the first conductive layer 212a comprises a polysilicon layer and the second conductive layer 212b comprises tungsten or a tungsten composite. The upper surface of the second conductive layer 212b is flush with the upper surface of the bit line 204, as shown in fig. 21 (a) to (C).
As an example, the semiconductor memory capacitor connection line structure further includes a shallow trench isolation structure 202 and a buried word line 203 formed within the semiconductor substrate 201, the plurality of active regions 203a being isolated by the shallow trench isolation structure 202. Optionally, the buried word line 203 is formed in the trench of the semiconductor substrate 201, and includes a gate dielectric layer 203C, a conductive material layer 203b, and a word line isolation layer 203a, as shown in fig. 8 (a) - (C).
In summary, the present invention provides a semiconductor memory capacitor connecting wire structure and a preparation method thereof, wherein the preparation method comprises the following steps: 1) Providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a plurality of active areas which are arranged at intervals, and a plurality of bit lines connected with the active areas are formed on the semiconductor substrate; 2) Forming an interlayer dielectric layer on the semiconductor substrate, wherein the interlayer dielectric layer fills up gaps among the bit lines and the outer side areas of the bit lines; 3) Forming first capacitance connecting holes in the interlayer dielectric layer, wherein the first capacitance connecting holes are distributed on part of the active area between the bit lines and expose part of the active area; 4) Forming a sacrificial dielectric layer in the first capacitance connecting hole, wherein the sacrificial dielectric layer at least fills the first capacitance connecting hole; 5) Forming second capacitance connecting holes in the interlayer dielectric layer, wherein the second capacitance connecting holes are distributed on part of the active area between the bit lines, expose part of the active area and are separated from the first capacitance connecting holes through the interlayer dielectric layer; 6) And removing the sacrificial dielectric layer, forming a conductive layer in the first capacitance connecting hole and the second capacitance connecting hole, and filling the first capacitance connecting hole and the second capacitance connecting hole with the conductive layer to form a first capacitance connecting wire structure and a second capacitance connecting wire structure respectively. The invention also provides a semiconductor memory capacitor connecting wire structure, which comprises: the surface of the semiconductor substrate comprises a plurality of active areas which are distributed at intervals; a plurality of bit lines on the semiconductor substrate and connected to the active region; an interlayer dielectric layer filled in the gaps between the bit lines and the bit line outer area; the first capacitor connecting hole is formed in the interlayer dielectric layer and is positioned on part of the active area between the bit lines; the second capacitance connecting hole is formed in the interlayer dielectric layer, is positioned on part of the active area between the bit lines, and is separated from the first capacitance connecting hole through the interlayer dielectric layer; the conductive layer is filled in the first capacitance connecting hole and the second capacitance connecting hole to respectively form a first capacitance connecting wire structure and a second capacitance connecting wire structure, and the lower part of the conductive layer is connected with the active region; and the isolation medium layer is covered on the side wall of the conductive layer. The method for sequentially forming the first capacitor connecting hole and the second capacitor connecting hole by introducing two times of photoetching and etching avoids the problem of poor resistance of the capacitor connecting wire caused by poor appearance of the capacitor connecting hole after etching.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (12)
1. The preparation method of the semiconductor memory capacitor connecting wire structure is characterized by comprising the following steps of:
1) Providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a plurality of active areas which are arranged at intervals, and a plurality of bit lines connected with the active areas are formed on the semiconductor substrate;
2) Forming an interlayer dielectric layer on the semiconductor substrate, wherein the interlayer dielectric layer fills up gaps among the bit lines and the outer side areas of the bit lines;
3) Forming first capacitance connecting holes in the interlayer dielectric layer, wherein the first capacitance connecting holes are distributed on part of the active area between the bit lines and expose part of the active area;
4) Forming a sacrificial dielectric layer in the first capacitance connecting hole, wherein the sacrificial dielectric layer at least fills the first capacitance connecting hole;
5) Forming second capacitance connecting holes in the interlayer dielectric layer, wherein the second capacitance connecting holes are distributed on part of the active area between the bit lines, expose part of the active area and are separated from the first capacitance connecting holes through the interlayer dielectric layer; and
6) And removing the sacrificial dielectric layer, forming a conductive layer in the first capacitance connecting hole and the second capacitance connecting hole, and filling the first capacitance connecting hole and the second capacitance connecting hole with the conductive layer to form a first capacitance connecting wire structure and a second capacitance connecting wire structure respectively.
2. The method of claim 1, further comprising the step of forming an isolation dielectric layer on sidewall surfaces of the first and second capacitor connecting holes before forming the conductive layer in the first and second capacitor connecting holes in step 6).
3. The method of claim 2, wherein the isolation dielectric layer formed in step 6) comprises a first isolation dielectric layer and a second isolation dielectric layer, the first isolation dielectric layer is formed on the sidewall surfaces of the first capacitor connecting hole and the second capacitor connecting hole, and the second isolation dielectric layer is formed on the surface of the first isolation dielectric layer.
4. The method of claim 1, wherein in step 3), the method of forming the first capacitor connection hole includes forming a patterned etch stop layer over the interlayer dielectric layer and the bit line, and forming the first capacitor connection hole by dry etching using the etch stop layer as an etch mask.
5. The method of claim 1, wherein in step 5), the method of forming the second capacitor connection hole comprises forming a patterned etch stop layer over the interlayer dielectric layer, the bit line, and the sacrificial dielectric layer, and forming the second capacitor connection hole by dry etching using the etch stop layer as an etch mask.
6. The method of claim 5, wherein the sacrificial dielectric layer formed in step 4) is distributed on the surface of the interlayer dielectric layer in addition to filling the first capacitor connecting hole; in step 5), when the second capacitor connection hole is formed by dry etching, the patterned etching barrier layer is formed on the surface of the sacrificial dielectric layer, and the exposed part of the sacrificial dielectric layer is removed by dry etching.
7. The method of claim 1, wherein the conductive layer formed in step 6) comprises at least a first conductive layer and a second conductive layer, the first conductive layer being over the active region, the second conductive layer being over the first conductive layer.
8. The method of claim 1, wherein in step 1), before forming the bit line on the semiconductor substrate, further comprising forming a shallow trench isolation structure and a buried word line in the semiconductor substrate in sequence, wherein the plurality of active regions are isolated by the shallow trench isolation structure.
9. A semiconductor memory capacitor connecting line structure, comprising:
The surface of the semiconductor substrate comprises a plurality of active areas which are distributed at intervals;
a plurality of bit lines on the semiconductor substrate and connected to the active region;
An interlayer dielectric layer filled in the gaps between the bit lines and the bit line outer area;
The first capacitor connecting hole is formed in the interlayer dielectric layer and is positioned on part of the active area between the bit lines;
The second capacitance connecting hole is formed in the interlayer dielectric layer, is positioned on part of the active area between the bit lines, and is separated from the first capacitance connecting hole through the interlayer dielectric layer;
the conductive layer is filled in the first capacitance connecting hole and the second capacitance connecting hole to respectively form a first capacitance connecting wire structure and a second capacitance connecting wire structure, and the lower part of the conductive layer is connected with the active region; and
And the isolation medium layer is covered on the side wall of the conductive layer.
10. The semiconductor memory capacitor connecting line structure of claim 9, wherein the isolation dielectric layer comprises at least a first isolation dielectric layer and a second isolation dielectric layer, the first isolation dielectric layer is formed on sidewall surfaces of the first capacitor connecting hole and the second capacitor connecting hole, and the second isolation dielectric layer is formed on a surface of the first isolation dielectric layer.
11. The semiconductor memory capacitor connecting line structure of claim 9, wherein the conductive layer comprises at least a first conductive layer and a second conductive layer, the first conductive layer being located above the active region, the second conductive layer being located above the first conductive layer.
12. The semiconductor memory capacitor connecting line structure of claim 9, further comprising a shallow trench isolation structure and a buried word line formed within the semiconductor substrate, the plurality of active regions being isolated by the shallow trench isolation structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811100903.1A CN110931485B (en) | 2018-09-20 | 2018-09-20 | Semiconductor memory capacitor connecting wire structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811100903.1A CN110931485B (en) | 2018-09-20 | 2018-09-20 | Semiconductor memory capacitor connecting wire structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110931485A CN110931485A (en) | 2020-03-27 |
| CN110931485B true CN110931485B (en) | 2024-06-07 |
Family
ID=69856282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811100903.1A Active CN110931485B (en) | 2018-09-20 | 2018-09-20 | Semiconductor memory capacitor connecting wire structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110931485B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113496952B (en) * | 2020-04-08 | 2023-06-09 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000299444A (en) * | 1999-04-12 | 2000-10-24 | Hitachi Ltd | Semiconductor device and manufacture of the same |
| JP2001185701A (en) * | 1999-12-27 | 2001-07-06 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing it |
| US6576509B1 (en) * | 1999-08-18 | 2003-06-10 | Hitachi Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
| CN1525570A (en) * | 2003-02-24 | 2004-09-01 | ���ǵ�����ʽ���� | Semiconductor device and method of manufacturing the same |
| KR20070058112A (en) * | 2005-12-01 | 2007-06-07 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| CN104900584A (en) * | 2014-03-05 | 2015-09-09 | 爱思开海力士有限公司 | Semiconductor device with line-type air gaps and method for fabricating the same |
| CN106941097A (en) * | 2016-01-05 | 2017-07-11 | 华邦电子股份有限公司 | Semiconductor device and its manufacture method |
| CN107946302A (en) * | 2017-12-06 | 2018-04-20 | 睿力集成电路有限公司 | Semiconductor memory and its manufacture method |
| CN108231738A (en) * | 2017-12-29 | 2018-06-29 | 睿力集成电路有限公司 | Semiconductor device structure and its manufacturing method |
| CN208722878U (en) * | 2018-09-20 | 2019-04-09 | 长鑫存储技术有限公司 | Semiconductor memory capacitance connection cable architecture |
-
2018
- 2018-09-20 CN CN201811100903.1A patent/CN110931485B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000299444A (en) * | 1999-04-12 | 2000-10-24 | Hitachi Ltd | Semiconductor device and manufacture of the same |
| US6576509B1 (en) * | 1999-08-18 | 2003-06-10 | Hitachi Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
| JP2001185701A (en) * | 1999-12-27 | 2001-07-06 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing it |
| CN1525570A (en) * | 2003-02-24 | 2004-09-01 | ���ǵ�����ʽ���� | Semiconductor device and method of manufacturing the same |
| KR20070058112A (en) * | 2005-12-01 | 2007-06-07 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| CN104900584A (en) * | 2014-03-05 | 2015-09-09 | 爱思开海力士有限公司 | Semiconductor device with line-type air gaps and method for fabricating the same |
| CN106941097A (en) * | 2016-01-05 | 2017-07-11 | 华邦电子股份有限公司 | Semiconductor device and its manufacture method |
| CN107946302A (en) * | 2017-12-06 | 2018-04-20 | 睿力集成电路有限公司 | Semiconductor memory and its manufacture method |
| CN108231738A (en) * | 2017-12-29 | 2018-06-29 | 睿力集成电路有限公司 | Semiconductor device structure and its manufacturing method |
| CN208722878U (en) * | 2018-09-20 | 2019-04-09 | 长鑫存储技术有限公司 | Semiconductor memory capacitance connection cable architecture |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110931485A (en) | 2020-03-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9082784B2 (en) | Method of fabricating a semiconductor device having stacked storage nodes of capacitors in cell region separated from peripheral region | |
| KR20020012857A (en) | Method of manufacturing semiconductor device including metal contact and capacitor | |
| KR100799125B1 (en) | Method for manufacturing a semiconductor device having a capacitor | |
| KR20120067126A (en) | Semiconductor device and method for manufacturing the same | |
| KR20120066787A (en) | Semiconductor device with buried gate and method for fabricating the same | |
| KR20030003906A (en) | Method of forming contact of semiconductor device and semiconductor memory device fabricated by the same method | |
| CN110931485B (en) | Semiconductor memory capacitor connecting wire structure and preparation method thereof | |
| US7902631B2 (en) | Contact plug structure | |
| KR20050116421A (en) | Method of forming self-aligned contact in semiconductor memory device and method of fabricating the semiconductor memory device using the method | |
| CN208722878U (en) | Semiconductor memory capacitance connection cable architecture | |
| TWI681507B (en) | Via contact, memory device, and method of forming semiconductor structure | |
| US20050142830A1 (en) | Method for forming a contact of a semiconductor device | |
| CN110970351B (en) | Capacitor contact structure of semiconductor memory and preparation method thereof | |
| WO2020125515A1 (en) | Semiconductor structure and forming method therefor | |
| US7199013B2 (en) | Semiconductor device and method for fabricating the same | |
| US7268085B2 (en) | Method for fabricating semiconductor device | |
| US20220051933A1 (en) | Semiconductor device and method for manufacturing the same | |
| WO2022077959A1 (en) | Memory and manufacturing method therefor | |
| CN113948462B (en) | Semiconductor structure and forming method thereof | |
| US20220216211A1 (en) | Buried word line structure and manufacturing method thereof | |
| WO2021022811A1 (en) | Semiconductor structure and forming method therefor | |
| CN110970351A (en) | Semiconductor memory capacitor contact structure and preparation method | |
| KR100681207B1 (en) | A method for forming a contact plug in semiconductor device | |
| CN117995759A (en) | Semiconductor structure, preparation method thereof and memory | |
| CN115910784A (en) | Vertical transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |