CN112802758A - 基板制备方法及基板结构、芯片封装方法及芯片封装结构 - Google Patents
基板制备方法及基板结构、芯片封装方法及芯片封装结构 Download PDFInfo
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- CN112802758A CN112802758A CN202011576413.6A CN202011576413A CN112802758A CN 112802758 A CN112802758 A CN 112802758A CN 202011576413 A CN202011576413 A CN 202011576413A CN 112802758 A CN112802758 A CN 112802758A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/02381—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (10)
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CN202011576413.6A CN112802758B (zh) | 2020-12-28 | 2020-12-28 | 基板制备方法及基板结构、芯片封装方法及芯片封装结构 |
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CN202011576413.6A CN112802758B (zh) | 2020-12-28 | 2020-12-28 | 基板制备方法及基板结构、芯片封装方法及芯片封装结构 |
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CN112802758A true CN112802758A (zh) | 2021-05-14 |
CN112802758B CN112802758B (zh) | 2022-08-05 |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060289203A1 (en) * | 2003-05-19 | 2006-12-28 | Dai Nippon Printing Co., Ltd. | Double-sided wiring board, double sided wiring board manufacturing method, and multilayer wiring board |
JP2010129650A (ja) * | 2008-11-26 | 2010-06-10 | Kyocera Corp | 複合配線基板の製造方法 |
JP2012227310A (ja) * | 2011-04-19 | 2012-11-15 | Panasonic Corp | セラミックス多層基板とその製造方法 |
TW201349974A (zh) * | 2012-05-28 | 2013-12-01 | Zhen Ding Technology Co Ltd | 多層電路板及其製作方法 |
US20140085846A1 (en) * | 2012-09-24 | 2014-03-27 | Qing Ma | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
CN106206466A (zh) * | 2016-08-17 | 2016-12-07 | 友达光电(昆山)有限公司 | 玻璃中介层结构及其制备方法 |
-
2020
- 2020-12-28 CN CN202011576413.6A patent/CN112802758B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060289203A1 (en) * | 2003-05-19 | 2006-12-28 | Dai Nippon Printing Co., Ltd. | Double-sided wiring board, double sided wiring board manufacturing method, and multilayer wiring board |
JP2010129650A (ja) * | 2008-11-26 | 2010-06-10 | Kyocera Corp | 複合配線基板の製造方法 |
JP2012227310A (ja) * | 2011-04-19 | 2012-11-15 | Panasonic Corp | セラミックス多層基板とその製造方法 |
TW201349974A (zh) * | 2012-05-28 | 2013-12-01 | Zhen Ding Technology Co Ltd | 多層電路板及其製作方法 |
US20140085846A1 (en) * | 2012-09-24 | 2014-03-27 | Qing Ma | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
CN106206466A (zh) * | 2016-08-17 | 2016-12-07 | 友达光电(昆山)有限公司 | 玻璃中介层结构及其制备方法 |
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Effective date of registration: 20230404 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |