CN112786686B - 一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管 - Google Patents

一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管 Download PDF

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CN112786686B
CN112786686B CN202110180298.9A CN202110180298A CN112786686B CN 112786686 B CN112786686 B CN 112786686B CN 202110180298 A CN202110180298 A CN 202110180298A CN 112786686 B CN112786686 B CN 112786686B
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贾护军
王笑伟
董梦宇
朱顺威
杨银堂
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Abstract

本发明提供了一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管；自下而上设置有：半绝缘衬底(1)、AlN成核层(2)、GaN缓冲层(3)和AlGaN势垒层(4)；所述AlGaN势垒层(4)的上表面从左到右分别设有源电极(5)、栅电极(6)和漏电极(7)；从栅电极(6)与源电极(5)之间的所述AlGaN势垒层(4)的表面处向下进行掺杂形成栅源间表面P型掺杂区域(8)；从栅电极(6)与漏电极(7)之间的所述AlGaN势垒层的表面处向下进行掺杂形成栅漏间表面P型掺杂区域(9)。本发明旨在提高器件击穿电压的同时可以改善直流特性与频率特性，增强器件的输出功率密度与功率附加效率。

Description

一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶 体管
技术领域
本发明属于高电子迁移率晶体管技术领域；尤其涉及一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管。
背景技术
氮化镓作为新一代宽禁带半导体，比其他材料的临界击穿电场更大、禁带宽度更宽，使得它在同样尺寸下可以承受更大的功率密度，电子饱和速度更高，可以提高器件的频率特性与输出电流，抗辐照特性更好，可以大大提升器件的稳定性。对于AlGaN/GaN异质结，由于自发极化和压电极化效应，可以在异质结界面处产生高浓度和高迁移率的2DEG，因此GaN基功率器件在微波功率放大方面展现出前所未有的应用前景。
传统的AlGaN/GaN高电子迁移率晶体管具有耐压性差、寄生电容大以及跨导饱和区窄等特点，严重影响着器件功率密度和功率附加效率的输出，制约着微波功率放大器的整体性能。目前，针对AlGaN/GaN高电子迁移率晶体管，进行的研究主要集中在对器件的势垒层、缓冲层以及栅极形状的改进。对AlGaN/GaN异质结器件进行研究工作的重点在于异质结界面处的二维电子气，AlGaN势垒层的变化很容易使器件的直流特性发生恶化，因此如何在保证器件直流工作状态的前提下提升器件的交流特性与效率输出能力是一大难题。
发明内容
本发明的目的是提供了一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管。
本发明是通过以下技术方案实现的：
本发明涉及一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管，自下而上设置有：半绝缘衬底1、AlN成核层2、GaN缓冲层3和AlGaN势垒层4；其中，所述AlGaN势垒层4的上表面从左到右分别设有源电极5、栅电极6和漏电极7；从栅电极6与源电极5之间的所述AlGaN势垒层4的表面处向下进行掺杂形成栅源间表面P型掺杂区域8；从栅电极6与漏电极7之间的所述AlGaN势垒层的表面处向下进行掺杂形成栅漏间表面P型掺杂区域9。
优选地，所述栅源间表面P型掺杂区域8的掺杂深度为10nm，掺杂浓度为1×1016cm-3；所述栅漏间表面P型掺杂区域9的掺杂深度为10nm，掺杂浓度为1×1016cm-3。
优选地，所述栅源间表面P型掺杂区域8的宽度为栅电极6与源电极5之间的距离，所述栅漏间表面P型掺杂区域9的宽度为栅电极6与漏电极7之间的距离。
优选地，所述源电极5、栅电极6、漏电极7的长度均为1μm，所述源电极5和栅电极6的间距为1μm，所述栅电极6和漏电极7的间距为2.5μm。
优选地，所述AlGaN势垒层4的厚度为25nm，所述GaN缓冲层3的厚度为3μm，所述AlN成核层2的厚度为40nm。
优选地，所述栅电极6通过肖特基接触与所述AlGaN势垒层相连，所述源电极(5)和漏电极7均通过欧姆接触与所述AlGaN势垒层相连。
本发明具有以下优点：
(1)本发明涉及的具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管使得击穿电压提高，本发明所涉及的GaN高电子迁移率晶体管器件的击穿发生在栅的漏侧边缘，通过引入势垒层表面的P型掺杂区域，增强了器件表面的耐压性，并在P型掺杂区域的边缘引入新的击穿点，有效的改善了栅极漏侧边缘的电场集中效应，使等势线分布更加均匀。
(2)本发明涉及的具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管使得频率特性改善；本发明通过引入P型掺杂区域，阻止了耗尽区向两侧源漏的扩展，而在垂直方向上进行分布，使栅源、栅漏电容减少，从而改善了器件的频率特性。
(3)本发明涉及的具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管使得效率输出能力增强；本发明所提出的结构具有较低的阈值电压与最大饱和跨导，器件的频率特性也得到优化，因此相比传统结构拥有了更高的功率附加效率，使得器件的微波输出特性得到提高。
附图说明
图1是本发明具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管的器件结构示意图；
图中：1为半绝缘衬底，2为AlN成核层，3是GaN缓冲层，4是AlGaN势垒层，5是源电极，6是栅电极，7是漏电极，8是栅源间表面P型掺杂区域，9是栅漏表面P型掺杂区域。
具体实施方式
下面结合具体实施例对本发明进行详细说明。应当指出的是，以下的实施实例只是对本发明的进一步说明，但本发明的保护范围并不限于以下实施例。
实施例
本实施例涉及一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管，见图1所示：自下而上设置有：半绝缘衬底1、AlN成核层2、GaN缓冲层3和AlGaN势垒层4；其中，所述AlGaN势垒层4的上表面从左到右分别设有源电极5、栅电极6和漏电极7；从栅电极6与源电极5之间的所述AlGaN势垒层4的表面处向下进行掺杂形成栅源间表面P型掺杂区域8；从栅电极6与漏电极7之间的所述AlGaN势垒层的表面处向下进行掺杂形成栅漏间表面P型掺杂区域9。
进一步地，所述栅源间表面P型掺杂区域8的掺杂深度为10nm，掺杂浓度为1×1016cm-3；所述栅漏间表面P型掺杂区域9的掺杂深度为10nm，掺杂浓度为1×1016cm-3。
进一步地，所述栅源间表面P型掺杂区域8的宽度为栅电极6与源电极5之间的距离，所述栅漏间表面P型掺杂区域9的宽度为栅电极6与漏电极7之间的距离。
进一步地，所述源电极5、栅电极6、漏电极7的长度均为1.0μm，所述源电极5和栅电极6的间距为1μm，所述栅电极6和漏电极7的间距为2.5μm。
进一步地，所述AlGaN势垒层4的厚度为25nm，所述GaN缓冲层3的厚度为3μm，所述AlN成核层2的厚度为40nm。
进一步地，所述栅电极6通过肖特基接触与所述AlGaN势垒层相连，所述源电极(5)和漏电极7均通过欧姆接触与所述AlGaN势垒层相连。
与现有技术相比，本发明具有以下优点：本发明涉及的具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管使得击穿电压提高，本发明所涉及的GaN高电子迁移率晶体管器件的击穿发生在栅的漏侧边缘，通过引入势垒层表面的P型掺杂区域，增强了器件表面的耐压性，并在P型掺杂区域的边缘引入新的击穿点，有效的改善了栅极漏侧边缘的电场集中效应，使等势线分布更加均匀。本发明涉及的具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管使得频率特性改善；本发明通过引入P型掺杂区域，阻止了耗尽区向两侧源漏的扩展，而在垂直方向上进行分布，使栅源、栅漏电容减少，从而改善了器件的频率特性。本发明涉及的具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管使得效率输出能力增强；本发明所提出的结构具有较低的阈值电压与最大饱和跨导，器件的频率特性也得到优化，因此相比传统结构拥有了更高的功率附加效率，使得器件的微波输出特性得到提高。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变形或修改，这并不影响本发明的实质。

Claims (1)

1.一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管，其特征在于，自下而上设置有：半绝缘衬底(1)、AlN成核层(2)、GaN缓冲层(3)和AlGaN势垒层(4)；
其中，所述AlGaN势垒层(4)的上表面从左到右分别设有源电极(5)、栅电极(6)和漏电极(7)；从栅电极(6)与源电极(5)之间的所述AlGaN势垒层(4)的表面处向下进行掺杂形成栅源间表面P型掺杂区域(8)；从栅电极(6)与漏电极(7)之间的所述AlGaN势垒层的表面处向下进行掺杂形成栅漏间表面P型掺杂区域(9)；
所述栅源间表面P型掺杂区域(8)的掺杂深度为10nm，掺杂浓度为1×1016cm-3；所述栅漏间表面P型掺杂区域(9)的掺杂深度为10nm，掺杂浓度为1×1016cm-3；
所述栅源间表面P型掺杂区域(8)的宽度为栅电极(6)与源电极(5)之间的距离，所述栅漏间表面P型掺杂区域(9)的宽度为栅电极(6)与漏电极(7)之间的距离；
所述源电极(5)、栅电极(6)、漏电极(7)的长度均为1μm，所述源电极(5)和栅电极(6)的间距为1μm，所述栅电极(6)和漏电极(7)的间距为2.5μm；
所述AlGaN势垒层(4)的厚度为25nm，所述GaN缓冲层(3)的厚度为3μm，所述AlN成核层(2)的厚度为40nm；
所述栅电极(6)通过肖特基接触与所述AlGaN势垒层相连，所述源电极(5)和漏电极(7)均通过欧姆接触与所述AlGaN势垒层相连。
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