CN107017293A - 一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管 - Google Patents

一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管 Download PDF

Info

Publication number
CN107017293A
CN107017293A CN201710242816.9A CN201710242816A CN107017293A CN 107017293 A CN107017293 A CN 107017293A CN 201710242816 A CN201710242816 A CN 201710242816A CN 107017293 A CN107017293 A CN 107017293A
Authority
CN
China
Prior art keywords
algan
potential barrier
gan
source
algan potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710242816.9A
Other languages
English (en)
Inventor
贾护军
罗烨辉
吴秋媛
杨银堂
柴常春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN201710242816.9A priority Critical patent/CN107017293A/zh
Publication of CN107017293A publication Critical patent/CN107017293A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66431Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,结构自下而上包括:半绝缘衬底、AlN成核层、GaN缓冲层和AlGaN势垒层,其中,所述AlGaN势垒层的上表面的两侧分别设有源电极和漏电极、源电极和漏电极之间且靠近源电极处设有栅电极,在栅电极的源侧区域一部分AlGaN势垒层向下凹陷形成凹陷栅源势垒层区域,在栅电极的漏侧区域一部分AlGaN势垒层向下凹陷形成凹陷栅漏势垒层区域。本发明的有益之处在于:(1)跨导饱和区扩展;(2)击穿电压提高;(3)频率特性改善;(4)微波输出特性增强。

Description

一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶 体管
技术领域
本发明涉及一种AlGaN/GaN异质结场效应晶体管,具体涉及一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,属于场效应晶体管技术领域。
背景技术
氮化镓(GaN)作为第三代宽禁带半导体材料,其所具有的高电子饱和速度、高耐压性、抗辐照、耐高温等特点,弥补了传统硅材料和砷化镓材料在大功率密度、高温、高频应用领域中的不足。同时,GaN材料所具备的优越的功率品质因数,使得以GaN为基础的AlGaN/GaN高电子迁移率晶体管(HEMT),在微波大功率应用上,有着更为广阔的发展前景。
目前,基于GaN HEMT的微波功率放大器,多是采用外围电路对功率管的调控以及补偿等方式来实现高效率的输出环境。随着无线通讯系统、相控雷达、航空航天等领域的发展,对微波功率放大器的要求越来越高,常规GaN HEMT器件结构耐压低、寄生电容大以及跨导饱和区窄等特点,严重影响着器件大功率密度和高附加效率的输出,制约着微波功率放大器的整体性能。
发明内容
为解决现有技术的不足,本发明的目的在于提供一种耐压高、寄生电容低、跨导饱和区宽的AlGaN/GaN异质结场效应晶体管,从而提高器件的射频输出特性,使器件具备高能效的输出能力。
为了实现上述目标,本发明采用如下的技术方案:
一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,结构自下而上包括:半绝缘衬底、AlN成核层、GaN缓冲层和AlGaN势垒层,其特征在于,前述AlGaN势垒层的上表面的两侧分别设有源电极和漏电极、源电极和漏电极之间且靠近源电极处设有栅电极,在栅电极的源侧区域一部分AlGaN势垒层向下凹陷形成凹陷栅源势垒层区域,在栅电极的漏侧区域一部分AlGaN势垒层向下凹陷形成凹陷栅漏势垒层区域。
前述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,前述凹陷栅源势垒层区域和凹陷栅漏势垒层区域均是通过在AlGaN势垒层的表面进行光刻、刻蚀形成的。
前述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,前述凹陷栅源势垒层区域的长度为0.5μm、刻蚀深度为5nm,前述凹陷栅漏势垒层区域的长度为0.6μm、刻蚀深度为4nm。
前述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,前述栅电极的长度为1.0μm,栅源间距为1μm,栅漏间距为2.5μm。
前述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,前述栅电极通过肖特基接触与AlGaN势垒层相连,前述源电极和漏电极均通过欧姆接触与AlGaN势垒层相连。
前述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,前述GaN缓冲层具有n型电阻特性或半绝缘特性。
前述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,前述半绝缘衬底为硅衬底、碳化硅衬底或蓝宝石衬底。
本发明的有益之处在于:
一、跨导饱和区扩展
凹陷栅源势垒层区域和凹陷栅漏势垒层区域的存在,使得在栅下沟道两侧形成了高阻区域,对沟道电流的增长起到了缓冲作用,使得跨导接近饱和区后,随着栅源电压进一步升高,跨导增长的速度减缓,跨导不会处于急速上升和急速下降的状态,跨导饱和区得到了有效延长。
与常规GaN HEMT相比,具有双凹陷AlGaN势垒层的GaN HEMT拥有更宽的饱和跨导区间。
二、击穿电压提高
由于凹陷栅漏势垒层区域的存在,其有效的改善了栅电极漏侧边缘的电场集中效应,所以等势线分布更加均匀。
同时,栅电极漏侧AlGaN势垒区的向下凹陷,抑制了栅下耗尽层往漏极的延展,在一定漏压下,减小了电子从肖特基栅注入到表面的概率,降低了表面泄露电流。
所以与常规GaN HEMT相比,具有双凹陷AlGaN势垒层的GaN HEMT能够承受更大的漏极击穿电压,提高了器件的耐压性能。
三、频率特性改善
对于具有双凹陷AlGaN势垒层的GaN HEMT,栅电极两侧凹陷势垒层区域有效的抑制了栅下耗尽层对源/漏极区域的延伸,使得其拥有比常规结构更小的栅源电容和栅漏电容。
仿真结果显示,具有双凹陷AlGaN势垒层的GaN HEMT的最大振荡频率达到64GHz,比常规结构增长了12.3%,单边功率增益和最大可获得增益比常规GaN HEMT增长了1.2dB和0.8dB,仿真结果如图2所示。
四、微波输出特性增强
更低的寄生栅源、栅漏电容,更宽的跨导饱和区域以及优异的频率特性,增强了器件的功率、效率输出能力。
微波特性仿真验证,在S波段,具有双凹陷AlGaN势垒层的GaN HEMT的最大功率附加效率和饱和输出功率密度均高于常规GaN HEMT的输出能力,如图3所示。
附图说明
图1是本发明的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管的剖面结构示意图;
图2是常规GaN HEMT器件与具有双凹陷AlGaN势垒层GaN HEMT器件的小信号高频特性曲线对比图;
图3是常规GaN HEMT器件与具有双凹陷AlGaN势垒层GaN HEMT器件的微波输出特性对比图;
图4是本发明的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管的制作流程图。
图中附图标记的含义:1-半绝缘衬底、2-AlN成核层、3-GaN缓冲层、4-AlGaN势垒层、5-源电极、6-漏电极、7-栅电极、8-凹陷栅源势垒层区域、9-凹陷栅漏势垒层区域。
具体实施方式
为了提高和改善GaN HEMT的微波输出特性,使其具备高能效的输出能力,我们在常规GaN HEMT器件结构的基础上进行了改进。
以下结合附图和具体实施例对本发明作具体的介绍。
一、改进后的AlGaN/GaN异质结场效应晶体管的结构
参照图1,本发明的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,结构自下而上包括:半绝缘衬底1、AlN成核层2、GaN缓冲层3和AlGaN势垒层4。
半绝缘衬底1为硅衬底、碳化硅衬底或蓝宝石衬底。
GaN缓冲层3具有n型电阻特性或半绝缘特性。
AlGaN势垒层4的上表面的两侧分别设有源电极5和漏电极6,二者均通过欧姆接触与AlGaN势垒层4相连,源电极5和漏电极6之间且靠近源电极5处设有栅电极7,栅电极7通过肖特基接触与AlGaN势垒层4相连。
在栅电极7的源侧区域,一部分AlGaN势垒层4向下凹陷形成凹陷栅源势垒层区域8;在栅电极7的漏侧区域,一部分AlGaN势垒层4向下凹陷形成凹陷栅漏势垒层区域9。凹陷栅源势垒层区域8和凹陷栅漏势垒层区域9均是通过在AlGaN势垒层4的表面进行光刻、刻蚀形成的。
作为一种优选的方案,凹陷栅源势垒层区域8的长度为0.5μm、刻蚀深度为5nm,凹陷栅漏势垒层区域9的长度为0.6μm、刻蚀深度为4nm,栅电极7的长度为1.0μm,栅源间距为1μm,栅漏间距为2.5μm。
二、改进后的AlGaN/GaN异质结场效应晶体管的制作方法
参照图1和图4,本发明的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其制作方法如下:
(1)、对半绝缘衬底1(SiC衬底)进行清洗,去除表面污物;
(2)、在半绝缘衬底1(SiC衬底)上通过金属-有机物化学气相淀积(MOCVD)技术,淀积生长40nm厚的AlN成核层2;
(3)、在AlN成核层2上淀积生长3μm厚、浓度为1.0×1015cm-3的n型GaN缓冲层3;
(4)、在GaN缓冲层3上方异质外延生长AlGaN势垒层4,在AlGaN势垒层4薄膜生长过程中,控制势垒层中Al含量为0.25,AlGaN势垒层4高度为25nm;
(5)、在AlGaN势垒层4上依次进行光刻和隔离注入,形成隔离区和有源区;
(6)、对有源区依次进行源漏光刻,利用磁控溅射技术形成Ti/Al/Ni/Au四层合金层,金属剥离并高温退火,形成1μm长的源电极5和漏电极6,源电极5和漏电极6与AlGaN势垒层4形成良好的欧姆接触;
(7)、对栅源之间需要凹陷的势垒层区域进行光刻,采用感应耦合等离子体(ICP)刻蚀技术,形成刻蚀深度和长度分别为5nm和0.5μm的凹陷栅源势垒层区域8;
(8)、对栅漏之间需要凹陷的势垒层区域进行光刻,采用感应耦合等离子体(ICP)刻蚀技术,形成刻蚀深度和长度分别为4nm和0.6μm的凹陷栅漏势垒层区域9;
(9)、对于凹陷栅源势垒层区域8与凹陷栅漏势垒层区域9之间,采用栅光刻板进行光刻,在AlGaN势垒层4表面电子束蒸发形成Ni/Au合金,金属剥离,形成1μm长的栅电极7,栅电极7与AlGaN势垒层4形成肖特基接触;
(10)、对所形成的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管进行表面钝化,形成电极压焊点,完成器件制作。
优选的是,栅电极7长为1μm,栅源间距为1μm,栅漏间距为2.5μm。
三、改进后的AlGaN/GaN异质结场效应晶体管的性能
我们对改进后的AlGaN/GaN异质结场效应晶体管与常规的AlGaN/GaN异质结场效应晶体管在小信号高频特性、微波输出特性这两方面做了比较。
1、小信号高频特性
图2是常规GaN HEMT器件与具有双凹陷AlGaN势垒层GaN HEMT器件的小信号高频特性曲线对比图。
图2的仿真结果显示,具有双凹陷AlGaN势垒层的GaN HEMT的最大振荡频率达到64GHz,比常规结构增长了12.3%,单边功率增益和最大可获得增益比常规GaN HEMT增长了1.2dB和0.8dB。
2、微波输出特性
图3是常规GaN HEMT器件与具有双凹陷AlGaN势垒层GaN HEMT器件的微波输出特性对比图。
微波特性仿真验证,在S波段,具有双凹陷AlGaN势垒层的GaN HEMT的最大功率附加效率和饱和输出功率密度均高于常规GaN HEMT的输出能力。
需要说明的是,上述实施例不以任何形式限制本发明,凡采用等同替换或等效变换的方式所获得的技术方案,均落在本发明的保护范围内。

Claims (7)

1.一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,结构自下而上包括:半绝缘衬底(1)、AlN成核层(2)、GaN缓冲层(3)和AlGaN势垒层(4),其特征在于,所述AlGaN势垒层(4)的上表面的两侧分别设有源电极(5)和漏电极(6)、源电极(5)和漏电极(6)之间且靠近源电极(5)处设有栅电极(7),在栅电极(7)的源侧区域一部分AlGaN势垒层(4)向下凹陷形成凹陷栅源势垒层区域(8),在栅电极(7)的漏侧区域一部分AlGaN势垒层(4)向下凹陷形成凹陷栅漏势垒层区域(9)。
2.根据权利要求1所述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,所述凹陷栅源势垒层区域(8)和凹陷栅漏势垒层区域(9)均是通过在AlGaN势垒层(4)的表面进行光刻、刻蚀形成的。
3.根据权利要求2所述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,所述凹陷栅源势垒层区域(8)的长度为0.5μm、刻蚀深度为5nm,所述凹陷栅漏势垒层区域(9)的长度为0.6μm、刻蚀深度为4nm。
4.根据权利要求3所述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,所述栅电极(7)的长度为1.0μm,栅源间距为1μm,栅漏间距为2.5μm。
5.根据权利要求1所述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,所述栅电极(7)通过肖特基接触与AlGaN势垒层(4)相连,所述源电极(5)和漏电极(6)均通过欧姆接触与AlGaN势垒层(4)相连。
6.根据权利要求1所述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,所述GaN缓冲层(3)具有n型电阻特性或半绝缘特性。
7.根据权利要求1所述的具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管,其特征在于,所述半绝缘衬底(1)为硅衬底、碳化硅衬底或蓝宝石衬底。
CN201710242816.9A 2017-04-14 2017-04-14 一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管 Pending CN107017293A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710242816.9A CN107017293A (zh) 2017-04-14 2017-04-14 一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710242816.9A CN107017293A (zh) 2017-04-14 2017-04-14 一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管

Publications (1)

Publication Number Publication Date
CN107017293A true CN107017293A (zh) 2017-08-04

Family

ID=59445697

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710242816.9A Pending CN107017293A (zh) 2017-04-14 2017-04-14 一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管

Country Status (1)

Country Link
CN (1) CN107017293A (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107742643A (zh) * 2017-10-09 2018-02-27 山东大学 提高AlGaN/GaN异质结场效应晶体管线性度的方法
CN107968052A (zh) * 2017-11-24 2018-04-27 中国计量大学 一种提高击穿电压的阶梯状AlGaN外延新型AlGaN/GaN-HEMT设计方法
CN110112208A (zh) * 2019-06-06 2019-08-09 电子科技大学 一种高频低结温的GaN异质结场效应晶体管
CN111081763A (zh) * 2019-12-25 2020-04-28 大连理工大学 一种场板下方具有蜂窝凹槽势垒层结构的常关型hemt器件及其制备方法
CN112786686A (zh) * 2021-02-08 2021-05-11 西安电子科技大学 一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005203544A (ja) * 2004-01-15 2005-07-28 Mitsubishi Electric Corp 窒化物半導体装置とその製造方法
WO2009116223A1 (ja) * 2008-03-21 2009-09-24 パナソニック株式会社 半導体装置
CN106298909A (zh) * 2016-08-09 2017-01-04 电子科技大学 一种hemt器件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005203544A (ja) * 2004-01-15 2005-07-28 Mitsubishi Electric Corp 窒化物半導体装置とその製造方法
WO2009116223A1 (ja) * 2008-03-21 2009-09-24 パナソニック株式会社 半導体装置
CN106298909A (zh) * 2016-08-09 2017-01-04 电子科技大学 一种hemt器件

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107742643A (zh) * 2017-10-09 2018-02-27 山东大学 提高AlGaN/GaN异质结场效应晶体管线性度的方法
CN107968052A (zh) * 2017-11-24 2018-04-27 中国计量大学 一种提高击穿电压的阶梯状AlGaN外延新型AlGaN/GaN-HEMT设计方法
CN110112208A (zh) * 2019-06-06 2019-08-09 电子科技大学 一种高频低结温的GaN异质结场效应晶体管
CN111081763A (zh) * 2019-12-25 2020-04-28 大连理工大学 一种场板下方具有蜂窝凹槽势垒层结构的常关型hemt器件及其制备方法
CN111081763B (zh) * 2019-12-25 2021-09-14 大连理工大学 一种场板下方具有蜂窝凹槽势垒层结构的常关型hemt器件及其制备方法
CN112786686A (zh) * 2021-02-08 2021-05-11 西安电子科技大学 一种具有势垒层表面P型掺杂的AlGaN/GaN高电子迁移率晶体管

Similar Documents

Publication Publication Date Title
CN1950945B (zh) 具有多个场板的宽能带隙晶体管
CN107017293A (zh) 一种具有双凹陷AlGaN势垒层的AlGaN/GaN异质结场效应晶体管
US8592867B2 (en) Wide bandgap HEMTS with source connected field plates
US7388236B2 (en) High efficiency and/or high power density wide bandgap transistors
US8933486B2 (en) GaN based HEMTs with buried field plates
US7566918B2 (en) Nitride based transistors for millimeter wave operation
US7161194B2 (en) High power density and/or linearity transistors
CN105283958B (zh) GaN HEMT的共源共栅结构
US7126426B2 (en) Cascode amplifier structures including wide bandgap field effect transistor with field plates
US20070235761A1 (en) Wide bandgap transistor devices with field plates
CN101414629B (zh) 源场板高电子迁移率晶体管
CN104299999B (zh) 一种具有复合栅介质层的氮化镓基异质结场效应晶体管
US20220376105A1 (en) Field effect transistor with selective channel layer doping
CN108878524A (zh) 一种氮化镓基高电子迁移率晶体管
CN207611772U (zh) 一种大栅宽的GaN基微波功率器件
WO2023097520A1 (zh) 半导体器件及电子设备
WO2023197213A1 (zh) 半导体器件及其工作方法、电子设备
DeSalvo Silicon carbide static induction transistors
CN103762235A (zh) 基于超结漏场板的AlGaN/GaN高压器件及其制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170804

RJ01 Rejection of invention patent application after publication