CN112786572A - 半导体装置封装 - Google Patents

半导体装置封装 Download PDF

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Publication number
CN112786572A
CN112786572A CN202011215794.5A CN202011215794A CN112786572A CN 112786572 A CN112786572 A CN 112786572A CN 202011215794 A CN202011215794 A CN 202011215794A CN 112786572 A CN112786572 A CN 112786572A
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layer
conductive
semiconductor device
device package
encapsulant
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詹雅芳
蒋源峰
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

半导体装置封装包含重新分布层、多个导电柱、增强层及包封物。所述导电柱与所述第一重新分布层直接接触。所述增强层围绕所述导电柱的侧表面。所述包封物包封所述第一重新分布层及所述增强层。所述导电柱通过所述增强层彼此分隔开。

Description

半导体装置封装
技术领域
本公开涉及一种半导体装置封装，且更确切地说，涉及一种具有多个导电柱的封装结构。
背景技术
在三维集成电路的扇出叠层封装(Package-on-Package)技术中，硅通孔或铜柱通常用作堆叠封装的电气通道。然而，制造硅通孔或铜柱的成本很高。此外，铜柱的高度可能由于制造工艺而彼此不同，并且高度差可高达30μm或更多。因此，堆叠封装之间可能存在短路故障。
发明内容
在一些实施例中，半导体装置封装包含第一重新分布层、多个导电柱、增强层及包封物。所述第一重新分布层具有第一表面，并且所述导电柱与所述第一重新分布层的所述第一表面直接接触。所述增强层围绕所述导电柱的侧表面。所述包封物包封所述增强层并且与所述第一重新分布层的所述第一表面接触。所述导电柱通过所述增强层彼此分隔开。
在一些实施例中，半导体装置封装包含电连接构件、第一电子组件、包封物及第一重新分布层。所述电连接构件包含增强层及穿过所述增强层的多个导电柱。所述包封物包封所述第一电子组件及所述电连接构件。所述第一重新分布层安置于所述包封物的顶部表面上并且电连接到所述导电柱中的至少一者。所述导电柱的底部表面与所述增强层的底部表面及所述包封物的底部表面共面。
在一些实施例中，制造半导体装置封装的方法包含制造电连接构件。所述电连接构件通过以下步骤制造：提供第一载体，其中第一导电层安置于所述第一载体的表面上；在所述第一导电层上形成多个第一导电柱；在所述第一导电层上提供介电材料，其中所述介电材料填充在所述第一导电柱之间；及移除所述第一载体。
附图说明
图1说明根据本公开的一些实施例的半导体装置封装的截面图。
图2说明根据本公开的一些实施例的半导体装置封装的截面图。
图3说明根据本公开的一些实施例的半导体装置封装的截面图。
图4说明根据本公开的一些实施例的半导体装置封装的截面图。
图5说明根据本公开的一些实施例的半导体装置封装的截面图。
图6说明根据本公开的一些实施例的半导体装置封装的截面图。
图7A、7B、7C、7D、7E及7F说明根据本公开的一些实施例的制造电连接构件的方法的一或多个阶段。
图8A、8B、8C、8D、8E、8F、8G、8H、8I及8J说明根据本公开的一些实施例的制造电连接构件的方法的一或多个阶段。
图9A、9B、9C、9D、9E、9F、9G、9H、9I及9J说明根据本公开的一些实施例的制造半导体装置封装的方法的一或多个阶段。
图10A、10B、10C、10D、10E、10F、10G、10H、10I及10J说明根据本公开的一些实施例的制造半导体装置封装的方法的一或多个阶段。
贯穿图式及详细描述使用共同参考标号来指示相同或相似组件。据以下实施方式结合随附图式，将更容易理解本公开的内容。
具体实施方式
出于进一步解释本公开的范围的目的，上述说明及以下详细描述为示范性的。将在后续描述及附图中说明与本公开有关的其它目标及优点。
除非另外规定，否则例如“上”、“下”、“向上”、“左”、“右”、“向下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“高于”、“低于”、“上部”、“上方”、“下方”等空间描述是相对于图式中所示的定向指示的。应理解，本文中所使用的空间描述是出于说明的目的，并且本文中所描述的结构的实际实施方案可以任何定向或方式在空间上布置，其限制条件为本公开的实施例的优点不会因此布置而有偏差。
本公开描述在不使用硅通孔(TSV)作为电气通道的情况下制造半导体装置封装的技术。在根据本公开的一些实施例中，预先形成包含多个导电柱的电连接构件并且所述电连接构件用作电气通道。导电柱由增强层覆盖，因此可避免在应用模塑料的步骤期间导电柱的潜在移位。另外，在根据本公开的一些实施例中，可通过研磨电连接构件来控制导电柱的高度，从而可避免在比较实施例中由于导电柱或TSV的高度差引起的短路故障。
图1说明根据本公开的一些实施例的半导体装置封装1的截面图。半导体装置封装1可包括电连接构件10、重新分布层11、包封物12、第一电子组件15、第二电子组件17及第三电子组件18。
电连接构件10可包含多个导电柱13及增强层14。举例来说，导电柱13可包含铜或其它金属，或金属合金，或其它导电材料。在一些实施例中，导电柱13是铜柱。增强层14可为介电层。增强层14可由阻焊剂、味之素堆积膜(Ajinomoto Build-up Film,ABF)，或其它介电材料制成。在一些实施例中，增强层14由具有较低热膨胀系数(CTE)的介电材料(例如，ABF)制成，举例来说，30ppm/℃或更低、25ppm/℃或更低、20ppm/℃或更低、18ppm/℃或更低，或15ppm/℃或更低，并且可减少半导体装置封装1的翘曲。在一些实施例中，导电柱13是铜柱，增强层14由ABF制成，并且半导体装置封装1具有减少的翘曲。增强层14围绕每个导电柱13的侧表面，并且导电柱13由增强层14彼此分隔开。在图1所说明的实施例中，增强层14完全覆盖导电柱13的侧表面。因此，增强层14的厚度基本上等于导电柱13的高度。此外，导电柱13可穿过增强层14并且可从增强层14的第一表面142暴露，其中增强层14的第一表面142是基本上平坦的并且背对重新分布层11。
重新分布层11安置于电子构件10的增强层14上并且电连接导电柱13。如图1所示，增强层14的第二表面141可附接到重新分布层11的第一表面111且与所述第一表面接触，并且导电柱13与重新分布层11的第一表面111直接接触。
包封物12可围绕或包封电连接构件10的增强层14的侧表面及第一电子组件15。包封物12可与重新分布层11的第一表面111接触。举例来说，包封物12可包含基于酚醛的树脂、环氧基树脂、基于硅酮的树脂，或其它另一合适的包封物。还可包含合适的填料，例如粉末SiO2。在一些实施例中，增强层14可含有填料，并且增强层14中的填料可小于包封物12的填料。参考图1，包封物12可具有：第一表面121，所述第一表面附接到重新分布层11的第一表面111；及第二表面122，所述第二表面与第一表面121相对并且与电连接构件10的增强层14的第一表面142基本上共面。从增强层14的第一表面142暴露的导电柱13的表面132也可与包封物12的第二表面122共面。
第一电子组件15可为裸片或芯片，并且具有面对重新分布层11的有源表面。在一些实施例中，电连接构件10(或两个或多于两个电连接构件10)限定用于容纳第一电子组件15的空腔。换句话说，第一电子组件15容纳在由电连接构件(即，电连接构件的增强层14)限定的空腔内，并且包封物12填充在空腔内并覆盖第一电子组件15。第一电子组件15可电连接到重新分布层11。第一电子组件15可具有后表面151(例如，无源表面)，所述后表面背对重新分布层11并且与增强层14的第二表面141共面。在一些实施例中，例如散热层或金属层的附加层16可附接到第一电子组件15的表面151。
在一些实施例中，半导体装置封装还可包含安装在重新分布层11的第二表面112上的一或多个电子组件，例如DRAM或电容器。在图1所说明的实施例中，半导体装置封装还包含安装在重新分布层11的第二表面112上的第二电子组件17和第三电子组件18，所述第二表面与重新分布层11的第一表面111相对。
图2说明根据本公开的一些实施例的半导体装置封装1'的截面图。图2所示的半导体装置封装1'在某些方面类似于图1所示的半导体装置封装1，不同之处在于，在图2中，多个焊球19安置于电连接构件10的增强层14的第一表面142上并且电连接到导电柱13。因此，在至少一些实施例中，半导体装置封装1'还包含多个焊球19，所述多个焊球安置于电连接构件10的增强层14的第一表面142上并且电连接到导电柱13。
图3说明根据本公开的一些实施例的半导体装置封装1”的截面图。图3所示的半导体装置封装1”在某些方面类似于图1所示的半导体装置封装1，不同之处在于，在图3中，附加的重新分布层100安置于电连接构件10的增强层14的第一表面142上并且电连接到导电柱13。因此，在至少一些实施例中，半导体装置封装1”还包含重新分布层100，所述重新分布层安置于电连接构件20的增强层14的第一表面142上并且电连接到导电柱13。
图4说明根据本公开的一些实施例的半导体装置封装2的截面图。半导体装置封装2可包含电连接构件20、重新分布层21、包封物22、第一电子组件25、第二电子组件27及第三电子组件28。
电连接构件20可包含多个导电柱23及增强层24。举例来说，导电柱23可包含铜或其它金属，或金属合金，或其它导电材料。在一些实施例中，导电柱23是铜柱。增强层24可为介电层。增强层24可由防焊剂或ABF，或其它介电材料制成。类似于上述用于图1的半导体装置封装1的那些增强层，增强层24可由具有较低CTE的介电材料制成并且可减少半导体装置封装2的翘曲。在一些实施例中，导电柱23是铜柱且增强层24由ABF制成，并且半导体装置封装2具有减少的翘曲。导电柱23可包含第一柱部分231及第二柱部分232。第一柱部分231的直径可以与第二柱部分232的直径基本上相同或不同于第二柱部分232的直径。在一些实施例中，第一柱部分231的直径大于第二柱部分232的直径。增强层24围绕每个第一柱部分231的侧表面，并且第一柱部分231由增强层24彼此分隔开。此外，第一柱部分231可穿过增强层24并且可从电子构件20的增强层24的第一表面242暴露，其中增强层24的第一表面242是基本上平坦的并且背对重新分布层21。另外，第二柱部分232与第一柱部分231直接接触并且不由增强层24覆盖。
重新分布层21安置于电子构件20上并且电连接导电柱23。如图4中所示，第二柱部分231附接到重新分布层21的第一表面211并且与重新分布层21的第一表面211接触。也就是说，电子构件20的导电柱23与重新分布层21的第一表面211直接接触。
包封物22可以围绕或包封增强层24的侧表面，及电连接构件20的第二柱部分232的侧表面，及第一电子组件25。举例来说，包封物12可包含基于酚醛的树脂、环氧基树脂、基于硅酮的树脂，或其它另一合适的包封物。还可包含合适的填料，例如粉末SiO2。在一些实施例中，增强层24可含有填料，并且增强层24中的填料可小于包封物22的填料。参考图4，包封物22可具有：第一表面221，所述第一表面附接到重新分布层21的第一表面211；及第二表面222，所述第二表面与表面211相对并且与电连接构件20的增强层24的第一表面242基本上共面。也就是说，第一柱部分231的表面2312也可与包封物22的第二表面222共面。
第一电子组件25可为裸片或芯片，并且具有面对重新分布层21的有源表面。在一些实施例中，电连接构件20(或两个或多于两个电连接构件20)限定用于容纳第一电子组件25的空腔。换句话说，第一电子组件25容纳在由电连接构件(即，电连接构件的增强层24)限定的空腔内，并且包封物22填充在空腔内并覆盖第一电子组件25。第一电子组件25可电连接到重新分布层21。
第一电子组件25可具有后表面(例如，无源表面)，所述后表面与电子组件25的有源表面相对。在一些实施例中，类似于图1所说明的那些实施例，第一电子组件25的后表面可与增强层24的第一表面242共面。在图2所说明的其它实施例中，第一电子组件25的后表面可高于增强层24的第一表面242，并且例如散热层或金属层的附加层26可附接到第一电子组件25的后表面。层26具有第一表面261及与第一表面261相对的第二表面262。层26的第一表面261与第一电子组件25的后表面接触。层26的第二表面262背对重新分布层21，并且可与电连接构件20的增强层24的第一表面242基本上共面。层26可横向地延伸以接触电连接构件20。
可为DRAM及/或电容器的第一电子组件27及第三电子组件28安装在重新分布层21的第二表面212上，所述第二表面与重新分布层21的第一表面211相对。
图5说明根据本公开的一些实施例的半导体装置封装2'的截面图。图5所示的半导体装置封装2'在某些方面类似于图4所示的半导体装置封装2，不同之处在于，在图5中，多个焊球29安置于电连接构件20的增强层24的第一表面242上并且电连接到导电柱23的第一柱部分231。因此，在至少一些实施例中，半导体装置封装2'还包含多个焊球29，所述多个焊球安置于电连接构件20的增强层24的第一表面242上并且电连接到导电柱23。
图6说明根据本公开的一些实施例的半导体装置封装2”的截面图。图6所示的半导体装置封装2”在某些方面类似于图4所示的半导体装置封装2，不同之处在于，在图6中，附加的重新分布层200安置于电连接构件20的增强层24的第一表面242上并且电连接到导电柱23的第一柱部分231。因此，在至少一些实施例中，半导体装置封装2”还包含重新分布层200，所述重新分布层安置于电连接构件20的增强层24的第一表面242上并且电连接到导电柱23。
图7A、7B、7C、7D、7E及7F说明根据本公开的一些实施例的制造电连接构件的方法的一或多个阶段。
在图7A中，提供载体5(例如，预浸料)。载体5具有安置于载体的第一表面501上的导电层50，并且可具有安置于相对表面上的导电层(未标示)。导电层50是金属层，所述金属层包含铜或其它金属，或金属合金，或其它导电材料。
如图7B中所示，光致抗蚀剂层51形成于载体5的导电层50上。光致抗蚀剂层51包含通孔511。
如图7C中所示，导电柱33形成于光致抗蚀剂层51的通孔511中。导电柱33可由铜或其它金属，或金属合金，或其它导电材料制成。导电柱33可与导电层50集成。
如图7D中所示，光致抗蚀剂层51从载体5移除。
如图7E中所示，增强层34通过使用介电材料形成于导电层50上以围绕导电柱33。介电材料可为防焊剂。介电材料填充在导电柱33之间，因此所得增强层34围绕每个导电柱33的侧表面并且导电柱13通过增强层34彼此分隔开。此外，增强层34还覆盖导电层50。
如图7F中所示，移除载体5。在移除载体5之后，电连接构件30形成及附接于导电层50上，所述电连接构件包含多个导电柱33及围绕导电柱33的侧表面的增强层34。
图8A、8B、8C、8D、8E、8F、8G、8H、8I及8J说明根据本公开的一些实施例的制造电连接构件40的方法的一或多个阶段。
在图8A中，提供载体6(例如，预浸料)。载体6具有安置于载体的第一表面601上的导电层60，并且可具有安置于相对表面上的导电层(未标示)。导电层60是金属层，所述金属层包含铜或其它金属，或金属合金，或其它导电材料。
如图8B中所示，第一光致抗蚀剂层61形成于载体6的导电层60上。第一光致抗蚀剂层61包含通孔611及空腔612。
如图8C中所示，第一柱部分431形成于第一光致抗蚀剂层61的通孔611中，并且另一导电层46形成于第一光致抗蚀剂层61的空腔612中。第一柱部分431及另一导电层46可由相同或不同材料制成，包含铜或其它金属，或金属合金，或其它导电材料。第一柱部分431可与导电层60集成。此外，另一导电层46也可与导电层60集成。
如图8D中所示，第一光致抗蚀剂层61从载体6移除。
如图8E中所示，增强层44通过使用介电材料形成于导电层60上以包封第一柱部分431。介电材料可为ABF。介电材料填充在第一柱部分431之间，因此所得增强层44围绕每个第一柱部分431的侧表面并且第一柱部分431通过增强层44彼此分隔开。增强层43还围绕导电层46的侧表面或外周。增强层44覆盖导电层60。另外，增强层44可覆盖第一柱部分431的顶部及导电层46的顶部。
如图8F中所示，例如通过研磨移除增强层44的一部分，因此第一柱部分431及导电层46可从增强层44的表面441暴露。第一柱部分431及导电层46可同时与增强层44一起接地。在一些实施例中，在研磨之后，第一柱部分431的顶部、导电层46的顶部及增强层44的顶部共面。
如图8G中所示，第二光致抗蚀剂层63形成于增强层44及导电层46上，第二光致抗蚀剂层63包含多个通孔631，所述通孔中的每一者与第一柱部分431中的相应一者对准。通孔631的直径可与相应第一柱部分431的直径相同或不同。在一些实施例中，通孔631的直径可小于相应第一柱部分431的直径。
如图8H中所示，第二柱部分432形成于第二光致抗蚀剂层63的通孔631中。所得第二导电柱33具有由通孔631限定的形状。第二柱部分432可由铜或其它金属，或金属合金，或其它导电材料制成。导电柱33可与第一柱部分431集成。
如图8I中所示，移除第二光致抗蚀剂层63。另外，由于第一柱部分431及第二柱部分432在不同阶段形成，因此可在第一柱部分431与第二柱部分432之间存在界面。
如图8J中所示，移除载体6。在移除载体6之后，电连接构件形成及附接于导电层60上，所述电连接构件包含多个导电柱43、增强层44及导电层46。每个导电柱43包含第一柱部分431及第二柱部分432。增强层44围绕第一柱部分431的侧表面及导电层46的侧表面(或外周)。
图9A、9B、9C、9D、9E、9F、9G、9H、9I及9J说明根据本公开的一些实施例的制造半导体封装的方法的一或多个阶段。
参考图9A，提供在载体的顶部表面上具有导电层70的载体7。根据图7A、7B、7C、7D、7E及7F中所说明的方法制备电连接构件30，并且芯片35布置于载体7的导电层70上，如图9A中所示。与电连接构件30集成的导电层50附接到载体7的导电层70。芯片35具有有源表面及与所述有源表面相对的后表面。电触点355安置于芯片35的有源表面上。芯片35的后表面附接在载体7的导电层70上。
如图9B中所示，包封物32施加于载体7的导电层70、电连接构件30及芯片35上。包封物32包封电连接构件30及芯片35。
如图9C中所示，例如通过研磨移除包封物32的一部分，因此电连接构件30的增强层34具有表面341且包封物32具有表面321，并且表面341与表面321基本上共面。此外，导电柱33从增强层34的表面341暴露，并且芯片35的电触点355从包封物32的表面321暴露。
如图9D中所示，重新分布层31安置于电连接构件30及包封物32上，并且电连接到导电柱33及芯片35的电触点355。重新分布层31具有表面311，所述表面附接到电连接构件30的增强层34的表面341及包封物32的表面321。
如图9E中所示，多个焊球315安装在重新分布层31的与表面311相对的表面312上。
如图9F中所示，电子组件37及38安装在重新分布层31的表面312上并且电连接到焊球315。
如图9G中所示，条带317施加在重新分布层31的表面312上，并且覆盖电子组件37及38及焊球315。
如图9H中所示，移除载体7及载体7的导电层70。
如图9I中所示，例如通过研磨移除导电层50。在研磨导电层50之后，电连接构件30具有基本上平坦的表面(即，增强层34的表面342及导电柱33的表面332为平坦的且共面)，包封物32具有基本上平坦的表面322。表面342及表面332与表面322基本上共面。另外，芯片35的后表面与增强层34的表面342基本上共面。
如图9J中所示，移除条带317。此外，多个焊球39安装及电连接到导电柱33的表面332。
图10A、10B、10C、10D、10E、10F、10G、10H、10I及10J说明根据本公开的一些实施例的制造半导体封装的方法的一或多个阶段。
如图10A中所示，提供在载体的顶部表面上具有导电层80的载体8。根据图8A、8B、8C、8D、8E、8F、8G、8H、8I及8J中说明的方法制备的电连接构件40布置于载体8的导电层80上。芯片45布置于电连接构件40的导电层46上。与电连接构件40集成的导电层60附接到载体8的导电层80。芯片45具有有源表面及与所述有源表面相对的后表面。电触点455安置于芯片45的有源表面上。芯片45的后表面附接在载体8的导电层80上。
如图10B中所示，包封物42施加于载体8的导电层80、电连接构件40及芯片45上。因此，包封物42包封载体8、电连接构件40及芯片45。
如图10C中所示，例如通过研磨移除包封物42的一部分，因此包封物42具有表面421。此外，导电柱43的第二柱部分432及芯片45的电触点455从包封物42的表面421暴露。
如图10D中所示，重新分布层41安置于电连接构件40及包封物42上，并且电连接到导电柱43的第二柱部分432及芯片45的连接件455。重新分布层41具有附接到包封物42的表面421的表面411。
如图10E中所示，多个焊球415安装在重新分布层41的表面412上，表面412与表面411相对。
如图10F中所示，电子组件47及48安装在重新分布层41的表面412上并且电连接到焊球415。
如图10G中所示，条带417施加在重新分布层41的表面412上，并且覆盖电子组件47及48及焊球415。
如图10H中所示，移除载体8及载体8的导电层80。
如图10I中所示，例如通过研磨移除导电层60。在研磨导电层60之后，电连接构件40具有基本上平坦的表面(即，增强层44的表面442及导电柱43的表面4312为平坦的且共面)，并且包封物42具有基本上平坦的表面422。表面442与表面422基本上共面。另外，导电层46可具有表面462，所述表面与增强层42的表面442基本上共面。
如图10J中所示，移除条带417。此外，多个焊球49安装及电连接到导电柱43的第一柱部分431。
如本文中所使用，例如“内”、“内部”、“外”、“外部”、“顶部”、“底部”、“前”、“后”、“上”、“向上地”、“下”、“向下地”、“垂直”、“垂直地”、“横向”、“横向地”、“上方”及“下方”的相对术语是指一组组件相对于彼此的定向；此定向根据附图，但在制造或使用期间不需要。
如本文中所使用，除非上下文另外明确规定，否则单数术语“一”、“一个”及“所述”可包含多个提及物。
如本文中所使用，术语“连接(connect)”、“连接的(connected)”及“连接(connection)”指操作耦合或链接。连接组件可例如通过另一组组件直接地或间接地彼此耦合。
如本文中所使用，术语“导电(conductive)”、“导电(electrically conductive)”及“导电性”是指传输电流的能力。导电材料通常指示展示对于电流流动的极少或零对抗的那些材料。导电性的一个量度为西门子每米(S/m)。通常，导电材料为导电性大于约104S/m，例如，至少105S/m或至少106S/m的一种材料。材料的导电性有时可随温度而变化。除非另外指定，否则材料的导电性是在室温下测量。
如本文中所使用，术语“大致”、“基本上”、“大量”及“大约”指相当大的程度或范围。当结合事件或情况使用时，术语可指事件或情况准确发生的情况以及事件或情况紧密近似地发生的情况，例如当解释本文中所描述的制造方法的典型容限电平时。举例来说，当结合数值使用时，术语可指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％，那么可认为所述两个数值“基本上”相同或相等。
如果两个表面之间的位移不超过5μm、不超过2μm、不超过1μm或不超过0.5μm，那么可认为这两个表面是共面的或基本上共面。
如果表面的最高点与最低点之间的差值不超过5μm、不超过2μm、不超过1μm或不超过0.5μm，那么可认为表面是平面的或基本上平面。
此外，有时在本文中以范围格式呈现量、比率及其它数值。应理解，此类范围格式是为便利及简洁起见使用，且应灵活地解释为包含明确地指定为范围限制的数值以及涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值及子范围一般。
在一些实施例的描述中，提供于另一组件“上”或“上面”的组件可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个中间组件位于前一组件与后一组件之间的情况。
尽管已参考本公开的特定实施例描述并说明本公开，但这些描述及说明并不限制本公开。本领域技术人员应理解，可在不脱离如由所附权利要求书界定的本公开的真实精神及范围的情况下，作出各种改变且取代等效物。
如在各个实例实施例中展示的结构及方法的构造及布置仅仅是说明性的。因此，所有这些修改预期包含在本公开的范围内。任何过程或方法步骤的顺序或次序可根据替代实施例变化或重新排序。可在不脱离本公开的范围的情况下对实例实施例的设计、操作条件及布置作出其它替代、修改、改变及省略。

Claims (20)

1.一种半导体装置封装，其包括：
第一重新分布层，其具有第一表面；
多个导电柱，其与所述第一重新分布层的所述第一表面直接接触；
增强层，其围绕所述导电柱的侧表面；及
包封物，其包封所述增强层并且与所述第一重新分布层的所述第一表面接触；
其中所述导电柱通过所述增强层彼此分隔开。
2.根据权利要求1所述的半导体装置封装，其中所述增强层含有比所述包封物的填料小的填料。
3.根据权利要求1所述的半导体装置封装，其中所述增强层具有背对所述第一重新分布层的第一表面，并且其中所述导电柱从所述增强层的所述第一表面暴露。
4.根据权利要求3所述的半导体装置封装，其中从所述增强层的所述第一表面暴露的所述导电柱中的至少一者连接到焊球。
5.根据权利要求1所述的半导体装置封装，其中所述增强层限定用于容纳第一电子组件的空腔，并且其中所述第一电子组件具有背对所述第一重新分布层的第一表面。
6.根据权利要求1所述的半导体装置封装，其中所述第一重新分布层进一步包括与所述第一重新分布层的所述第一表面相对的第二表面，并且其中第二电子组件安装到所述第一重新分布层的所述第二表面。
7.根据权利要求1所述的半导体装置封装，其中所述增强层接触所述第一重新分布层的所述第一表面。
8.根据权利要求1所述的半导体装置封装，其中所述导电柱中的每一者具有第一柱部分及第二柱部分，其中所述第二柱部分安置于所述第一重新分布层的所述第一表面上并且所述第二柱部分的侧表面由所述包封物覆盖，并且其中所述第一柱部分与所述第二柱部分直接接触并且所述第一柱部分的侧表面由所述增强层覆盖。
9.根据权利要求8所述的半导体装置封装，其中所述第一柱部分的直径不同于所述第二柱部分的直径。
10.根据权利要求5所述的半导体装置封装，进一步包括附接到所述第一电子组件的所述第一表面的金属层或散热层。
11.根据权利要求5所述的半导体装置封装，进一步包括附接到所述第一电子组件的所述第一表面的金属层或散热层，其中所述金属层或所述散热层具有背对所述第一重新分布层的第一表面，并且其中所述金属层或所述散热层的所述第一表面与所述增强层的第一表面共面。
12.一种半导体装置封装，其包括：
电连接构件，其包括增强层及穿过所述增强层的多个导电柱；
第一电子组件；
包封物，其包封所述第一电子组件及所述电连接构件；及
第一重新分布层，其安置于所述包封物的顶部表面上并且电连接到所述导电柱中的至少一者；
其中所述导电柱的底部表面与所述增强层的底部表面及所述包封物的底部表面共面。
13.根据权利要求12所述的半导体装置封装，进一步包括安置于所述包封物的底部表面上并且电连接到所述导电柱中的至少一者的焊球或第二重新分布层。
14.根据权利要求12所述的半导体装置封装，进一步包括安置于所述第一重新分布层的所述顶部表面上的第二电子组件。
15.根据权利要求12所述的半导体装置封装，其中所述导电柱中的每一者具有第一柱部分及第二柱部分，并且其中所述第二柱部分安置于所述第一重新分布层的所述底部表面及由所述包封物覆盖的所述第二柱部分的侧表面上，并且其中所述第一柱部分与所述第二柱部分直接接触并且所述第一柱部分的侧表面由所述增强层覆盖。
16.一种制造半导体装置封装的方法，包括通过以下步骤制备电连接构件：
提供第一载体，其中第一导电层安置于所述第一载体的表面上；
在所述第一导电层上形成多个第一导电柱；
在所述第一导电层上提供介电材料，其中所述介电材料填充在所述第一导电柱之间；及
移除所述第一载体。
17.根据权利要求16所述的方法，其包括：
将所述电连接构件及第一电子组件安置于第二载体上；
在所述载体上形成包封物，其中所述包封物包封所述电连接构件及所述第一电子组件，并且暴露所述连接构件的所述第一导电柱的顶部表面；
在所述包封物上形成重新分布层，其中所述重新分布层电连接到所述第一导电柱；
移除所述第二载体；及
移除所述电连接构件的所述第一导电层。
18.根据权利要求16所述的方法，在移除所述第一载体之前在所述第一导电柱中的相应一者上形成第二导电柱。
19.根据权利要求18所述的方法，其中在形成所述第一导电柱时，在所述第一导电层上形成第二导电层。
20.根据权利要求19所述的方法，其进一步包括：
将所述电连接构件及第一电子组件安置于第二载体上；
在所述载体上形成包封物，其中所述包封物包封所述电连接构件及所述第一电子组件，并且暴露所述电连接构件的所述第二导电柱的顶部表面；
在所述包封物上形成重新分布层，其中所述重新分布层电连接到所述第二导电柱；
移除所述第二载体；及
移除所述电连接构件的所述第一导电层。
CN202011215794.5A 2019-11-05 2020-11-04 半导体装置封装 Pending CN112786572A (zh)

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